1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
13 #include <rte_malloc.h>
14 #include <ethdev_driver.h>
16 #include <rte_bus_pci.h>
17 #include <rte_common.h>
18 #include <rte_kvargs.h>
19 #include <rte_rwlock.h>
20 #include <rte_spinlock.h>
21 #include <rte_string_fns.h>
22 #include <rte_alarm.h>
23 #include <rte_cycles.h>
25 #include <mlx5_glue.h>
26 #include <mlx5_devx_cmds.h>
27 #include <mlx5_common.h>
28 #include <mlx5_common_os.h>
29 #include <mlx5_common_mp.h>
30 #include <mlx5_malloc.h>
32 #include "mlx5_defs.h"
34 #include "mlx5_utils.h"
35 #include "mlx5_rxtx.h"
38 #include "mlx5_autoconf.h"
40 #include "mlx5_flow.h"
41 #include "mlx5_flow_os.h"
42 #include "rte_pmd_mlx5.h"
44 #define MLX5_ETH_DRIVER_NAME mlx5_eth
46 /* Driver type key for new device global syntax. */
47 #define MLX5_DRIVER_KEY "driver"
49 /* Device parameter to enable RX completion queue compression. */
50 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
52 /* Device parameter to enable padding Rx packet to cacheline size. */
53 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
55 /* Device parameter to enable Multi-Packet Rx queue. */
56 #define MLX5_RX_MPRQ_EN "mprq_en"
58 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
59 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
61 /* Device parameter to configure log 2 of the stride size for MPRQ. */
62 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
64 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
65 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
67 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
68 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
70 /* Device parameter to configure inline send. Deprecated, ignored.*/
71 #define MLX5_TXQ_INLINE "txq_inline"
73 /* Device parameter to limit packet size to inline with ordinary SEND. */
74 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
76 /* Device parameter to configure minimal data size to inline. */
77 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
79 /* Device parameter to limit packet size to inline with Enhanced MPW. */
80 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
83 * Device parameter to configure the number of TX queues threshold for
84 * enabling inline send.
86 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
89 * Device parameter to configure the number of TX queues threshold for
90 * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
92 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
94 /* Device parameter to enable multi-packet send WQEs. */
95 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
98 * Device parameter to force doorbell register mapping
99 * to non-cahed region eliminating the extra write memory barrier.
101 #define MLX5_TX_DB_NC "tx_db_nc"
104 * Device parameter to include 2 dsegs in the title WQEBB.
105 * Deprecated, ignored.
107 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
110 * Device parameter to limit the size of inlining packet.
111 * Deprecated, ignored.
113 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
116 * Device parameter to enable Tx scheduling on timestamps
117 * and specify the packet pacing granularity in nanoseconds.
119 #define MLX5_TX_PP "tx_pp"
122 * Device parameter to specify skew in nanoseconds on Tx datapath,
123 * it represents the time between SQ start WQE processing and
124 * appearing actual packet data on the wire.
126 #define MLX5_TX_SKEW "tx_skew"
129 * Device parameter to enable hardware Tx vector.
130 * Deprecated, ignored (no vectorized Tx routines anymore).
132 #define MLX5_TX_VEC_EN "tx_vec_en"
134 /* Device parameter to enable hardware Rx vector. */
135 #define MLX5_RX_VEC_EN "rx_vec_en"
137 /* Allow L3 VXLAN flow creation. */
138 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
140 /* Activate DV E-Switch flow steering. */
141 #define MLX5_DV_ESW_EN "dv_esw_en"
143 /* Activate DV flow steering. */
144 #define MLX5_DV_FLOW_EN "dv_flow_en"
146 /* Enable extensive flow metadata support. */
147 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
149 /* Device parameter to let the user manage the lacp traffic of bonded device */
150 #define MLX5_LACP_BY_USER "lacp_by_user"
152 /* Activate Netlink support in VF mode. */
153 #define MLX5_VF_NL_EN "vf_nl_en"
155 /* Enable extending memsegs when creating a MR. */
156 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
158 /* Select port representors to instantiate. */
159 #define MLX5_REPRESENTOR "representor"
161 /* Device parameter to configure the maximum number of dump files per queue. */
162 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
164 /* Configure timeout of LRO session (in microseconds). */
165 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
168 * Device parameter to configure the total data buffer size for a single
169 * hairpin queue (logarithm value).
171 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
173 /* Flow memory reclaim mode. */
174 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
176 /* The default memory allocator used in PMD. */
177 #define MLX5_SYS_MEM_EN "sys_mem_en"
178 /* Decap will be used or not. */
179 #define MLX5_DECAP_EN "decap_en"
181 /* Device parameter to configure allow or prevent duplicate rules pattern. */
182 #define MLX5_ALLOW_DUPLICATE_PATTERN "allow_duplicate_pattern"
184 /* Device parameter to configure implicit registration of mempool memory. */
185 #define MLX5_MR_MEMPOOL_REG_EN "mr_mempool_reg_en"
187 /* Shared memory between primary and secondary processes. */
188 struct mlx5_shared_data *mlx5_shared_data;
190 /** Driver-specific log messages type. */
193 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
194 LIST_HEAD_INITIALIZER();
195 static pthread_mutex_t mlx5_dev_ctx_list_mutex;
196 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
197 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
198 [MLX5_IPOOL_DECAP_ENCAP] = {
199 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
205 .malloc = mlx5_malloc,
207 .type = "mlx5_encap_decap_ipool",
209 [MLX5_IPOOL_PUSH_VLAN] = {
210 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
216 .malloc = mlx5_malloc,
218 .type = "mlx5_push_vlan_ipool",
221 .size = sizeof(struct mlx5_flow_dv_tag_resource),
227 .per_core_cache = (1 << 16),
228 .malloc = mlx5_malloc,
230 .type = "mlx5_tag_ipool",
232 [MLX5_IPOOL_PORT_ID] = {
233 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
239 .malloc = mlx5_malloc,
241 .type = "mlx5_port_id_ipool",
243 [MLX5_IPOOL_JUMP] = {
244 .size = sizeof(struct mlx5_flow_tbl_data_entry),
250 .malloc = mlx5_malloc,
252 .type = "mlx5_jump_ipool",
254 [MLX5_IPOOL_SAMPLE] = {
255 .size = sizeof(struct mlx5_flow_dv_sample_resource),
261 .malloc = mlx5_malloc,
263 .type = "mlx5_sample_ipool",
265 [MLX5_IPOOL_DEST_ARRAY] = {
266 .size = sizeof(struct mlx5_flow_dv_dest_array_resource),
272 .malloc = mlx5_malloc,
274 .type = "mlx5_dest_array_ipool",
276 [MLX5_IPOOL_TUNNEL_ID] = {
277 .size = sizeof(struct mlx5_flow_tunnel),
278 .trunk_size = MLX5_MAX_TUNNELS,
281 .type = "mlx5_tunnel_offload",
283 [MLX5_IPOOL_TNL_TBL_ID] = {
286 .type = "mlx5_flow_tnl_tbl_ipool",
291 * The ipool index should grow continually from small to big,
292 * for meter idx, so not set grow_trunk to avoid meter index
293 * not jump continually.
295 .size = sizeof(struct mlx5_legacy_flow_meter),
299 .malloc = mlx5_malloc,
301 .type = "mlx5_meter_ipool",
304 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
310 .malloc = mlx5_malloc,
312 .type = "mlx5_mcp_ipool",
314 [MLX5_IPOOL_HRXQ] = {
315 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
321 .malloc = mlx5_malloc,
323 .type = "mlx5_hrxq_ipool",
325 [MLX5_IPOOL_MLX5_FLOW] = {
327 * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
328 * It set in run time according to PCI function configuration.
336 .per_core_cache = 1 << 19,
337 .malloc = mlx5_malloc,
339 .type = "mlx5_flow_handle_ipool",
341 [MLX5_IPOOL_RTE_FLOW] = {
342 .size = sizeof(struct rte_flow),
346 .malloc = mlx5_malloc,
348 .type = "rte_flow_ipool",
350 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID] = {
353 .type = "mlx5_flow_rss_id_ipool",
355 [MLX5_IPOOL_RSS_SHARED_ACTIONS] = {
356 .size = sizeof(struct mlx5_shared_action_rss),
362 .malloc = mlx5_malloc,
364 .type = "mlx5_shared_action_rss",
366 [MLX5_IPOOL_MTR_POLICY] = {
368 * The ipool index should grow continually from small to big,
369 * for policy idx, so not set grow_trunk to avoid policy index
370 * not jump continually.
372 .size = sizeof(struct mlx5_flow_meter_sub_policy),
376 .malloc = mlx5_malloc,
378 .type = "mlx5_meter_policy_ipool",
383 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
384 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
386 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 1024
389 * Decide whether representor ID is a HPF(host PF) port on BF2.
392 * Pointer to Ethernet device structure.
395 * Non-zero if HPF, otherwise 0.
398 mlx5_is_hpf(struct rte_eth_dev *dev)
400 struct mlx5_priv *priv = dev->data->dev_private;
401 uint16_t repr = MLX5_REPRESENTOR_REPR(priv->representor_id);
402 int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
404 return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_VF &&
405 MLX5_REPRESENTOR_REPR(-1) == repr;
409 * Decide whether representor ID is a SF port representor.
412 * Pointer to Ethernet device structure.
415 * Non-zero if HPF, otherwise 0.
418 mlx5_is_sf_repr(struct rte_eth_dev *dev)
420 struct mlx5_priv *priv = dev->data->dev_private;
421 int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
423 return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_SF;
427 * Initialize the ASO aging management structure.
430 * Pointer to mlx5_dev_ctx_shared object to free
433 * 0 on success, a negative errno value otherwise and rte_errno is set.
436 mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh)
442 sh->aso_age_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->aso_age_mng),
443 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
444 if (!sh->aso_age_mng) {
445 DRV_LOG(ERR, "aso_age_mng allocation was failed.");
449 err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_FLOW_HIT);
451 mlx5_free(sh->aso_age_mng);
454 rte_spinlock_init(&sh->aso_age_mng->resize_sl);
455 rte_spinlock_init(&sh->aso_age_mng->free_sl);
456 LIST_INIT(&sh->aso_age_mng->free);
461 * Close and release all the resources of the ASO aging management structure.
464 * Pointer to mlx5_dev_ctx_shared object to free.
467 mlx5_flow_aso_age_mng_close(struct mlx5_dev_ctx_shared *sh)
471 mlx5_aso_flow_hit_queue_poll_stop(sh);
472 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_FLOW_HIT);
473 if (sh->aso_age_mng->pools) {
474 struct mlx5_aso_age_pool *pool;
476 for (i = 0; i < sh->aso_age_mng->next; ++i) {
477 pool = sh->aso_age_mng->pools[i];
478 claim_zero(mlx5_devx_cmd_destroy
479 (pool->flow_hit_aso_obj));
480 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j)
481 if (pool->actions[j].dr_action)
483 (mlx5_flow_os_destroy_flow_action
484 (pool->actions[j].dr_action));
487 mlx5_free(sh->aso_age_mng->pools);
489 mlx5_free(sh->aso_age_mng);
493 * Initialize the shared aging list information per port.
496 * Pointer to mlx5_dev_ctx_shared object.
499 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
502 struct mlx5_age_info *age_info;
504 for (i = 0; i < sh->max_port; i++) {
505 age_info = &sh->port[i].age_info;
507 TAILQ_INIT(&age_info->aged_counters);
508 LIST_INIT(&age_info->aged_aso);
509 rte_spinlock_init(&age_info->aged_sl);
510 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
515 * Initialize the counters management structure.
518 * Pointer to mlx5_dev_ctx_shared object to free
521 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
525 memset(&sh->cmng, 0, sizeof(sh->cmng));
526 TAILQ_INIT(&sh->cmng.flow_counters);
527 sh->cmng.min_id = MLX5_CNT_BATCH_OFFSET;
528 sh->cmng.max_id = -1;
529 sh->cmng.last_pool_idx = POOL_IDX_INVALID;
530 rte_spinlock_init(&sh->cmng.pool_update_sl);
531 for (i = 0; i < MLX5_COUNTER_TYPE_MAX; i++) {
532 TAILQ_INIT(&sh->cmng.counters[i]);
533 rte_spinlock_init(&sh->cmng.csl[i]);
538 * Destroy all the resources allocated for a counter memory management.
541 * Pointer to the memory management structure.
544 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
546 uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
548 LIST_REMOVE(mng, next);
549 claim_zero(mlx5_devx_cmd_destroy(mng->dm));
550 claim_zero(mlx5_os_umem_dereg(mng->umem));
555 * Close and release all the resources of the counters management.
558 * Pointer to mlx5_dev_ctx_shared object to free.
561 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
563 struct mlx5_counter_stats_mem_mng *mng;
569 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
570 if (rte_errno != EINPROGRESS)
575 if (sh->cmng.pools) {
576 struct mlx5_flow_counter_pool *pool;
577 uint16_t n_valid = sh->cmng.n_valid;
578 bool fallback = sh->cmng.counter_fallback;
580 for (i = 0; i < n_valid; ++i) {
581 pool = sh->cmng.pools[i];
582 if (!fallback && pool->min_dcs)
583 claim_zero(mlx5_devx_cmd_destroy
585 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
586 struct mlx5_flow_counter *cnt =
587 MLX5_POOL_GET_CNT(pool, j);
591 (mlx5_flow_os_destroy_flow_action
593 if (fallback && MLX5_POOL_GET_CNT
594 (pool, j)->dcs_when_free)
595 claim_zero(mlx5_devx_cmd_destroy
596 (cnt->dcs_when_free));
600 mlx5_free(sh->cmng.pools);
602 mng = LIST_FIRST(&sh->cmng.mem_mngs);
604 mlx5_flow_destroy_counter_stat_mem_mng(mng);
605 mng = LIST_FIRST(&sh->cmng.mem_mngs);
607 memset(&sh->cmng, 0, sizeof(sh->cmng));
611 * Initialize the aso flow meters management structure.
614 * Pointer to mlx5_dev_ctx_shared object to free
617 mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh)
620 sh->mtrmng = mlx5_malloc(MLX5_MEM_ZERO,
622 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
625 "meter management allocation was failed.");
629 if (sh->meter_aso_en) {
630 rte_spinlock_init(&sh->mtrmng->pools_mng.mtrsl);
631 LIST_INIT(&sh->mtrmng->pools_mng.meters);
633 sh->mtrmng->def_policy_id = MLX5_INVALID_POLICY_ID;
639 * Close and release all the resources of
640 * the ASO flow meter management structure.
643 * Pointer to mlx5_dev_ctx_shared object to free.
646 mlx5_aso_flow_mtrs_mng_close(struct mlx5_dev_ctx_shared *sh)
648 struct mlx5_aso_mtr_pool *mtr_pool;
649 struct mlx5_flow_mtr_mng *mtrmng = sh->mtrmng;
651 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
652 struct mlx5_aso_mtr *aso_mtr;
654 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
656 if (sh->meter_aso_en) {
657 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_POLICER);
658 idx = mtrmng->pools_mng.n_valid;
660 mtr_pool = mtrmng->pools_mng.pools[idx];
661 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
662 for (i = 0; i < MLX5_ASO_MTRS_PER_POOL; i++) {
663 aso_mtr = &mtr_pool->mtrs[i];
664 if (aso_mtr->fm.meter_action)
666 (mlx5_glue->destroy_flow_action
667 (aso_mtr->fm.meter_action));
669 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
670 claim_zero(mlx5_devx_cmd_destroy
671 (mtr_pool->devx_obj));
672 mtrmng->pools_mng.n_valid--;
675 mlx5_free(sh->mtrmng->pools_mng.pools);
677 mlx5_free(sh->mtrmng);
681 /* Send FLOW_AGED event if needed. */
683 mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh)
685 struct mlx5_age_info *age_info;
688 for (i = 0; i < sh->max_port; i++) {
689 age_info = &sh->port[i].age_info;
690 if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW))
692 MLX5_AGE_UNSET(age_info, MLX5_AGE_EVENT_NEW);
693 if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER)) {
694 MLX5_AGE_UNSET(age_info, MLX5_AGE_TRIGGER);
695 rte_eth_dev_callback_process
696 (&rte_eth_devices[sh->port[i].devx_ih_port_id],
697 RTE_ETH_EVENT_FLOW_AGED, NULL);
703 * Initialize the ASO connection tracking structure.
706 * Pointer to mlx5_dev_ctx_shared object.
709 * 0 on success, a negative errno value otherwise and rte_errno is set.
712 mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh)
718 sh->ct_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->ct_mng),
719 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
721 DRV_LOG(ERR, "ASO CT management allocation failed.");
725 err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
727 mlx5_free(sh->ct_mng);
728 /* rte_errno should be extracted from the failure. */
732 rte_spinlock_init(&sh->ct_mng->ct_sl);
733 rte_rwlock_init(&sh->ct_mng->resize_rwl);
734 LIST_INIT(&sh->ct_mng->free_cts);
739 * Close and release all the resources of the
740 * ASO connection tracking management structure.
743 * Pointer to mlx5_dev_ctx_shared object to free.
746 mlx5_flow_aso_ct_mng_close(struct mlx5_dev_ctx_shared *sh)
748 struct mlx5_aso_ct_pools_mng *mng = sh->ct_mng;
749 struct mlx5_aso_ct_pool *ct_pool;
750 struct mlx5_aso_ct_action *ct;
756 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
760 ct_pool = mng->pools[idx];
761 for (i = 0; i < MLX5_ASO_CT_ACTIONS_PER_POOL; i++) {
762 ct = &ct_pool->actions[i];
763 val = __atomic_fetch_sub(&ct->refcnt, 1,
765 MLX5_ASSERT(val == 1);
768 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
769 if (ct->dr_action_orig)
770 claim_zero(mlx5_glue->destroy_flow_action
771 (ct->dr_action_orig));
772 if (ct->dr_action_rply)
773 claim_zero(mlx5_glue->destroy_flow_action
774 (ct->dr_action_rply));
777 claim_zero(mlx5_devx_cmd_destroy(ct_pool->devx_obj));
779 DRV_LOG(DEBUG, "%u ASO CT objects are being used in the pool %u",
783 /* in case of failure. */
786 mlx5_free(mng->pools);
788 /* Management structure must be cleared to 0s during allocation. */
793 * Initialize the flow resources' indexed mempool.
796 * Pointer to mlx5_dev_ctx_shared object.
798 * Pointer to user dev config.
801 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
802 const struct mlx5_dev_config *config)
805 struct mlx5_indexed_pool_config cfg;
807 for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
808 cfg = mlx5_ipool_cfg[i];
813 * Set MLX5_IPOOL_MLX5_FLOW ipool size
814 * according to PCI function flow configuration.
816 case MLX5_IPOOL_MLX5_FLOW:
817 cfg.size = config->dv_flow_en ?
818 sizeof(struct mlx5_flow_handle) :
819 MLX5_FLOW_HANDLE_VERBS_SIZE;
822 if (config->reclaim_mode) {
823 cfg.release_mem_en = 1;
824 cfg.per_core_cache = 0;
826 cfg.release_mem_en = 0;
828 sh->ipool[i] = mlx5_ipool_create(&cfg);
834 * Release the flow resources' indexed mempool.
837 * Pointer to mlx5_dev_ctx_shared object.
840 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
844 for (i = 0; i < MLX5_IPOOL_MAX; ++i)
845 mlx5_ipool_destroy(sh->ipool[i]);
846 for (i = 0; i < MLX5_MAX_MODIFY_NUM; ++i)
847 if (sh->mdh_ipools[i])
848 mlx5_ipool_destroy(sh->mdh_ipools[i]);
852 * Check if dynamic flex parser for eCPRI already exists.
855 * Pointer to Ethernet device structure.
858 * true on exists, false on not.
861 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
863 struct mlx5_priv *priv = dev->data->dev_private;
864 struct mlx5_flex_parser_profiles *prf =
865 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
871 * Allocation of a flex parser for eCPRI. Once created, this parser related
872 * resources will be held until the device is closed.
875 * Pointer to Ethernet device structure.
878 * 0 on success, a negative errno value otherwise and rte_errno is set.
881 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
883 struct mlx5_priv *priv = dev->data->dev_private;
884 struct mlx5_flex_parser_profiles *prf =
885 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
886 struct mlx5_devx_graph_node_attr node = {
887 .modify_field_select = 0,
892 if (!priv->config.hca_attr.parse_graph_flex_node) {
893 DRV_LOG(ERR, "Dynamic flex parser is not supported "
894 "for device %s.", priv->dev_data->name);
897 node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
898 /* 8 bytes now: 4B common header + 4B message body header. */
899 node.header_length_base_value = 0x8;
900 /* After MAC layer: Ether / VLAN. */
901 node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
902 /* Type of compared condition should be 0xAEFE in the L2 layer. */
903 node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
904 /* Sample #0: type in common header. */
905 node.sample[0].flow_match_sample_en = 1;
907 node.sample[0].flow_match_sample_offset_mode = 0x0;
908 /* Only the 2nd byte will be used. */
909 node.sample[0].flow_match_sample_field_base_offset = 0x0;
910 /* Sample #1: message payload. */
911 node.sample[1].flow_match_sample_en = 1;
913 node.sample[1].flow_match_sample_offset_mode = 0x0;
915 * Only the first two bytes will be used right now, and its offset will
916 * start after the common header that with the length of a DW(u32).
918 node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
919 prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->ctx, &node);
921 DRV_LOG(ERR, "Failed to create flex parser node object.");
922 return (rte_errno == 0) ? -ENODEV : -rte_errno;
925 ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
927 DRV_LOG(ERR, "Failed to query sample IDs.");
928 return (rte_errno == 0) ? -ENODEV : -rte_errno;
930 prf->offset[0] = 0x0;
931 prf->offset[1] = sizeof(uint32_t);
932 prf->ids[0] = ids[0];
933 prf->ids[1] = ids[1];
938 * Destroy the flex parser node, including the parser itself, input / output
939 * arcs and DW samples. Resources could be reused then.
942 * Pointer to Ethernet device structure.
945 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
947 struct mlx5_priv *priv = dev->data->dev_private;
948 struct mlx5_flex_parser_profiles *prf =
949 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
952 mlx5_devx_cmd_destroy(prf->obj);
957 mlx5_get_supported_sw_parsing_offloads(const struct mlx5_hca_attr *attr)
959 uint32_t sw_parsing_offloads = 0;
962 sw_parsing_offloads |= MLX5_SW_PARSING_CAP;
964 sw_parsing_offloads |= MLX5_SW_PARSING_CSUM_CAP;
967 sw_parsing_offloads |= MLX5_SW_PARSING_TSO_CAP;
969 return sw_parsing_offloads;
973 * Allocate Rx and Tx UARs in robust fashion.
974 * This routine handles the following UAR allocation issues:
976 * - tries to allocate the UAR with the most appropriate memory
977 * mapping type from the ones supported by the host
979 * - tries to allocate the UAR with non-NULL base address
980 * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
981 * UAR base address if UAR was not the first object in the UAR page.
982 * It caused the PMD failure and we should try to get another UAR
983 * till we get the first one with non-NULL base address returned.
986 mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh,
987 const struct mlx5_dev_config *config)
989 uint32_t uar_mapping, retry;
993 for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
994 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
995 /* Control the mapping type according to the settings. */
996 uar_mapping = (config->dbnc == MLX5_TXDB_NCACHED) ?
997 MLX5DV_UAR_ALLOC_TYPE_NC :
998 MLX5DV_UAR_ALLOC_TYPE_BF;
1000 RTE_SET_USED(config);
1002 * It seems we have no way to control the memory mapping type
1003 * for the UAR, the default "Write-Combining" type is supposed.
1004 * The UAR initialization on queue creation queries the
1005 * actual mapping type done by Verbs/kernel and setups the
1006 * PMD datapath accordingly.
1010 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, uar_mapping);
1011 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
1013 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
1014 if (config->dbnc == MLX5_TXDB_CACHED ||
1015 config->dbnc == MLX5_TXDB_HEURISTIC)
1016 DRV_LOG(WARNING, "Devarg tx_db_nc setting "
1017 "is not supported by DevX");
1019 * In some environments like virtual machine
1020 * the Write Combining mapped might be not supported
1021 * and UAR allocation fails. We try "Non-Cached"
1022 * mapping for the case. The tx_burst routines take
1023 * the UAR mapping type into account on UAR setup
1024 * on queue creation.
1026 DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (BF)");
1027 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
1028 sh->tx_uar = mlx5_glue->devx_alloc_uar
1029 (sh->ctx, uar_mapping);
1030 } else if (!sh->tx_uar &&
1031 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) {
1032 if (config->dbnc == MLX5_TXDB_NCACHED)
1033 DRV_LOG(WARNING, "Devarg tx_db_nc settings "
1034 "is not supported by DevX");
1036 * If Verbs/kernel does not support "Non-Cached"
1037 * try the "Write-Combining".
1039 DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (NC)");
1040 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;
1041 sh->tx_uar = mlx5_glue->devx_alloc_uar
1042 (sh->ctx, uar_mapping);
1046 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (BF/NC)");
1050 base_addr = mlx5_os_get_devx_uar_base_addr(sh->tx_uar);
1054 * The UARs are allocated by rdma_core within the
1055 * IB device context, on context closure all UARs
1056 * will be freed, should be no memory/object leakage.
1058 DRV_LOG(DEBUG, "Retrying to allocate Tx DevX UAR");
1061 /* Check whether we finally succeeded with valid UAR allocation. */
1063 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (NULL base)");
1067 for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
1069 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
1070 (sh->ctx, uar_mapping);
1071 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
1072 if (!sh->devx_rx_uar &&
1073 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
1075 * Rx UAR is used to control interrupts only,
1076 * should be no datapath noticeable impact,
1077 * can try "Non-Cached" mapping safely.
1079 DRV_LOG(DEBUG, "Failed to allocate Rx DevX UAR (BF)");
1080 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
1081 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
1082 (sh->ctx, uar_mapping);
1085 if (!sh->devx_rx_uar) {
1086 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (BF/NC)");
1090 base_addr = mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar);
1094 * The UARs are allocated by rdma_core within the
1095 * IB device context, on context closure all UARs
1096 * will be freed, should be no memory/object leakage.
1098 DRV_LOG(DEBUG, "Retrying to allocate Rx DevX UAR");
1099 sh->devx_rx_uar = NULL;
1101 /* Check whether we finally succeeded with valid UAR allocation. */
1102 if (!sh->devx_rx_uar) {
1103 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (NULL base)");
1111 * Unregister the mempool from the protection domain.
1114 * Pointer to the device shared context.
1116 * Mempool being unregistered.
1119 mlx5_dev_ctx_shared_mempool_unregister(struct mlx5_dev_ctx_shared *sh,
1120 struct rte_mempool *mp)
1122 struct mlx5_mp_id mp_id;
1124 mlx5_mp_id_init(&mp_id, 0);
1125 if (mlx5_mr_mempool_unregister(&sh->share_cache, mp, &mp_id) < 0)
1126 DRV_LOG(WARNING, "Failed to unregister mempool %s for PD %p: %s",
1127 mp->name, sh->pd, rte_strerror(rte_errno));
1131 * rte_mempool_walk() callback to register mempools
1132 * for the protection domain.
1135 * The mempool being walked.
1137 * Pointer to the device shared context.
1140 mlx5_dev_ctx_shared_mempool_register_cb(struct rte_mempool *mp, void *arg)
1142 struct mlx5_dev_ctx_shared *sh = arg;
1143 struct mlx5_mp_id mp_id;
1146 mlx5_mp_id_init(&mp_id, 0);
1147 ret = mlx5_mr_mempool_register(&sh->share_cache, sh->pd, mp, &mp_id);
1148 if (ret < 0 && rte_errno != EEXIST)
1149 DRV_LOG(ERR, "Failed to register existing mempool %s for PD %p: %s",
1150 mp->name, sh->pd, rte_strerror(rte_errno));
1154 * rte_mempool_walk() callback to unregister mempools
1155 * from the protection domain.
1158 * The mempool being walked.
1160 * Pointer to the device shared context.
1163 mlx5_dev_ctx_shared_mempool_unregister_cb(struct rte_mempool *mp, void *arg)
1165 mlx5_dev_ctx_shared_mempool_unregister
1166 ((struct mlx5_dev_ctx_shared *)arg, mp);
1170 * Mempool life cycle callback for Ethernet devices.
1173 * Mempool life cycle event.
1175 * Associated mempool.
1177 * Pointer to a device shared context.
1180 mlx5_dev_ctx_shared_mempool_event_cb(enum rte_mempool_event event,
1181 struct rte_mempool *mp, void *arg)
1183 struct mlx5_dev_ctx_shared *sh = arg;
1184 struct mlx5_mp_id mp_id;
1187 case RTE_MEMPOOL_EVENT_READY:
1188 mlx5_mp_id_init(&mp_id, 0);
1189 if (mlx5_mr_mempool_register(&sh->share_cache, sh->pd, mp,
1191 DRV_LOG(ERR, "Failed to register new mempool %s for PD %p: %s",
1192 mp->name, sh->pd, rte_strerror(rte_errno));
1194 case RTE_MEMPOOL_EVENT_DESTROY:
1195 mlx5_dev_ctx_shared_mempool_unregister(sh, mp);
1201 * Callback used when implicit mempool registration is disabled
1202 * in order to track Rx mempool destruction.
1205 * Mempool life cycle event.
1207 * An Rx mempool registered explicitly when the port is started.
1209 * Pointer to a device shared context.
1212 mlx5_dev_ctx_shared_rx_mempool_event_cb(enum rte_mempool_event event,
1213 struct rte_mempool *mp, void *arg)
1215 struct mlx5_dev_ctx_shared *sh = arg;
1217 if (event == RTE_MEMPOOL_EVENT_DESTROY)
1218 mlx5_dev_ctx_shared_mempool_unregister(sh, mp);
1222 mlx5_dev_ctx_shared_mempool_subscribe(struct rte_eth_dev *dev)
1224 struct mlx5_priv *priv = dev->data->dev_private;
1225 struct mlx5_dev_ctx_shared *sh = priv->sh;
1228 /* Check if we only need to track Rx mempool destruction. */
1229 if (!priv->config.mr_mempool_reg_en) {
1230 ret = rte_mempool_event_callback_register
1231 (mlx5_dev_ctx_shared_rx_mempool_event_cb, sh);
1232 return ret == 0 || rte_errno == EEXIST ? 0 : ret;
1234 /* Callback for this shared context may be already registered. */
1235 ret = rte_mempool_event_callback_register
1236 (mlx5_dev_ctx_shared_mempool_event_cb, sh);
1237 if (ret != 0 && rte_errno != EEXIST)
1239 /* Register mempools only once for this shared context. */
1241 rte_mempool_walk(mlx5_dev_ctx_shared_mempool_register_cb, sh);
1246 * Allocate shared device context. If there is multiport device the
1247 * master and representors will share this context, if there is single
1248 * port dedicated device, the context will be used by only given
1249 * port due to unification.
1251 * Routine first searches the context for the specified device name,
1252 * if found the shared context assumed and reference counter is incremented.
1253 * If no context found the new one is created and initialized with specified
1254 * device context and parameters.
1257 * Pointer to the device attributes (name, port, etc).
1259 * Pointer to device configuration structure.
1262 * Pointer to mlx5_dev_ctx_shared object on success,
1263 * otherwise NULL and rte_errno is set.
1265 struct mlx5_dev_ctx_shared *
1266 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
1267 const struct mlx5_dev_config *config)
1269 struct mlx5_dev_ctx_shared *sh;
1272 struct mlx5_devx_tis_attr tis_attr = { 0 };
1275 /* Secondary process should not create the shared context. */
1276 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1277 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1278 /* Search for IB context by device name. */
1279 LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
1280 if (!strcmp(sh->ibdev_name,
1281 mlx5_os_get_dev_device_name(spawn->phys_dev))) {
1286 /* No device found, we have to create new shared context. */
1287 MLX5_ASSERT(spawn->max_port);
1288 sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
1289 sizeof(struct mlx5_dev_ctx_shared) +
1291 sizeof(struct mlx5_dev_shared_port),
1292 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
1294 DRV_LOG(ERR, "shared context allocation failure");
1298 sh->numa_node = spawn->numa_node;
1299 if (spawn->bond_info)
1300 sh->bond = *spawn->bond_info;
1301 err = mlx5_os_open_device(spawn, config, sh);
1304 err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
1306 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
1310 sh->max_port = spawn->max_port;
1311 sh->reclaim_mode = config->reclaim_mode;
1312 strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
1313 sizeof(sh->ibdev_name) - 1);
1314 strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
1315 sizeof(sh->ibdev_path) - 1);
1317 * Setting port_id to max unallowed value means
1318 * there is no interrupt subhandler installed for
1319 * the given port index i.
1321 for (i = 0; i < sh->max_port; i++) {
1322 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
1323 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
1325 sh->pd = mlx5_os_alloc_pd(sh->ctx);
1326 if (sh->pd == NULL) {
1327 DRV_LOG(ERR, "PD allocation failure");
1332 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
1334 DRV_LOG(ERR, "Fail to extract pdn from PD");
1337 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
1339 DRV_LOG(ERR, "TD allocation failure");
1343 tis_attr.transport_domain = sh->td->id;
1344 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
1346 DRV_LOG(ERR, "TIS allocation failure");
1350 err = mlx5_alloc_rxtx_uars(sh, config);
1353 MLX5_ASSERT(sh->tx_uar);
1354 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar));
1356 MLX5_ASSERT(sh->devx_rx_uar);
1357 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar));
1360 /* Initialize UAR access locks for 32bit implementations. */
1361 rte_spinlock_init(&sh->uar_lock_cq);
1362 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
1363 rte_spinlock_init(&sh->uar_lock[i]);
1366 * Once the device is added to the list of memory event
1367 * callback, its global MR cache table cannot be expanded
1368 * on the fly because of deadlock. If it overflows, lookup
1369 * should be done by searching MR list linearly, which is slow.
1371 * At this point the device is not added to the memory
1372 * event list yet, context is just being created.
1374 err = mlx5_mr_btree_init(&sh->share_cache.cache,
1375 MLX5_MR_BTREE_CACHE_N * 2,
1381 mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
1382 &sh->share_cache.dereg_mr_cb);
1383 mlx5_os_dev_shared_handler_install(sh);
1384 if (LIST_EMPTY(&mlx5_dev_ctx_list)) {
1385 err = mlx5_flow_os_init_workspace_once();
1389 mlx5_flow_aging_init(sh);
1390 mlx5_flow_counters_mng_init(sh);
1391 mlx5_flow_ipool_create(sh, config);
1392 /* Add device to memory callback list. */
1393 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1394 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
1396 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1397 /* Add context to the global device list. */
1398 LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
1399 rte_spinlock_init(&sh->geneve_tlv_opt_sl);
1401 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1404 pthread_mutex_destroy(&sh->txpp.mutex);
1405 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1407 if (sh->share_cache.cache.table)
1408 mlx5_mr_btree_free(&sh->share_cache.cache);
1410 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1412 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1413 if (sh->devx_rx_uar)
1414 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1416 mlx5_glue->devx_free_uar(sh->tx_uar);
1418 claim_zero(mlx5_os_dealloc_pd(sh->pd));
1420 claim_zero(mlx5_glue->close_device(sh->ctx));
1422 MLX5_ASSERT(err > 0);
1428 * Free shared IB device context. Decrement counter and if zero free
1429 * all allocated resources and close handles.
1432 * Pointer to mlx5_dev_ctx_shared object to free
1435 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
1439 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1440 #ifdef RTE_LIBRTE_MLX5_DEBUG
1441 /* Check the object presence in the list. */
1442 struct mlx5_dev_ctx_shared *lctx;
1444 LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
1449 DRV_LOG(ERR, "Freeing non-existing shared IB context");
1454 MLX5_ASSERT(sh->refcnt);
1455 /* Secondary process should not free the shared context. */
1456 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1459 /* Stop watching for mempool events and unregister all mempools. */
1460 ret = rte_mempool_event_callback_unregister
1461 (mlx5_dev_ctx_shared_mempool_event_cb, sh);
1462 if (ret < 0 && rte_errno == ENOENT)
1463 ret = rte_mempool_event_callback_unregister
1464 (mlx5_dev_ctx_shared_rx_mempool_event_cb, sh);
1466 rte_mempool_walk(mlx5_dev_ctx_shared_mempool_unregister_cb,
1468 /* Remove from memory callback device list. */
1469 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1470 LIST_REMOVE(sh, mem_event_cb);
1471 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1472 /* Release created Memory Regions. */
1473 mlx5_mr_release_cache(&sh->share_cache);
1474 /* Remove context from the global device list. */
1475 LIST_REMOVE(sh, next);
1476 /* Release flow workspaces objects on the last device. */
1477 if (LIST_EMPTY(&mlx5_dev_ctx_list))
1478 mlx5_flow_os_release_workspace();
1479 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1481 * Ensure there is no async event handler installed.
1482 * Only primary process handles async device events.
1484 mlx5_flow_counters_mng_close(sh);
1485 if (sh->aso_age_mng) {
1486 mlx5_flow_aso_age_mng_close(sh);
1487 sh->aso_age_mng = NULL;
1490 mlx5_aso_flow_mtrs_mng_close(sh);
1491 mlx5_flow_ipool_destroy(sh);
1492 mlx5_os_dev_shared_handler_uninstall(sh);
1494 mlx5_glue->devx_free_uar(sh->tx_uar);
1498 claim_zero(mlx5_os_dealloc_pd(sh->pd));
1500 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1502 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1503 if (sh->devx_rx_uar)
1504 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1506 claim_zero(mlx5_glue->close_device(sh->ctx));
1507 MLX5_ASSERT(sh->geneve_tlv_option_resource == NULL);
1508 pthread_mutex_destroy(&sh->txpp.mutex);
1512 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1516 * Destroy table hash list.
1519 * Pointer to the private device data structure.
1522 mlx5_free_table_hash_list(struct mlx5_priv *priv)
1524 struct mlx5_dev_ctx_shared *sh = priv->sh;
1528 mlx5_hlist_destroy(sh->flow_tbls);
1529 sh->flow_tbls = NULL;
1533 * Initialize flow table hash list and create the root tables entry
1537 * Pointer to the private device data structure.
1540 * Zero on success, positive error code otherwise.
1543 mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused)
1546 /* Tables are only used in DV and DR modes. */
1547 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
1548 struct mlx5_dev_ctx_shared *sh = priv->sh;
1549 char s[MLX5_NAME_SIZE];
1552 snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1553 sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE,
1555 flow_dv_tbl_create_cb,
1556 flow_dv_tbl_match_cb,
1557 flow_dv_tbl_remove_cb,
1558 flow_dv_tbl_clone_cb,
1559 flow_dv_tbl_clone_free_cb);
1560 if (!sh->flow_tbls) {
1561 DRV_LOG(ERR, "flow tables with hash creation failed.");
1565 #ifndef HAVE_MLX5DV_DR
1566 struct rte_flow_error error;
1567 struct rte_eth_dev *dev = &rte_eth_devices[priv->dev_data->port_id];
1570 * In case we have not DR support, the zero tables should be created
1571 * because DV expect to see them even if they cannot be created by
1574 if (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0,
1575 NULL, 0, 1, 0, &error) ||
1576 !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0,
1577 NULL, 0, 1, 0, &error) ||
1578 !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0,
1579 NULL, 0, 1, 0, &error)) {
1585 mlx5_free_table_hash_list(priv);
1586 #endif /* HAVE_MLX5DV_DR */
1592 * Retrieve integer value from environment variable.
1595 * Environment variable name.
1598 * Integer value, 0 if the variable is not set.
1601 mlx5_getenv_int(const char *name)
1603 const char *val = getenv(name);
1611 * DPDK callback to add udp tunnel port
1614 * A pointer to eth_dev
1615 * @param[in] udp_tunnel
1616 * A pointer to udp tunnel
1619 * 0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1622 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1623 struct rte_eth_udp_tunnel *udp_tunnel)
1625 MLX5_ASSERT(udp_tunnel != NULL);
1626 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1627 udp_tunnel->udp_port == 4789)
1629 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1630 udp_tunnel->udp_port == 4790)
1636 * Initialize process private data structure.
1639 * Pointer to Ethernet device structure.
1642 * 0 on success, a negative errno value otherwise and rte_errno is set.
1645 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1647 struct mlx5_priv *priv = dev->data->dev_private;
1648 struct mlx5_proc_priv *ppriv;
1651 mlx5_proc_priv_uninit(dev);
1653 * UAR register table follows the process private structure. BlueFlame
1654 * registers for Tx queues are stored in the table.
1657 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1658 ppriv = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, ppriv_size,
1659 RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1664 ppriv->uar_table_sz = priv->txqs_n;
1665 dev->process_private = ppriv;
1670 * Un-initialize process private data structure.
1673 * Pointer to Ethernet device structure.
1676 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1678 if (!dev->process_private)
1680 mlx5_free(dev->process_private);
1681 dev->process_private = NULL;
1685 * DPDK callback to close the device.
1687 * Destroy all queues and objects, free memory.
1690 * Pointer to Ethernet device structure.
1693 mlx5_dev_close(struct rte_eth_dev *dev)
1695 struct mlx5_priv *priv = dev->data->dev_private;
1699 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1700 /* Check if process_private released. */
1701 if (!dev->process_private)
1703 mlx5_tx_uar_uninit_secondary(dev);
1704 mlx5_proc_priv_uninit(dev);
1705 rte_eth_dev_release_port(dev);
1710 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1712 ((priv->sh->ctx != NULL) ?
1713 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1715 * If default mreg copy action is removed at the stop stage,
1716 * the search will return none and nothing will be done anymore.
1718 mlx5_flow_stop_default(dev);
1719 mlx5_traffic_disable(dev);
1721 * If all the flows are already flushed in the device stop stage,
1722 * then this will return directly without any action.
1724 mlx5_flow_list_flush(dev, MLX5_FLOW_TYPE_GEN, true);
1725 mlx5_action_handle_flush(dev);
1726 mlx5_flow_meter_flush(dev, NULL);
1727 /* Prevent crashes when queues are still in use. */
1728 dev->rx_pkt_burst = removed_rx_burst;
1729 dev->tx_pkt_burst = removed_tx_burst;
1731 /* Disable datapath on secondary process. */
1732 mlx5_mp_os_req_stop_rxtx(dev);
1733 /* Free the eCPRI flex parser resource. */
1734 mlx5_flex_parser_ecpri_release(dev);
1735 if (priv->rxqs != NULL) {
1736 /* XXX race condition if mlx5_rx_burst() is still running. */
1737 rte_delay_us_sleep(1000);
1738 for (i = 0; (i != priv->rxqs_n); ++i)
1739 mlx5_rxq_release(dev, i);
1743 if (priv->representor) {
1744 /* Each representor has a dedicated interrupts handler */
1745 mlx5_free(dev->intr_handle);
1746 dev->intr_handle = NULL;
1748 if (priv->txqs != NULL) {
1749 /* XXX race condition if mlx5_tx_burst() is still running. */
1750 rte_delay_us_sleep(1000);
1751 for (i = 0; (i != priv->txqs_n); ++i)
1752 mlx5_txq_release(dev, i);
1756 mlx5_proc_priv_uninit(dev);
1757 if (priv->q_counters) {
1758 mlx5_devx_cmd_destroy(priv->q_counters);
1759 priv->q_counters = NULL;
1761 if (priv->drop_queue.hrxq)
1762 mlx5_drop_action_destroy(dev);
1763 if (priv->mreg_cp_tbl)
1764 mlx5_hlist_destroy(priv->mreg_cp_tbl);
1765 mlx5_mprq_free_mp(dev);
1766 if (priv->sh->ct_mng)
1767 mlx5_flow_aso_ct_mng_close(priv->sh);
1768 mlx5_os_free_shared_dr(priv);
1769 if (priv->rss_conf.rss_key != NULL)
1770 mlx5_free(priv->rss_conf.rss_key);
1771 if (priv->reta_idx != NULL)
1772 mlx5_free(priv->reta_idx);
1773 if (priv->config.vf)
1774 mlx5_os_mac_addr_flush(dev);
1775 if (priv->nl_socket_route >= 0)
1776 close(priv->nl_socket_route);
1777 if (priv->nl_socket_rdma >= 0)
1778 close(priv->nl_socket_rdma);
1779 if (priv->vmwa_context)
1780 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1781 ret = mlx5_hrxq_verify(dev);
1783 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1784 dev->data->port_id);
1785 ret = mlx5_ind_table_obj_verify(dev);
1787 DRV_LOG(WARNING, "port %u some indirection table still remain",
1788 dev->data->port_id);
1789 ret = mlx5_rxq_obj_verify(dev);
1791 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1792 dev->data->port_id);
1793 ret = mlx5_rxq_verify(dev);
1795 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1796 dev->data->port_id);
1797 ret = mlx5_txq_obj_verify(dev);
1799 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1800 dev->data->port_id);
1801 ret = mlx5_txq_verify(dev);
1803 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1804 dev->data->port_id);
1805 ret = mlx5_flow_verify(dev);
1807 DRV_LOG(WARNING, "port %u some flows still remain",
1808 dev->data->port_id);
1810 mlx5_list_destroy(priv->hrxqs);
1812 * Free the shared context in last turn, because the cleanup
1813 * routines above may use some shared fields, like
1814 * mlx5_os_mac_addr_flush() uses ibdev_path for retrieveing
1815 * ifindex if Netlink fails.
1817 mlx5_free_shared_dev_ctx(priv->sh);
1818 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1822 MLX5_ETH_FOREACH_DEV(port_id, dev->device) {
1823 struct mlx5_priv *opriv =
1824 rte_eth_devices[port_id].data->dev_private;
1827 opriv->domain_id != priv->domain_id ||
1828 &rte_eth_devices[port_id] == dev)
1834 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1836 memset(priv, 0, sizeof(*priv));
1837 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1839 * Reset mac_addrs to NULL such that it is not freed as part of
1840 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1841 * it is freed when dev_private is freed.
1843 dev->data->mac_addrs = NULL;
1847 const struct eth_dev_ops mlx5_dev_ops = {
1848 .dev_configure = mlx5_dev_configure,
1849 .dev_start = mlx5_dev_start,
1850 .dev_stop = mlx5_dev_stop,
1851 .dev_set_link_down = mlx5_set_link_down,
1852 .dev_set_link_up = mlx5_set_link_up,
1853 .dev_close = mlx5_dev_close,
1854 .promiscuous_enable = mlx5_promiscuous_enable,
1855 .promiscuous_disable = mlx5_promiscuous_disable,
1856 .allmulticast_enable = mlx5_allmulticast_enable,
1857 .allmulticast_disable = mlx5_allmulticast_disable,
1858 .link_update = mlx5_link_update,
1859 .stats_get = mlx5_stats_get,
1860 .stats_reset = mlx5_stats_reset,
1861 .xstats_get = mlx5_xstats_get,
1862 .xstats_reset = mlx5_xstats_reset,
1863 .xstats_get_names = mlx5_xstats_get_names,
1864 .fw_version_get = mlx5_fw_version_get,
1865 .dev_infos_get = mlx5_dev_infos_get,
1866 .representor_info_get = mlx5_representor_info_get,
1867 .read_clock = mlx5_txpp_read_clock,
1868 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1869 .vlan_filter_set = mlx5_vlan_filter_set,
1870 .rx_queue_setup = mlx5_rx_queue_setup,
1871 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1872 .tx_queue_setup = mlx5_tx_queue_setup,
1873 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1874 .rx_queue_release = mlx5_rx_queue_release,
1875 .tx_queue_release = mlx5_tx_queue_release,
1876 .rx_queue_start = mlx5_rx_queue_start,
1877 .rx_queue_stop = mlx5_rx_queue_stop,
1878 .tx_queue_start = mlx5_tx_queue_start,
1879 .tx_queue_stop = mlx5_tx_queue_stop,
1880 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1881 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1882 .mac_addr_remove = mlx5_mac_addr_remove,
1883 .mac_addr_add = mlx5_mac_addr_add,
1884 .mac_addr_set = mlx5_mac_addr_set,
1885 .set_mc_addr_list = mlx5_set_mc_addr_list,
1886 .mtu_set = mlx5_dev_set_mtu,
1887 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1888 .vlan_offload_set = mlx5_vlan_offload_set,
1889 .reta_update = mlx5_dev_rss_reta_update,
1890 .reta_query = mlx5_dev_rss_reta_query,
1891 .rss_hash_update = mlx5_rss_hash_update,
1892 .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1893 .flow_ops_get = mlx5_flow_ops_get,
1894 .rxq_info_get = mlx5_rxq_info_get,
1895 .txq_info_get = mlx5_txq_info_get,
1896 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1897 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1898 .rx_queue_intr_enable = mlx5_rx_intr_enable,
1899 .rx_queue_intr_disable = mlx5_rx_intr_disable,
1900 .is_removed = mlx5_is_removed,
1901 .udp_tunnel_port_add = mlx5_udp_tunnel_port_add,
1902 .get_module_info = mlx5_get_module_info,
1903 .get_module_eeprom = mlx5_get_module_eeprom,
1904 .hairpin_cap_get = mlx5_hairpin_cap_get,
1905 .mtr_ops_get = mlx5_flow_meter_ops_get,
1906 .hairpin_bind = mlx5_hairpin_bind,
1907 .hairpin_unbind = mlx5_hairpin_unbind,
1908 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1909 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1910 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1911 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1912 .get_monitor_addr = mlx5_get_monitor_addr,
1915 /* Available operations from secondary process. */
1916 const struct eth_dev_ops mlx5_dev_sec_ops = {
1917 .stats_get = mlx5_stats_get,
1918 .stats_reset = mlx5_stats_reset,
1919 .xstats_get = mlx5_xstats_get,
1920 .xstats_reset = mlx5_xstats_reset,
1921 .xstats_get_names = mlx5_xstats_get_names,
1922 .fw_version_get = mlx5_fw_version_get,
1923 .dev_infos_get = mlx5_dev_infos_get,
1924 .representor_info_get = mlx5_representor_info_get,
1925 .read_clock = mlx5_txpp_read_clock,
1926 .rx_queue_start = mlx5_rx_queue_start,
1927 .rx_queue_stop = mlx5_rx_queue_stop,
1928 .tx_queue_start = mlx5_tx_queue_start,
1929 .tx_queue_stop = mlx5_tx_queue_stop,
1930 .rxq_info_get = mlx5_rxq_info_get,
1931 .txq_info_get = mlx5_txq_info_get,
1932 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1933 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1934 .get_module_info = mlx5_get_module_info,
1935 .get_module_eeprom = mlx5_get_module_eeprom,
1938 /* Available operations in flow isolated mode. */
1939 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1940 .dev_configure = mlx5_dev_configure,
1941 .dev_start = mlx5_dev_start,
1942 .dev_stop = mlx5_dev_stop,
1943 .dev_set_link_down = mlx5_set_link_down,
1944 .dev_set_link_up = mlx5_set_link_up,
1945 .dev_close = mlx5_dev_close,
1946 .promiscuous_enable = mlx5_promiscuous_enable,
1947 .promiscuous_disable = mlx5_promiscuous_disable,
1948 .allmulticast_enable = mlx5_allmulticast_enable,
1949 .allmulticast_disable = mlx5_allmulticast_disable,
1950 .link_update = mlx5_link_update,
1951 .stats_get = mlx5_stats_get,
1952 .stats_reset = mlx5_stats_reset,
1953 .xstats_get = mlx5_xstats_get,
1954 .xstats_reset = mlx5_xstats_reset,
1955 .xstats_get_names = mlx5_xstats_get_names,
1956 .fw_version_get = mlx5_fw_version_get,
1957 .dev_infos_get = mlx5_dev_infos_get,
1958 .representor_info_get = mlx5_representor_info_get,
1959 .read_clock = mlx5_txpp_read_clock,
1960 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1961 .vlan_filter_set = mlx5_vlan_filter_set,
1962 .rx_queue_setup = mlx5_rx_queue_setup,
1963 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1964 .tx_queue_setup = mlx5_tx_queue_setup,
1965 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1966 .rx_queue_release = mlx5_rx_queue_release,
1967 .tx_queue_release = mlx5_tx_queue_release,
1968 .rx_queue_start = mlx5_rx_queue_start,
1969 .rx_queue_stop = mlx5_rx_queue_stop,
1970 .tx_queue_start = mlx5_tx_queue_start,
1971 .tx_queue_stop = mlx5_tx_queue_stop,
1972 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1973 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1974 .mac_addr_remove = mlx5_mac_addr_remove,
1975 .mac_addr_add = mlx5_mac_addr_add,
1976 .mac_addr_set = mlx5_mac_addr_set,
1977 .set_mc_addr_list = mlx5_set_mc_addr_list,
1978 .mtu_set = mlx5_dev_set_mtu,
1979 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1980 .vlan_offload_set = mlx5_vlan_offload_set,
1981 .flow_ops_get = mlx5_flow_ops_get,
1982 .rxq_info_get = mlx5_rxq_info_get,
1983 .txq_info_get = mlx5_txq_info_get,
1984 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1985 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1986 .rx_queue_intr_enable = mlx5_rx_intr_enable,
1987 .rx_queue_intr_disable = mlx5_rx_intr_disable,
1988 .is_removed = mlx5_is_removed,
1989 .get_module_info = mlx5_get_module_info,
1990 .get_module_eeprom = mlx5_get_module_eeprom,
1991 .hairpin_cap_get = mlx5_hairpin_cap_get,
1992 .mtr_ops_get = mlx5_flow_meter_ops_get,
1993 .hairpin_bind = mlx5_hairpin_bind,
1994 .hairpin_unbind = mlx5_hairpin_unbind,
1995 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1996 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1997 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1998 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1999 .get_monitor_addr = mlx5_get_monitor_addr,
2003 * Verify and store value for device argument.
2006 * Key argument to verify.
2008 * Value associated with key.
2013 * 0 on success, a negative errno value otherwise and rte_errno is set.
2016 mlx5_args_check(const char *key, const char *val, void *opaque)
2018 struct mlx5_dev_config *config = opaque;
2022 /* No-op, port representors are processed in mlx5_dev_spawn(). */
2023 if (!strcmp(MLX5_DRIVER_KEY, key) || !strcmp(MLX5_REPRESENTOR, key))
2026 tmp = strtol(val, NULL, 0);
2029 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
2032 if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
2033 /* Negative values are acceptable for some keys only. */
2035 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
2038 mod = tmp >= 0 ? tmp : -tmp;
2039 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
2040 if (tmp > MLX5_CQE_RESP_FORMAT_L34H_STRIDX) {
2041 DRV_LOG(ERR, "invalid CQE compression "
2042 "format parameter");
2046 config->cqe_comp = !!tmp;
2047 config->cqe_comp_fmt = tmp;
2048 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
2049 config->hw_padding = !!tmp;
2050 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
2051 config->mprq.enabled = !!tmp;
2052 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
2053 config->mprq.stride_num_n = tmp;
2054 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
2055 config->mprq.stride_size_n = tmp;
2056 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
2057 config->mprq.max_memcpy_len = tmp;
2058 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
2059 config->mprq.min_rxqs_num = tmp;
2060 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
2061 DRV_LOG(WARNING, "%s: deprecated parameter,"
2062 " converted to txq_inline_max", key);
2063 config->txq_inline_max = tmp;
2064 } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
2065 config->txq_inline_max = tmp;
2066 } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
2067 config->txq_inline_min = tmp;
2068 } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
2069 config->txq_inline_mpw = tmp;
2070 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
2071 config->txqs_inline = tmp;
2072 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
2073 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
2074 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
2075 config->mps = !!tmp;
2076 } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
2077 if (tmp != MLX5_TXDB_CACHED &&
2078 tmp != MLX5_TXDB_NCACHED &&
2079 tmp != MLX5_TXDB_HEURISTIC) {
2080 DRV_LOG(ERR, "invalid Tx doorbell "
2081 "mapping parameter");
2086 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
2087 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
2088 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
2089 DRV_LOG(WARNING, "%s: deprecated parameter,"
2090 " converted to txq_inline_mpw", key);
2091 config->txq_inline_mpw = tmp;
2092 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
2093 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
2094 } else if (strcmp(MLX5_TX_PP, key) == 0) {
2096 DRV_LOG(ERR, "Zero Tx packet pacing parameter");
2100 config->tx_pp = tmp;
2101 } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
2102 config->tx_skew = tmp;
2103 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
2104 config->rx_vec_en = !!tmp;
2105 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
2106 config->l3_vxlan_en = !!tmp;
2107 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
2108 config->vf_nl_en = !!tmp;
2109 } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
2110 config->dv_esw_en = !!tmp;
2111 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
2112 config->dv_flow_en = !!tmp;
2113 } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
2114 if (tmp != MLX5_XMETA_MODE_LEGACY &&
2115 tmp != MLX5_XMETA_MODE_META16 &&
2116 tmp != MLX5_XMETA_MODE_META32 &&
2117 tmp != MLX5_XMETA_MODE_MISS_INFO) {
2118 DRV_LOG(ERR, "invalid extensive "
2119 "metadata parameter");
2123 if (tmp != MLX5_XMETA_MODE_MISS_INFO)
2124 config->dv_xmeta_en = tmp;
2126 config->dv_miss_info = 1;
2127 } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
2128 config->lacp_by_user = !!tmp;
2129 } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
2130 config->mr_ext_memseg_en = !!tmp;
2131 } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
2132 config->max_dump_files_num = tmp;
2133 } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
2134 config->lro.timeout = tmp;
2135 } else if (strcmp(RTE_DEVARGS_KEY_CLASS, key) == 0) {
2136 DRV_LOG(DEBUG, "class argument is %s.", val);
2137 } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
2138 config->log_hp_size = tmp;
2139 } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
2140 if (tmp != MLX5_RCM_NONE &&
2141 tmp != MLX5_RCM_LIGHT &&
2142 tmp != MLX5_RCM_AGGR) {
2143 DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
2147 config->reclaim_mode = tmp;
2148 } else if (strcmp(MLX5_SYS_MEM_EN, key) == 0) {
2149 config->sys_mem_en = !!tmp;
2150 } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
2151 config->decap_en = !!tmp;
2152 } else if (strcmp(MLX5_ALLOW_DUPLICATE_PATTERN, key) == 0) {
2153 config->allow_duplicate_pattern = !!tmp;
2154 } else if (strcmp(MLX5_MR_MEMPOOL_REG_EN, key) == 0) {
2155 config->mr_mempool_reg_en = !!tmp;
2157 DRV_LOG(WARNING, "%s: unknown parameter", key);
2165 * Parse device parameters.
2168 * Pointer to device configuration structure.
2170 * Device arguments structure.
2173 * 0 on success, a negative errno value otherwise and rte_errno is set.
2176 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
2178 const char **params = (const char *[]){
2180 MLX5_RXQ_CQE_COMP_EN,
2181 MLX5_RXQ_PKT_PAD_EN,
2183 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
2184 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
2185 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
2188 MLX5_TXQ_INLINE_MIN,
2189 MLX5_TXQ_INLINE_MAX,
2190 MLX5_TXQ_INLINE_MPW,
2191 MLX5_TXQS_MIN_INLINE,
2194 MLX5_TXQ_MPW_HDR_DSEG_EN,
2195 MLX5_TXQ_MAX_INLINE_LEN,
2207 MLX5_MR_EXT_MEMSEG_EN,
2209 MLX5_MAX_DUMP_FILES_NUM,
2210 MLX5_LRO_TIMEOUT_USEC,
2211 RTE_DEVARGS_KEY_CLASS,
2216 MLX5_ALLOW_DUPLICATE_PATTERN,
2217 MLX5_MR_MEMPOOL_REG_EN,
2220 struct rte_kvargs *kvlist;
2224 if (devargs == NULL)
2226 /* Following UGLY cast is done to pass checkpatch. */
2227 kvlist = rte_kvargs_parse(devargs->args, params);
2228 if (kvlist == NULL) {
2232 /* Process parameters. */
2233 for (i = 0; (params[i] != NULL); ++i) {
2234 if (rte_kvargs_count(kvlist, params[i])) {
2235 ret = rte_kvargs_process(kvlist, params[i],
2236 mlx5_args_check, config);
2239 rte_kvargs_free(kvlist);
2244 rte_kvargs_free(kvlist);
2249 * Configures the minimal amount of data to inline into WQE
2250 * while sending packets.
2252 * - the txq_inline_min has the maximal priority, if this
2253 * key is specified in devargs
2254 * - if DevX is enabled the inline mode is queried from the
2255 * device (HCA attributes and NIC vport context if needed).
2256 * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
2257 * and none (0 bytes) for other NICs
2260 * Verbs device parameters (name, port, switch_info) to spawn.
2262 * Device configuration parameters.
2265 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
2266 struct mlx5_dev_config *config)
2268 if (config->txq_inline_min != MLX5_ARG_UNSET) {
2269 /* Application defines size of inlined data explicitly. */
2270 if (spawn->pci_dev != NULL) {
2271 switch (spawn->pci_dev->id.device_id) {
2272 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2273 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2274 if (config->txq_inline_min <
2275 (int)MLX5_INLINE_HSIZE_L2) {
2277 "txq_inline_mix aligned to minimal ConnectX-4 required value %d",
2278 (int)MLX5_INLINE_HSIZE_L2);
2279 config->txq_inline_min =
2280 MLX5_INLINE_HSIZE_L2;
2287 if (config->hca_attr.eth_net_offloads) {
2288 /* We have DevX enabled, inline mode queried successfully. */
2289 switch (config->hca_attr.wqe_inline_mode) {
2290 case MLX5_CAP_INLINE_MODE_L2:
2291 /* outer L2 header must be inlined. */
2292 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2294 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
2295 /* No inline data are required by NIC. */
2296 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2297 config->hw_vlan_insert =
2298 config->hca_attr.wqe_vlan_insert;
2299 DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
2301 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
2302 /* inline mode is defined by NIC vport context. */
2303 if (!config->hca_attr.eth_virt)
2305 switch (config->hca_attr.vport_inline_mode) {
2306 case MLX5_INLINE_MODE_NONE:
2307 config->txq_inline_min =
2308 MLX5_INLINE_HSIZE_NONE;
2310 case MLX5_INLINE_MODE_L2:
2311 config->txq_inline_min =
2312 MLX5_INLINE_HSIZE_L2;
2314 case MLX5_INLINE_MODE_IP:
2315 config->txq_inline_min =
2316 MLX5_INLINE_HSIZE_L3;
2318 case MLX5_INLINE_MODE_TCP_UDP:
2319 config->txq_inline_min =
2320 MLX5_INLINE_HSIZE_L4;
2322 case MLX5_INLINE_MODE_INNER_L2:
2323 config->txq_inline_min =
2324 MLX5_INLINE_HSIZE_INNER_L2;
2326 case MLX5_INLINE_MODE_INNER_IP:
2327 config->txq_inline_min =
2328 MLX5_INLINE_HSIZE_INNER_L3;
2330 case MLX5_INLINE_MODE_INNER_TCP_UDP:
2331 config->txq_inline_min =
2332 MLX5_INLINE_HSIZE_INNER_L4;
2337 if (spawn->pci_dev == NULL) {
2338 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2342 * We get here if we are unable to deduce
2343 * inline data size with DevX. Try PCI ID
2344 * to determine old NICs.
2346 switch (spawn->pci_dev->id.device_id) {
2347 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2348 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2349 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
2350 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
2351 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2352 config->hw_vlan_insert = 0;
2354 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
2355 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
2356 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
2357 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
2359 * These NICs support VLAN insertion from WQE and
2360 * report the wqe_vlan_insert flag. But there is the bug
2361 * and PFC control may be broken, so disable feature.
2363 config->hw_vlan_insert = 0;
2364 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2367 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2371 DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
2375 * Configures the metadata mask fields in the shared context.
2378 * Pointer to Ethernet device.
2381 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
2383 struct mlx5_priv *priv = dev->data->dev_private;
2384 struct mlx5_dev_ctx_shared *sh = priv->sh;
2385 uint32_t meta, mark, reg_c0;
2387 reg_c0 = ~priv->vport_meta_mask;
2388 switch (priv->config.dv_xmeta_en) {
2389 case MLX5_XMETA_MODE_LEGACY:
2391 mark = MLX5_FLOW_MARK_MASK;
2393 case MLX5_XMETA_MODE_META16:
2394 meta = reg_c0 >> rte_bsf32(reg_c0);
2395 mark = MLX5_FLOW_MARK_MASK;
2397 case MLX5_XMETA_MODE_META32:
2399 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
2407 if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
2408 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
2409 sh->dv_mark_mask, mark);
2411 sh->dv_mark_mask = mark;
2412 if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
2413 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
2414 sh->dv_meta_mask, meta);
2416 sh->dv_meta_mask = meta;
2417 if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
2418 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
2419 sh->dv_meta_mask, reg_c0);
2421 sh->dv_regc0_mask = reg_c0;
2422 DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
2423 DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
2424 DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
2425 DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
2429 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
2431 static const char *const dynf_names[] = {
2432 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
2433 RTE_MBUF_DYNFLAG_METADATA_NAME,
2434 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
2438 if (n < RTE_DIM(dynf_names))
2440 for (i = 0; i < RTE_DIM(dynf_names); i++) {
2441 if (names[i] == NULL)
2443 strcpy(names[i], dynf_names[i]);
2445 return RTE_DIM(dynf_names);
2449 * Comparison callback to sort device data.
2451 * This is meant to be used with qsort().
2454 * Pointer to pointer to first data object.
2456 * Pointer to pointer to second data object.
2459 * 0 if both objects are equal, less than 0 if the first argument is less
2460 * than the second, greater than 0 otherwise.
2463 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
2464 struct mlx5_dev_config *config,
2465 struct rte_device *dpdk_dev)
2467 struct mlx5_dev_ctx_shared *sh = priv->sh;
2468 struct mlx5_dev_config *sh_conf = NULL;
2472 /* Nothing to compare for the single/first device. */
2473 if (sh->refcnt == 1)
2475 /* Find the device with shared context. */
2476 MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) {
2477 struct mlx5_priv *opriv =
2478 rte_eth_devices[port_id].data->dev_private;
2480 if (opriv && opriv != priv && opriv->sh == sh) {
2481 sh_conf = &opriv->config;
2487 if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
2488 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
2489 " for shared %s context", sh->ibdev_name);
2493 if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
2494 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
2495 " for shared %s context", sh->ibdev_name);
2503 * Look for the ethernet device belonging to mlx5 driver.
2505 * @param[in] port_id
2506 * port_id to start looking for device.
2508 * Pointer to the hint device. When device is being probed
2509 * the its siblings (master and preceding representors might
2510 * not have assigned driver yet (because the mlx5_os_pci_probe()
2511 * is not completed yet, for this case match on hint
2512 * device may be used to detect sibling device.
2515 * port_id of found device, RTE_MAX_ETHPORT if not found.
2518 mlx5_eth_find_next(uint16_t port_id, struct rte_device *odev)
2520 while (port_id < RTE_MAX_ETHPORTS) {
2521 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
2523 if (dev->state != RTE_ETH_DEV_UNUSED &&
2525 (dev->device == odev ||
2526 (dev->device->driver &&
2527 dev->device->driver->name &&
2528 ((strcmp(dev->device->driver->name,
2529 MLX5_PCI_DRIVER_NAME) == 0) ||
2530 (strcmp(dev->device->driver->name,
2531 MLX5_AUXILIARY_DRIVER_NAME) == 0)))))
2535 if (port_id >= RTE_MAX_ETHPORTS)
2536 return RTE_MAX_ETHPORTS;
2541 * Callback to remove a device.
2543 * This function removes all Ethernet devices belong to a given device.
2546 * Pointer to the generic device.
2549 * 0 on success, the function cannot fail.
2552 mlx5_net_remove(struct rte_device *dev)
2557 RTE_ETH_FOREACH_DEV_OF(port_id, dev) {
2559 * mlx5_dev_close() is not registered to secondary process,
2560 * call the close function explicitly for secondary process.
2562 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
2563 ret |= mlx5_dev_close(&rte_eth_devices[port_id]);
2565 ret |= rte_eth_dev_close(port_id);
2567 return ret == 0 ? 0 : -EIO;
2570 static const struct rte_pci_id mlx5_pci_id_map[] = {
2572 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2573 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
2576 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2577 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
2580 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2581 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
2584 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2585 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2588 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2589 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2592 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2593 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2596 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2597 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2600 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2601 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2604 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2605 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2608 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2609 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2612 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2613 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2616 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2617 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2620 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2621 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2624 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2625 PCI_DEVICE_ID_MELLANOX_CONNECTXVF)
2628 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2629 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2632 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2633 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2636 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2637 PCI_DEVICE_ID_MELLANOX_CONNECTX7)
2640 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2641 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF)
2648 static struct mlx5_class_driver mlx5_net_driver = {
2649 .drv_class = MLX5_CLASS_ETH,
2650 .name = RTE_STR(MLX5_ETH_DRIVER_NAME),
2651 .id_table = mlx5_pci_id_map,
2652 .probe = mlx5_os_net_probe,
2653 .remove = mlx5_net_remove,
2654 .dma_map = mlx5_net_dma_map,
2655 .dma_unmap = mlx5_net_dma_unmap,
2661 /* Initialize driver log type. */
2662 RTE_LOG_REGISTER_DEFAULT(mlx5_logtype, NOTICE)
2665 * Driver initialization routine.
2667 RTE_INIT(rte_mlx5_pmd_init)
2669 pthread_mutex_init(&mlx5_dev_ctx_list_mutex, NULL);
2671 /* Build the static tables for Verbs conversion. */
2672 mlx5_set_ptype_table();
2673 mlx5_set_cksum_table();
2674 mlx5_set_swp_types_table();
2676 mlx5_class_driver_register(&mlx5_net_driver);
2679 RTE_PMD_EXPORT_NAME(MLX5_ETH_DRIVER_NAME, __COUNTER__);
2680 RTE_PMD_REGISTER_PCI_TABLE(MLX5_ETH_DRIVER_NAME, mlx5_pci_id_map);
2681 RTE_PMD_REGISTER_KMOD_DEP(MLX5_ETH_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib");