1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
13 #include <rte_malloc.h>
14 #include <ethdev_driver.h>
15 #include <ethdev_pci.h>
17 #include <rte_bus_pci.h>
18 #include <rte_common.h>
19 #include <rte_kvargs.h>
20 #include <rte_rwlock.h>
21 #include <rte_spinlock.h>
22 #include <rte_string_fns.h>
23 #include <rte_alarm.h>
24 #include <rte_cycles.h>
26 #include <mlx5_glue.h>
27 #include <mlx5_devx_cmds.h>
28 #include <mlx5_common.h>
29 #include <mlx5_common_os.h>
30 #include <mlx5_common_mp.h>
31 #include <mlx5_common_pci.h>
32 #include <mlx5_malloc.h>
34 #include "mlx5_defs.h"
36 #include "mlx5_utils.h"
37 #include "mlx5_rxtx.h"
40 #include "mlx5_autoconf.h"
42 #include "mlx5_flow.h"
43 #include "mlx5_flow_os.h"
44 #include "rte_pmd_mlx5.h"
46 /* Device parameter to enable RX completion queue compression. */
47 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
49 /* Device parameter to enable padding Rx packet to cacheline size. */
50 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
52 /* Device parameter to enable Multi-Packet Rx queue. */
53 #define MLX5_RX_MPRQ_EN "mprq_en"
55 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
56 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
58 /* Device parameter to configure log 2 of the stride size for MPRQ. */
59 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
61 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
62 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
64 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
65 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
67 /* Device parameter to configure inline send. Deprecated, ignored.*/
68 #define MLX5_TXQ_INLINE "txq_inline"
70 /* Device parameter to limit packet size to inline with ordinary SEND. */
71 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
73 /* Device parameter to configure minimal data size to inline. */
74 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
76 /* Device parameter to limit packet size to inline with Enhanced MPW. */
77 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
80 * Device parameter to configure the number of TX queues threshold for
81 * enabling inline send.
83 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
86 * Device parameter to configure the number of TX queues threshold for
87 * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
89 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
91 /* Device parameter to enable multi-packet send WQEs. */
92 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
95 * Device parameter to force doorbell register mapping
96 * to non-cahed region eliminating the extra write memory barrier.
98 #define MLX5_TX_DB_NC "tx_db_nc"
101 * Device parameter to include 2 dsegs in the title WQEBB.
102 * Deprecated, ignored.
104 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
107 * Device parameter to limit the size of inlining packet.
108 * Deprecated, ignored.
110 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
113 * Device parameter to enable Tx scheduling on timestamps
114 * and specify the packet pacing granularity in nanoseconds.
116 #define MLX5_TX_PP "tx_pp"
119 * Device parameter to specify skew in nanoseconds on Tx datapath,
120 * it represents the time between SQ start WQE processing and
121 * appearing actual packet data on the wire.
123 #define MLX5_TX_SKEW "tx_skew"
126 * Device parameter to enable hardware Tx vector.
127 * Deprecated, ignored (no vectorized Tx routines anymore).
129 #define MLX5_TX_VEC_EN "tx_vec_en"
131 /* Device parameter to enable hardware Rx vector. */
132 #define MLX5_RX_VEC_EN "rx_vec_en"
134 /* Allow L3 VXLAN flow creation. */
135 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
137 /* Activate DV E-Switch flow steering. */
138 #define MLX5_DV_ESW_EN "dv_esw_en"
140 /* Activate DV flow steering. */
141 #define MLX5_DV_FLOW_EN "dv_flow_en"
143 /* Enable extensive flow metadata support. */
144 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
146 /* Device parameter to let the user manage the lacp traffic of bonded device */
147 #define MLX5_LACP_BY_USER "lacp_by_user"
149 /* Activate Netlink support in VF mode. */
150 #define MLX5_VF_NL_EN "vf_nl_en"
152 /* Enable extending memsegs when creating a MR. */
153 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
155 /* Select port representors to instantiate. */
156 #define MLX5_REPRESENTOR "representor"
158 /* Device parameter to configure the maximum number of dump files per queue. */
159 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
161 /* Configure timeout of LRO session (in microseconds). */
162 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
165 * Device parameter to configure the total data buffer size for a single
166 * hairpin queue (logarithm value).
168 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
170 /* Flow memory reclaim mode. */
171 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
173 /* The default memory allocator used in PMD. */
174 #define MLX5_SYS_MEM_EN "sys_mem_en"
175 /* Decap will be used or not. */
176 #define MLX5_DECAP_EN "decap_en"
178 /* Shared memory between primary and secondary processes. */
179 struct mlx5_shared_data *mlx5_shared_data;
181 /** Driver-specific log messages type. */
184 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
185 LIST_HEAD_INITIALIZER();
186 static pthread_mutex_t mlx5_dev_ctx_list_mutex;
187 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
188 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
189 [MLX5_IPOOL_DECAP_ENCAP] = {
190 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
196 .malloc = mlx5_malloc,
198 .type = "mlx5_encap_decap_ipool",
200 [MLX5_IPOOL_PUSH_VLAN] = {
201 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
207 .malloc = mlx5_malloc,
209 .type = "mlx5_push_vlan_ipool",
212 .size = sizeof(struct mlx5_flow_dv_tag_resource),
218 .malloc = mlx5_malloc,
220 .type = "mlx5_tag_ipool",
222 [MLX5_IPOOL_PORT_ID] = {
223 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
229 .malloc = mlx5_malloc,
231 .type = "mlx5_port_id_ipool",
233 [MLX5_IPOOL_JUMP] = {
234 .size = sizeof(struct mlx5_flow_tbl_data_entry),
240 .malloc = mlx5_malloc,
242 .type = "mlx5_jump_ipool",
244 [MLX5_IPOOL_SAMPLE] = {
245 .size = sizeof(struct mlx5_flow_dv_sample_resource),
251 .malloc = mlx5_malloc,
253 .type = "mlx5_sample_ipool",
255 [MLX5_IPOOL_DEST_ARRAY] = {
256 .size = sizeof(struct mlx5_flow_dv_dest_array_resource),
262 .malloc = mlx5_malloc,
264 .type = "mlx5_dest_array_ipool",
266 [MLX5_IPOOL_TUNNEL_ID] = {
267 .size = sizeof(struct mlx5_flow_tunnel),
268 .trunk_size = MLX5_MAX_TUNNELS,
271 .type = "mlx5_tunnel_offload",
273 [MLX5_IPOOL_TNL_TBL_ID] = {
276 .type = "mlx5_flow_tnl_tbl_ipool",
281 * The ipool index should grow continually from small to big,
282 * for meter idx, so not set grow_trunk to avoid meter index
283 * not jump continually.
285 .size = sizeof(struct mlx5_legacy_flow_meter),
289 .malloc = mlx5_malloc,
291 .type = "mlx5_meter_ipool",
294 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
300 .malloc = mlx5_malloc,
302 .type = "mlx5_mcp_ipool",
304 [MLX5_IPOOL_HRXQ] = {
305 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
311 .malloc = mlx5_malloc,
313 .type = "mlx5_hrxq_ipool",
315 [MLX5_IPOOL_MLX5_FLOW] = {
317 * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
318 * It set in run time according to PCI function configuration.
326 .malloc = mlx5_malloc,
328 .type = "mlx5_flow_handle_ipool",
330 [MLX5_IPOOL_RTE_FLOW] = {
331 .size = sizeof(struct rte_flow),
335 .malloc = mlx5_malloc,
337 .type = "rte_flow_ipool",
339 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID] = {
342 .type = "mlx5_flow_rss_id_ipool",
344 [MLX5_IPOOL_RSS_SHARED_ACTIONS] = {
345 .size = sizeof(struct mlx5_shared_action_rss),
351 .malloc = mlx5_malloc,
353 .type = "mlx5_shared_action_rss",
355 [MLX5_IPOOL_MTR_POLICY] = {
357 * The ipool index should grow continually from small to big,
358 * for policy idx, so not set grow_trunk to avoid policy index
359 * not jump continually.
361 .size = sizeof(struct mlx5_flow_meter_sub_policy),
365 .malloc = mlx5_malloc,
367 .type = "mlx5_meter_policy_ipool",
372 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
373 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
375 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
378 * Decide whether representor ID is a HPF(host PF) port on BF2.
381 * Pointer to Ethernet device structure.
384 * Non-zero if HPF, otherwise 0.
387 mlx5_is_hpf(struct rte_eth_dev *dev)
389 struct mlx5_priv *priv = dev->data->dev_private;
390 uint16_t repr = MLX5_REPRESENTOR_REPR(priv->representor_id);
391 int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
393 return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_VF &&
394 MLX5_REPRESENTOR_REPR(-1) == repr;
398 * Initialize the ASO aging management structure.
401 * Pointer to mlx5_dev_ctx_shared object to free
404 * 0 on success, a negative errno value otherwise and rte_errno is set.
407 mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh)
413 sh->aso_age_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->aso_age_mng),
414 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
415 if (!sh->aso_age_mng) {
416 DRV_LOG(ERR, "aso_age_mng allocation was failed.");
420 err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_FLOW_HIT);
422 mlx5_free(sh->aso_age_mng);
425 rte_spinlock_init(&sh->aso_age_mng->resize_sl);
426 rte_spinlock_init(&sh->aso_age_mng->free_sl);
427 LIST_INIT(&sh->aso_age_mng->free);
432 * Close and release all the resources of the ASO aging management structure.
435 * Pointer to mlx5_dev_ctx_shared object to free.
438 mlx5_flow_aso_age_mng_close(struct mlx5_dev_ctx_shared *sh)
442 mlx5_aso_flow_hit_queue_poll_stop(sh);
443 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_FLOW_HIT);
444 if (sh->aso_age_mng->pools) {
445 struct mlx5_aso_age_pool *pool;
447 for (i = 0; i < sh->aso_age_mng->next; ++i) {
448 pool = sh->aso_age_mng->pools[i];
449 claim_zero(mlx5_devx_cmd_destroy
450 (pool->flow_hit_aso_obj));
451 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j)
452 if (pool->actions[j].dr_action)
454 (mlx5_flow_os_destroy_flow_action
455 (pool->actions[j].dr_action));
458 mlx5_free(sh->aso_age_mng->pools);
460 mlx5_free(sh->aso_age_mng);
464 * Initialize the shared aging list information per port.
467 * Pointer to mlx5_dev_ctx_shared object.
470 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
473 struct mlx5_age_info *age_info;
475 for (i = 0; i < sh->max_port; i++) {
476 age_info = &sh->port[i].age_info;
478 TAILQ_INIT(&age_info->aged_counters);
479 LIST_INIT(&age_info->aged_aso);
480 rte_spinlock_init(&age_info->aged_sl);
481 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
486 * Initialize the counters management structure.
489 * Pointer to mlx5_dev_ctx_shared object to free
492 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
496 memset(&sh->cmng, 0, sizeof(sh->cmng));
497 TAILQ_INIT(&sh->cmng.flow_counters);
498 sh->cmng.min_id = MLX5_CNT_BATCH_OFFSET;
499 sh->cmng.max_id = -1;
500 sh->cmng.last_pool_idx = POOL_IDX_INVALID;
501 rte_spinlock_init(&sh->cmng.pool_update_sl);
502 for (i = 0; i < MLX5_COUNTER_TYPE_MAX; i++) {
503 TAILQ_INIT(&sh->cmng.counters[i]);
504 rte_spinlock_init(&sh->cmng.csl[i]);
509 * Destroy all the resources allocated for a counter memory management.
512 * Pointer to the memory management structure.
515 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
517 uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
519 LIST_REMOVE(mng, next);
520 claim_zero(mlx5_devx_cmd_destroy(mng->dm));
521 claim_zero(mlx5_os_umem_dereg(mng->umem));
526 * Close and release all the resources of the counters management.
529 * Pointer to mlx5_dev_ctx_shared object to free.
532 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
534 struct mlx5_counter_stats_mem_mng *mng;
540 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
541 if (rte_errno != EINPROGRESS)
546 if (sh->cmng.pools) {
547 struct mlx5_flow_counter_pool *pool;
548 uint16_t n_valid = sh->cmng.n_valid;
549 bool fallback = sh->cmng.counter_fallback;
551 for (i = 0; i < n_valid; ++i) {
552 pool = sh->cmng.pools[i];
553 if (!fallback && pool->min_dcs)
554 claim_zero(mlx5_devx_cmd_destroy
556 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
557 struct mlx5_flow_counter *cnt =
558 MLX5_POOL_GET_CNT(pool, j);
562 (mlx5_flow_os_destroy_flow_action
564 if (fallback && MLX5_POOL_GET_CNT
565 (pool, j)->dcs_when_free)
566 claim_zero(mlx5_devx_cmd_destroy
567 (cnt->dcs_when_free));
571 mlx5_free(sh->cmng.pools);
573 mng = LIST_FIRST(&sh->cmng.mem_mngs);
575 mlx5_flow_destroy_counter_stat_mem_mng(mng);
576 mng = LIST_FIRST(&sh->cmng.mem_mngs);
578 memset(&sh->cmng, 0, sizeof(sh->cmng));
582 * Initialize the aso flow meters management structure.
585 * Pointer to mlx5_dev_ctx_shared object to free
588 mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh)
591 sh->mtrmng = mlx5_malloc(MLX5_MEM_ZERO,
593 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
596 "meter management allocation was failed.");
600 if (sh->meter_aso_en) {
601 rte_spinlock_init(&sh->mtrmng->pools_mng.mtrsl);
602 LIST_INIT(&sh->mtrmng->pools_mng.meters);
604 sh->mtrmng->def_policy_id = MLX5_INVALID_POLICY_ID;
610 * Close and release all the resources of
611 * the ASO flow meter management structure.
614 * Pointer to mlx5_dev_ctx_shared object to free.
617 mlx5_aso_flow_mtrs_mng_close(struct mlx5_dev_ctx_shared *sh)
619 struct mlx5_aso_mtr_pool *mtr_pool;
620 struct mlx5_flow_mtr_mng *mtrmng = sh->mtrmng;
622 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
623 struct mlx5_aso_mtr *aso_mtr;
625 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
627 if (sh->meter_aso_en) {
628 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_POLICER);
629 idx = mtrmng->pools_mng.n_valid;
631 mtr_pool = mtrmng->pools_mng.pools[idx];
632 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
633 for (i = 0; i < MLX5_ASO_MTRS_PER_POOL; i++) {
634 aso_mtr = &mtr_pool->mtrs[i];
635 if (aso_mtr->fm.meter_action)
637 (mlx5_glue->destroy_flow_action
638 (aso_mtr->fm.meter_action));
640 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
641 claim_zero(mlx5_devx_cmd_destroy
642 (mtr_pool->devx_obj));
643 mtrmng->pools_mng.n_valid--;
646 mlx5_free(sh->mtrmng->pools_mng.pools);
648 mlx5_free(sh->mtrmng);
652 /* Send FLOW_AGED event if needed. */
654 mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh)
656 struct mlx5_age_info *age_info;
659 for (i = 0; i < sh->max_port; i++) {
660 age_info = &sh->port[i].age_info;
661 if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW))
663 MLX5_AGE_UNSET(age_info, MLX5_AGE_EVENT_NEW);
664 if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER)) {
665 MLX5_AGE_UNSET(age_info, MLX5_AGE_TRIGGER);
666 rte_eth_dev_callback_process
667 (&rte_eth_devices[sh->port[i].devx_ih_port_id],
668 RTE_ETH_EVENT_FLOW_AGED, NULL);
674 * Initialize the ASO connection tracking structure.
677 * Pointer to mlx5_dev_ctx_shared object.
680 * 0 on success, a negative errno value otherwise and rte_errno is set.
683 mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh)
689 sh->ct_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->ct_mng),
690 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
692 DRV_LOG(ERR, "ASO CT management allocation failed.");
696 err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
698 mlx5_free(sh->ct_mng);
699 /* rte_errno should be extracted from the failure. */
703 rte_spinlock_init(&sh->ct_mng->ct_sl);
704 rte_rwlock_init(&sh->ct_mng->resize_rwl);
705 LIST_INIT(&sh->ct_mng->free_cts);
710 * Close and release all the resources of the
711 * ASO connection tracking management structure.
714 * Pointer to mlx5_dev_ctx_shared object to free.
717 mlx5_flow_aso_ct_mng_close(struct mlx5_dev_ctx_shared *sh)
719 struct mlx5_aso_ct_pools_mng *mng = sh->ct_mng;
720 struct mlx5_aso_ct_pool *ct_pool;
721 struct mlx5_aso_ct_action *ct;
727 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
731 ct_pool = mng->pools[idx];
732 for (i = 0; i < MLX5_ASO_CT_ACTIONS_PER_POOL; i++) {
733 ct = &ct_pool->actions[i];
734 val = __atomic_fetch_sub(&ct->refcnt, 1,
736 MLX5_ASSERT(val == 1);
739 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
740 if (ct->dr_action_orig)
741 claim_zero(mlx5_glue->destroy_flow_action
742 (ct->dr_action_orig));
743 if (ct->dr_action_rply)
744 claim_zero(mlx5_glue->destroy_flow_action
745 (ct->dr_action_rply));
748 claim_zero(mlx5_devx_cmd_destroy(ct_pool->devx_obj));
750 DRV_LOG(DEBUG, "%u ASO CT objects are being used in the pool %u",
754 /* in case of failure. */
757 mlx5_free(mng->pools);
759 /* Management structure must be cleared to 0s during allocation. */
764 * Initialize the flow resources' indexed mempool.
767 * Pointer to mlx5_dev_ctx_shared object.
769 * Pointer to user dev config.
772 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
773 const struct mlx5_dev_config *config)
776 struct mlx5_indexed_pool_config cfg;
778 for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
779 cfg = mlx5_ipool_cfg[i];
784 * Set MLX5_IPOOL_MLX5_FLOW ipool size
785 * according to PCI function flow configuration.
787 case MLX5_IPOOL_MLX5_FLOW:
788 cfg.size = config->dv_flow_en ?
789 sizeof(struct mlx5_flow_handle) :
790 MLX5_FLOW_HANDLE_VERBS_SIZE;
793 if (config->reclaim_mode)
794 cfg.release_mem_en = 1;
795 sh->ipool[i] = mlx5_ipool_create(&cfg);
800 * Release the flow resources' indexed mempool.
803 * Pointer to mlx5_dev_ctx_shared object.
806 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
810 for (i = 0; i < MLX5_IPOOL_MAX; ++i)
811 mlx5_ipool_destroy(sh->ipool[i]);
815 * Check if dynamic flex parser for eCPRI already exists.
818 * Pointer to Ethernet device structure.
821 * true on exists, false on not.
824 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
826 struct mlx5_priv *priv = dev->data->dev_private;
827 struct mlx5_flex_parser_profiles *prf =
828 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
834 * Allocation of a flex parser for eCPRI. Once created, this parser related
835 * resources will be held until the device is closed.
838 * Pointer to Ethernet device structure.
841 * 0 on success, a negative errno value otherwise and rte_errno is set.
844 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
846 struct mlx5_priv *priv = dev->data->dev_private;
847 struct mlx5_flex_parser_profiles *prf =
848 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
849 struct mlx5_devx_graph_node_attr node = {
850 .modify_field_select = 0,
855 if (!priv->config.hca_attr.parse_graph_flex_node) {
856 DRV_LOG(ERR, "Dynamic flex parser is not supported "
857 "for device %s.", priv->dev_data->name);
860 node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
861 /* 8 bytes now: 4B common header + 4B message body header. */
862 node.header_length_base_value = 0x8;
863 /* After MAC layer: Ether / VLAN. */
864 node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
865 /* Type of compared condition should be 0xAEFE in the L2 layer. */
866 node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
867 /* Sample #0: type in common header. */
868 node.sample[0].flow_match_sample_en = 1;
870 node.sample[0].flow_match_sample_offset_mode = 0x0;
871 /* Only the 2nd byte will be used. */
872 node.sample[0].flow_match_sample_field_base_offset = 0x0;
873 /* Sample #1: message payload. */
874 node.sample[1].flow_match_sample_en = 1;
876 node.sample[1].flow_match_sample_offset_mode = 0x0;
878 * Only the first two bytes will be used right now, and its offset will
879 * start after the common header that with the length of a DW(u32).
881 node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
882 prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->ctx, &node);
884 DRV_LOG(ERR, "Failed to create flex parser node object.");
885 return (rte_errno == 0) ? -ENODEV : -rte_errno;
888 ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
890 DRV_LOG(ERR, "Failed to query sample IDs.");
891 return (rte_errno == 0) ? -ENODEV : -rte_errno;
893 prf->offset[0] = 0x0;
894 prf->offset[1] = sizeof(uint32_t);
895 prf->ids[0] = ids[0];
896 prf->ids[1] = ids[1];
901 * Destroy the flex parser node, including the parser itself, input / output
902 * arcs and DW samples. Resources could be reused then.
905 * Pointer to Ethernet device structure.
908 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
910 struct mlx5_priv *priv = dev->data->dev_private;
911 struct mlx5_flex_parser_profiles *prf =
912 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
915 mlx5_devx_cmd_destroy(prf->obj);
920 * Allocate Rx and Tx UARs in robust fashion.
921 * This routine handles the following UAR allocation issues:
923 * - tries to allocate the UAR with the most appropriate memory
924 * mapping type from the ones supported by the host
926 * - tries to allocate the UAR with non-NULL base address
927 * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
928 * UAR base address if UAR was not the first object in the UAR page.
929 * It caused the PMD failure and we should try to get another UAR
930 * till we get the first one with non-NULL base address returned.
933 mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh,
934 const struct mlx5_dev_config *config)
936 uint32_t uar_mapping, retry;
940 for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
941 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
942 /* Control the mapping type according to the settings. */
943 uar_mapping = (config->dbnc == MLX5_TXDB_NCACHED) ?
944 MLX5DV_UAR_ALLOC_TYPE_NC :
945 MLX5DV_UAR_ALLOC_TYPE_BF;
947 RTE_SET_USED(config);
949 * It seems we have no way to control the memory mapping type
950 * for the UAR, the default "Write-Combining" type is supposed.
951 * The UAR initialization on queue creation queries the
952 * actual mapping type done by Verbs/kernel and setups the
953 * PMD datapath accordingly.
957 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, uar_mapping);
958 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
960 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
961 if (config->dbnc == MLX5_TXDB_CACHED ||
962 config->dbnc == MLX5_TXDB_HEURISTIC)
963 DRV_LOG(WARNING, "Devarg tx_db_nc setting "
964 "is not supported by DevX");
966 * In some environments like virtual machine
967 * the Write Combining mapped might be not supported
968 * and UAR allocation fails. We try "Non-Cached"
969 * mapping for the case. The tx_burst routines take
970 * the UAR mapping type into account on UAR setup
973 DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (BF)");
974 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
975 sh->tx_uar = mlx5_glue->devx_alloc_uar
976 (sh->ctx, uar_mapping);
977 } else if (!sh->tx_uar &&
978 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) {
979 if (config->dbnc == MLX5_TXDB_NCACHED)
980 DRV_LOG(WARNING, "Devarg tx_db_nc settings "
981 "is not supported by DevX");
983 * If Verbs/kernel does not support "Non-Cached"
984 * try the "Write-Combining".
986 DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (NC)");
987 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;
988 sh->tx_uar = mlx5_glue->devx_alloc_uar
989 (sh->ctx, uar_mapping);
993 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (BF/NC)");
997 base_addr = mlx5_os_get_devx_uar_base_addr(sh->tx_uar);
1001 * The UARs are allocated by rdma_core within the
1002 * IB device context, on context closure all UARs
1003 * will be freed, should be no memory/object leakage.
1005 DRV_LOG(DEBUG, "Retrying to allocate Tx DevX UAR");
1008 /* Check whether we finally succeeded with valid UAR allocation. */
1010 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (NULL base)");
1014 for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
1016 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
1017 (sh->ctx, uar_mapping);
1018 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
1019 if (!sh->devx_rx_uar &&
1020 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
1022 * Rx UAR is used to control interrupts only,
1023 * should be no datapath noticeable impact,
1024 * can try "Non-Cached" mapping safely.
1026 DRV_LOG(DEBUG, "Failed to allocate Rx DevX UAR (BF)");
1027 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
1028 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
1029 (sh->ctx, uar_mapping);
1032 if (!sh->devx_rx_uar) {
1033 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (BF/NC)");
1037 base_addr = mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar);
1041 * The UARs are allocated by rdma_core within the
1042 * IB device context, on context closure all UARs
1043 * will be freed, should be no memory/object leakage.
1045 DRV_LOG(DEBUG, "Retrying to allocate Rx DevX UAR");
1046 sh->devx_rx_uar = NULL;
1048 /* Check whether we finally succeeded with valid UAR allocation. */
1049 if (!sh->devx_rx_uar) {
1050 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (NULL base)");
1058 * Allocate shared device context. If there is multiport device the
1059 * master and representors will share this context, if there is single
1060 * port dedicated device, the context will be used by only given
1061 * port due to unification.
1063 * Routine first searches the context for the specified device name,
1064 * if found the shared context assumed and reference counter is incremented.
1065 * If no context found the new one is created and initialized with specified
1066 * device context and parameters.
1069 * Pointer to the device attributes (name, port, etc).
1071 * Pointer to device configuration structure.
1074 * Pointer to mlx5_dev_ctx_shared object on success,
1075 * otherwise NULL and rte_errno is set.
1077 struct mlx5_dev_ctx_shared *
1078 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
1079 const struct mlx5_dev_config *config)
1081 struct mlx5_dev_ctx_shared *sh;
1084 struct mlx5_devx_tis_attr tis_attr = { 0 };
1087 /* Secondary process should not create the shared context. */
1088 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1089 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1090 /* Search for IB context by device name. */
1091 LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
1092 if (!strcmp(sh->ibdev_name,
1093 mlx5_os_get_dev_device_name(spawn->phys_dev))) {
1098 /* No device found, we have to create new shared context. */
1099 MLX5_ASSERT(spawn->max_port);
1100 sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
1101 sizeof(struct mlx5_dev_ctx_shared) +
1103 sizeof(struct mlx5_dev_shared_port),
1104 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
1106 DRV_LOG(ERR, "shared context allocation failure");
1110 if (spawn->bond_info)
1111 sh->bond = *spawn->bond_info;
1112 err = mlx5_os_open_device(spawn, config, sh);
1115 err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
1117 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
1121 sh->max_port = spawn->max_port;
1122 strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
1123 sizeof(sh->ibdev_name) - 1);
1124 strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
1125 sizeof(sh->ibdev_path) - 1);
1127 * Setting port_id to max unallowed value means
1128 * there is no interrupt subhandler installed for
1129 * the given port index i.
1131 for (i = 0; i < sh->max_port; i++) {
1132 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
1133 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
1135 sh->pd = mlx5_os_alloc_pd(sh->ctx);
1136 if (sh->pd == NULL) {
1137 DRV_LOG(ERR, "PD allocation failure");
1142 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
1144 DRV_LOG(ERR, "Fail to extract pdn from PD");
1147 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
1149 DRV_LOG(ERR, "TD allocation failure");
1153 tis_attr.transport_domain = sh->td->id;
1154 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
1156 DRV_LOG(ERR, "TIS allocation failure");
1160 err = mlx5_alloc_rxtx_uars(sh, config);
1163 MLX5_ASSERT(sh->tx_uar);
1164 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar));
1166 MLX5_ASSERT(sh->devx_rx_uar);
1167 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar));
1170 /* Initialize UAR access locks for 32bit implementations. */
1171 rte_spinlock_init(&sh->uar_lock_cq);
1172 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
1173 rte_spinlock_init(&sh->uar_lock[i]);
1176 * Once the device is added to the list of memory event
1177 * callback, its global MR cache table cannot be expanded
1178 * on the fly because of deadlock. If it overflows, lookup
1179 * should be done by searching MR list linearly, which is slow.
1181 * At this point the device is not added to the memory
1182 * event list yet, context is just being created.
1184 err = mlx5_mr_btree_init(&sh->share_cache.cache,
1185 MLX5_MR_BTREE_CACHE_N * 2,
1186 spawn->pci_dev->device.numa_node);
1191 mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
1192 &sh->share_cache.dereg_mr_cb);
1193 mlx5_os_dev_shared_handler_install(sh);
1194 sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
1195 if (!sh->cnt_id_tbl) {
1199 if (LIST_EMPTY(&mlx5_dev_ctx_list)) {
1200 err = mlx5_flow_os_init_workspace_once();
1204 mlx5_flow_aging_init(sh);
1205 mlx5_flow_counters_mng_init(sh);
1206 mlx5_flow_ipool_create(sh, config);
1207 /* Add device to memory callback list. */
1208 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1209 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
1211 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1212 /* Add context to the global device list. */
1213 LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
1214 rte_spinlock_init(&sh->geneve_tlv_opt_sl);
1216 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1219 pthread_mutex_destroy(&sh->txpp.mutex);
1220 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1223 mlx5_l3t_destroy(sh->cnt_id_tbl);
1225 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1227 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1228 if (sh->devx_rx_uar)
1229 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1231 mlx5_glue->devx_free_uar(sh->tx_uar);
1233 claim_zero(mlx5_os_dealloc_pd(sh->pd));
1235 claim_zero(mlx5_glue->close_device(sh->ctx));
1237 MLX5_ASSERT(err > 0);
1243 * Free shared IB device context. Decrement counter and if zero free
1244 * all allocated resources and close handles.
1247 * Pointer to mlx5_dev_ctx_shared object to free
1250 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
1252 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1253 #ifdef RTE_LIBRTE_MLX5_DEBUG
1254 /* Check the object presence in the list. */
1255 struct mlx5_dev_ctx_shared *lctx;
1257 LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
1262 DRV_LOG(ERR, "Freeing non-existing shared IB context");
1267 MLX5_ASSERT(sh->refcnt);
1268 /* Secondary process should not free the shared context. */
1269 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1272 /* Remove from memory callback device list. */
1273 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1274 LIST_REMOVE(sh, mem_event_cb);
1275 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1276 /* Release created Memory Regions. */
1277 mlx5_mr_release_cache(&sh->share_cache);
1278 /* Remove context from the global device list. */
1279 LIST_REMOVE(sh, next);
1280 /* Release flow workspaces objects on the last device. */
1281 if (LIST_EMPTY(&mlx5_dev_ctx_list))
1282 mlx5_flow_os_release_workspace();
1283 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1285 * Ensure there is no async event handler installed.
1286 * Only primary process handles async device events.
1288 mlx5_flow_counters_mng_close(sh);
1289 if (sh->aso_age_mng) {
1290 mlx5_flow_aso_age_mng_close(sh);
1291 sh->aso_age_mng = NULL;
1294 mlx5_aso_flow_mtrs_mng_close(sh);
1295 mlx5_flow_ipool_destroy(sh);
1296 mlx5_os_dev_shared_handler_uninstall(sh);
1297 if (sh->cnt_id_tbl) {
1298 mlx5_l3t_destroy(sh->cnt_id_tbl);
1299 sh->cnt_id_tbl = NULL;
1302 mlx5_glue->devx_free_uar(sh->tx_uar);
1306 claim_zero(mlx5_os_dealloc_pd(sh->pd));
1308 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1310 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1311 if (sh->devx_rx_uar)
1312 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1314 claim_zero(mlx5_glue->close_device(sh->ctx));
1315 MLX5_ASSERT(sh->geneve_tlv_option_resource == NULL);
1316 pthread_mutex_destroy(&sh->txpp.mutex);
1320 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1324 * Destroy table hash list.
1327 * Pointer to the private device data structure.
1330 mlx5_free_table_hash_list(struct mlx5_priv *priv)
1332 struct mlx5_dev_ctx_shared *sh = priv->sh;
1336 mlx5_hlist_destroy(sh->flow_tbls);
1340 * Initialize flow table hash list and create the root tables entry
1344 * Pointer to the private device data structure.
1347 * Zero on success, positive error code otherwise.
1350 mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused)
1353 /* Tables are only used in DV and DR modes. */
1354 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
1355 struct mlx5_dev_ctx_shared *sh = priv->sh;
1356 char s[MLX5_HLIST_NAMESIZE];
1359 snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1360 sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE,
1361 0, 0, flow_dv_tbl_create_cb,
1362 flow_dv_tbl_match_cb,
1363 flow_dv_tbl_remove_cb);
1364 if (!sh->flow_tbls) {
1365 DRV_LOG(ERR, "flow tables with hash creation failed.");
1369 sh->flow_tbls->ctx = sh;
1370 #ifndef HAVE_MLX5DV_DR
1371 struct rte_flow_error error;
1372 struct rte_eth_dev *dev = &rte_eth_devices[priv->dev_data->port_id];
1375 * In case we have not DR support, the zero tables should be created
1376 * because DV expect to see them even if they cannot be created by
1379 if (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0,
1380 NULL, 0, 1, 0, &error) ||
1381 !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0,
1382 NULL, 0, 1, 0, &error) ||
1383 !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0,
1384 NULL, 0, 1, 0, &error)) {
1390 mlx5_free_table_hash_list(priv);
1391 #endif /* HAVE_MLX5DV_DR */
1397 * Retrieve integer value from environment variable.
1400 * Environment variable name.
1403 * Integer value, 0 if the variable is not set.
1406 mlx5_getenv_int(const char *name)
1408 const char *val = getenv(name);
1416 * DPDK callback to add udp tunnel port
1419 * A pointer to eth_dev
1420 * @param[in] udp_tunnel
1421 * A pointer to udp tunnel
1424 * 0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1427 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1428 struct rte_eth_udp_tunnel *udp_tunnel)
1430 MLX5_ASSERT(udp_tunnel != NULL);
1431 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1432 udp_tunnel->udp_port == 4789)
1434 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1435 udp_tunnel->udp_port == 4790)
1441 * Initialize process private data structure.
1444 * Pointer to Ethernet device structure.
1447 * 0 on success, a negative errno value otherwise and rte_errno is set.
1450 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1452 struct mlx5_priv *priv = dev->data->dev_private;
1453 struct mlx5_proc_priv *ppriv;
1456 mlx5_proc_priv_uninit(dev);
1458 * UAR register table follows the process private structure. BlueFlame
1459 * registers for Tx queues are stored in the table.
1462 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1463 ppriv = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, ppriv_size,
1464 RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1469 ppriv->uar_table_sz = priv->txqs_n;
1470 dev->process_private = ppriv;
1475 * Un-initialize process private data structure.
1478 * Pointer to Ethernet device structure.
1481 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1483 if (!dev->process_private)
1485 mlx5_free(dev->process_private);
1486 dev->process_private = NULL;
1490 * DPDK callback to close the device.
1492 * Destroy all queues and objects, free memory.
1495 * Pointer to Ethernet device structure.
1498 mlx5_dev_close(struct rte_eth_dev *dev)
1500 struct mlx5_priv *priv = dev->data->dev_private;
1504 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1505 /* Check if process_private released. */
1506 if (!dev->process_private)
1508 mlx5_tx_uar_uninit_secondary(dev);
1509 mlx5_proc_priv_uninit(dev);
1510 rte_eth_dev_release_port(dev);
1515 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1517 ((priv->sh->ctx != NULL) ?
1518 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1520 * If default mreg copy action is removed at the stop stage,
1521 * the search will return none and nothing will be done anymore.
1523 mlx5_flow_stop_default(dev);
1524 mlx5_traffic_disable(dev);
1526 * If all the flows are already flushed in the device stop stage,
1527 * then this will return directly without any action.
1529 mlx5_flow_list_flush(dev, &priv->flows, true);
1530 mlx5_action_handle_flush(dev);
1531 mlx5_flow_meter_flush(dev, NULL);
1532 /* Prevent crashes when queues are still in use. */
1533 dev->rx_pkt_burst = removed_rx_burst;
1534 dev->tx_pkt_burst = removed_tx_burst;
1536 /* Disable datapath on secondary process. */
1537 mlx5_mp_os_req_stop_rxtx(dev);
1538 /* Free the eCPRI flex parser resource. */
1539 mlx5_flex_parser_ecpri_release(dev);
1540 if (priv->rxqs != NULL) {
1541 /* XXX race condition if mlx5_rx_burst() is still running. */
1542 rte_delay_us_sleep(1000);
1543 for (i = 0; (i != priv->rxqs_n); ++i)
1544 mlx5_rxq_release(dev, i);
1548 if (priv->txqs != NULL) {
1549 /* XXX race condition if mlx5_tx_burst() is still running. */
1550 rte_delay_us_sleep(1000);
1551 for (i = 0; (i != priv->txqs_n); ++i)
1552 mlx5_txq_release(dev, i);
1556 mlx5_proc_priv_uninit(dev);
1557 if (priv->q_counters) {
1558 mlx5_devx_cmd_destroy(priv->q_counters);
1559 priv->q_counters = NULL;
1561 if (priv->drop_queue.hrxq)
1562 mlx5_drop_action_destroy(dev);
1563 if (priv->mreg_cp_tbl)
1564 mlx5_hlist_destroy(priv->mreg_cp_tbl);
1565 mlx5_mprq_free_mp(dev);
1566 if (priv->sh->ct_mng)
1567 mlx5_flow_aso_ct_mng_close(priv->sh);
1568 mlx5_os_free_shared_dr(priv);
1569 if (priv->rss_conf.rss_key != NULL)
1570 mlx5_free(priv->rss_conf.rss_key);
1571 if (priv->reta_idx != NULL)
1572 mlx5_free(priv->reta_idx);
1573 if (priv->config.vf)
1574 mlx5_os_mac_addr_flush(dev);
1575 if (priv->nl_socket_route >= 0)
1576 close(priv->nl_socket_route);
1577 if (priv->nl_socket_rdma >= 0)
1578 close(priv->nl_socket_rdma);
1579 if (priv->vmwa_context)
1580 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1581 ret = mlx5_hrxq_verify(dev);
1583 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1584 dev->data->port_id);
1585 ret = mlx5_ind_table_obj_verify(dev);
1587 DRV_LOG(WARNING, "port %u some indirection table still remain",
1588 dev->data->port_id);
1589 ret = mlx5_rxq_obj_verify(dev);
1591 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1592 dev->data->port_id);
1593 ret = mlx5_rxq_verify(dev);
1595 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1596 dev->data->port_id);
1597 ret = mlx5_txq_obj_verify(dev);
1599 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1600 dev->data->port_id);
1601 ret = mlx5_txq_verify(dev);
1603 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1604 dev->data->port_id);
1605 ret = mlx5_flow_verify(dev);
1607 DRV_LOG(WARNING, "port %u some flows still remain",
1608 dev->data->port_id);
1609 mlx5_cache_list_destroy(&priv->hrxqs);
1611 * Free the shared context in last turn, because the cleanup
1612 * routines above may use some shared fields, like
1613 * mlx5_os_mac_addr_flush() uses ibdev_path for retrieveing
1614 * ifindex if Netlink fails.
1616 mlx5_free_shared_dev_ctx(priv->sh);
1617 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1621 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1622 struct mlx5_priv *opriv =
1623 rte_eth_devices[port_id].data->dev_private;
1626 opriv->domain_id != priv->domain_id ||
1627 &rte_eth_devices[port_id] == dev)
1633 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1635 memset(priv, 0, sizeof(*priv));
1636 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1638 * Reset mac_addrs to NULL such that it is not freed as part of
1639 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1640 * it is freed when dev_private is freed.
1642 dev->data->mac_addrs = NULL;
1646 const struct eth_dev_ops mlx5_dev_ops = {
1647 .dev_configure = mlx5_dev_configure,
1648 .dev_start = mlx5_dev_start,
1649 .dev_stop = mlx5_dev_stop,
1650 .dev_set_link_down = mlx5_set_link_down,
1651 .dev_set_link_up = mlx5_set_link_up,
1652 .dev_close = mlx5_dev_close,
1653 .promiscuous_enable = mlx5_promiscuous_enable,
1654 .promiscuous_disable = mlx5_promiscuous_disable,
1655 .allmulticast_enable = mlx5_allmulticast_enable,
1656 .allmulticast_disable = mlx5_allmulticast_disable,
1657 .link_update = mlx5_link_update,
1658 .stats_get = mlx5_stats_get,
1659 .stats_reset = mlx5_stats_reset,
1660 .xstats_get = mlx5_xstats_get,
1661 .xstats_reset = mlx5_xstats_reset,
1662 .xstats_get_names = mlx5_xstats_get_names,
1663 .fw_version_get = mlx5_fw_version_get,
1664 .dev_infos_get = mlx5_dev_infos_get,
1665 .representor_info_get = mlx5_representor_info_get,
1666 .read_clock = mlx5_txpp_read_clock,
1667 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1668 .vlan_filter_set = mlx5_vlan_filter_set,
1669 .rx_queue_setup = mlx5_rx_queue_setup,
1670 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1671 .tx_queue_setup = mlx5_tx_queue_setup,
1672 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1673 .rx_queue_release = mlx5_rx_queue_release,
1674 .tx_queue_release = mlx5_tx_queue_release,
1675 .rx_queue_start = mlx5_rx_queue_start,
1676 .rx_queue_stop = mlx5_rx_queue_stop,
1677 .tx_queue_start = mlx5_tx_queue_start,
1678 .tx_queue_stop = mlx5_tx_queue_stop,
1679 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1680 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1681 .mac_addr_remove = mlx5_mac_addr_remove,
1682 .mac_addr_add = mlx5_mac_addr_add,
1683 .mac_addr_set = mlx5_mac_addr_set,
1684 .set_mc_addr_list = mlx5_set_mc_addr_list,
1685 .mtu_set = mlx5_dev_set_mtu,
1686 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1687 .vlan_offload_set = mlx5_vlan_offload_set,
1688 .reta_update = mlx5_dev_rss_reta_update,
1689 .reta_query = mlx5_dev_rss_reta_query,
1690 .rss_hash_update = mlx5_rss_hash_update,
1691 .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1692 .flow_ops_get = mlx5_flow_ops_get,
1693 .rxq_info_get = mlx5_rxq_info_get,
1694 .txq_info_get = mlx5_txq_info_get,
1695 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1696 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1697 .rx_queue_intr_enable = mlx5_rx_intr_enable,
1698 .rx_queue_intr_disable = mlx5_rx_intr_disable,
1699 .is_removed = mlx5_is_removed,
1700 .udp_tunnel_port_add = mlx5_udp_tunnel_port_add,
1701 .get_module_info = mlx5_get_module_info,
1702 .get_module_eeprom = mlx5_get_module_eeprom,
1703 .hairpin_cap_get = mlx5_hairpin_cap_get,
1704 .mtr_ops_get = mlx5_flow_meter_ops_get,
1705 .hairpin_bind = mlx5_hairpin_bind,
1706 .hairpin_unbind = mlx5_hairpin_unbind,
1707 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1708 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1709 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1710 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1711 .get_monitor_addr = mlx5_get_monitor_addr,
1714 /* Available operations from secondary process. */
1715 const struct eth_dev_ops mlx5_dev_sec_ops = {
1716 .stats_get = mlx5_stats_get,
1717 .stats_reset = mlx5_stats_reset,
1718 .xstats_get = mlx5_xstats_get,
1719 .xstats_reset = mlx5_xstats_reset,
1720 .xstats_get_names = mlx5_xstats_get_names,
1721 .fw_version_get = mlx5_fw_version_get,
1722 .dev_infos_get = mlx5_dev_infos_get,
1723 .read_clock = mlx5_txpp_read_clock,
1724 .rx_queue_start = mlx5_rx_queue_start,
1725 .rx_queue_stop = mlx5_rx_queue_stop,
1726 .tx_queue_start = mlx5_tx_queue_start,
1727 .tx_queue_stop = mlx5_tx_queue_stop,
1728 .rxq_info_get = mlx5_rxq_info_get,
1729 .txq_info_get = mlx5_txq_info_get,
1730 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1731 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1732 .get_module_info = mlx5_get_module_info,
1733 .get_module_eeprom = mlx5_get_module_eeprom,
1736 /* Available operations in flow isolated mode. */
1737 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1738 .dev_configure = mlx5_dev_configure,
1739 .dev_start = mlx5_dev_start,
1740 .dev_stop = mlx5_dev_stop,
1741 .dev_set_link_down = mlx5_set_link_down,
1742 .dev_set_link_up = mlx5_set_link_up,
1743 .dev_close = mlx5_dev_close,
1744 .promiscuous_enable = mlx5_promiscuous_enable,
1745 .promiscuous_disable = mlx5_promiscuous_disable,
1746 .allmulticast_enable = mlx5_allmulticast_enable,
1747 .allmulticast_disable = mlx5_allmulticast_disable,
1748 .link_update = mlx5_link_update,
1749 .stats_get = mlx5_stats_get,
1750 .stats_reset = mlx5_stats_reset,
1751 .xstats_get = mlx5_xstats_get,
1752 .xstats_reset = mlx5_xstats_reset,
1753 .xstats_get_names = mlx5_xstats_get_names,
1754 .fw_version_get = mlx5_fw_version_get,
1755 .dev_infos_get = mlx5_dev_infos_get,
1756 .read_clock = mlx5_txpp_read_clock,
1757 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1758 .vlan_filter_set = mlx5_vlan_filter_set,
1759 .rx_queue_setup = mlx5_rx_queue_setup,
1760 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1761 .tx_queue_setup = mlx5_tx_queue_setup,
1762 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1763 .rx_queue_release = mlx5_rx_queue_release,
1764 .tx_queue_release = mlx5_tx_queue_release,
1765 .rx_queue_start = mlx5_rx_queue_start,
1766 .rx_queue_stop = mlx5_rx_queue_stop,
1767 .tx_queue_start = mlx5_tx_queue_start,
1768 .tx_queue_stop = mlx5_tx_queue_stop,
1769 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1770 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1771 .mac_addr_remove = mlx5_mac_addr_remove,
1772 .mac_addr_add = mlx5_mac_addr_add,
1773 .mac_addr_set = mlx5_mac_addr_set,
1774 .set_mc_addr_list = mlx5_set_mc_addr_list,
1775 .mtu_set = mlx5_dev_set_mtu,
1776 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1777 .vlan_offload_set = mlx5_vlan_offload_set,
1778 .flow_ops_get = mlx5_flow_ops_get,
1779 .rxq_info_get = mlx5_rxq_info_get,
1780 .txq_info_get = mlx5_txq_info_get,
1781 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1782 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1783 .rx_queue_intr_enable = mlx5_rx_intr_enable,
1784 .rx_queue_intr_disable = mlx5_rx_intr_disable,
1785 .is_removed = mlx5_is_removed,
1786 .get_module_info = mlx5_get_module_info,
1787 .get_module_eeprom = mlx5_get_module_eeprom,
1788 .hairpin_cap_get = mlx5_hairpin_cap_get,
1789 .mtr_ops_get = mlx5_flow_meter_ops_get,
1790 .hairpin_bind = mlx5_hairpin_bind,
1791 .hairpin_unbind = mlx5_hairpin_unbind,
1792 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1793 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1794 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1795 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1796 .get_monitor_addr = mlx5_get_monitor_addr,
1800 * Verify and store value for device argument.
1803 * Key argument to verify.
1805 * Value associated with key.
1810 * 0 on success, a negative errno value otherwise and rte_errno is set.
1813 mlx5_args_check(const char *key, const char *val, void *opaque)
1815 struct mlx5_dev_config *config = opaque;
1819 /* No-op, port representors are processed in mlx5_dev_spawn(). */
1820 if (!strcmp(MLX5_REPRESENTOR, key))
1823 tmp = strtol(val, NULL, 0);
1826 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1829 if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1830 /* Negative values are acceptable for some keys only. */
1832 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1835 mod = tmp >= 0 ? tmp : -tmp;
1836 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1837 if (tmp > MLX5_CQE_RESP_FORMAT_L34H_STRIDX) {
1838 DRV_LOG(ERR, "invalid CQE compression "
1839 "format parameter");
1843 config->cqe_comp = !!tmp;
1844 config->cqe_comp_fmt = tmp;
1845 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1846 config->hw_padding = !!tmp;
1847 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1848 config->mprq.enabled = !!tmp;
1849 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1850 config->mprq.stride_num_n = tmp;
1851 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1852 config->mprq.stride_size_n = tmp;
1853 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1854 config->mprq.max_memcpy_len = tmp;
1855 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1856 config->mprq.min_rxqs_num = tmp;
1857 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1858 DRV_LOG(WARNING, "%s: deprecated parameter,"
1859 " converted to txq_inline_max", key);
1860 config->txq_inline_max = tmp;
1861 } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1862 config->txq_inline_max = tmp;
1863 } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1864 config->txq_inline_min = tmp;
1865 } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1866 config->txq_inline_mpw = tmp;
1867 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1868 config->txqs_inline = tmp;
1869 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1870 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1871 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1872 config->mps = !!tmp;
1873 } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1874 if (tmp != MLX5_TXDB_CACHED &&
1875 tmp != MLX5_TXDB_NCACHED &&
1876 tmp != MLX5_TXDB_HEURISTIC) {
1877 DRV_LOG(ERR, "invalid Tx doorbell "
1878 "mapping parameter");
1883 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1884 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1885 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1886 DRV_LOG(WARNING, "%s: deprecated parameter,"
1887 " converted to txq_inline_mpw", key);
1888 config->txq_inline_mpw = tmp;
1889 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1890 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1891 } else if (strcmp(MLX5_TX_PP, key) == 0) {
1893 DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1897 config->tx_pp = tmp;
1898 } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1899 config->tx_skew = tmp;
1900 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1901 config->rx_vec_en = !!tmp;
1902 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1903 config->l3_vxlan_en = !!tmp;
1904 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1905 config->vf_nl_en = !!tmp;
1906 } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1907 config->dv_esw_en = !!tmp;
1908 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1909 config->dv_flow_en = !!tmp;
1910 } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1911 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1912 tmp != MLX5_XMETA_MODE_META16 &&
1913 tmp != MLX5_XMETA_MODE_META32 &&
1914 tmp != MLX5_XMETA_MODE_MISS_INFO) {
1915 DRV_LOG(ERR, "invalid extensive "
1916 "metadata parameter");
1920 if (tmp != MLX5_XMETA_MODE_MISS_INFO)
1921 config->dv_xmeta_en = tmp;
1923 config->dv_miss_info = 1;
1924 } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1925 config->lacp_by_user = !!tmp;
1926 } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1927 config->mr_ext_memseg_en = !!tmp;
1928 } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1929 config->max_dump_files_num = tmp;
1930 } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1931 config->lro.timeout = tmp;
1932 } else if (strcmp(RTE_DEVARGS_KEY_CLASS, key) == 0) {
1933 DRV_LOG(DEBUG, "class argument is %s.", val);
1934 } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1935 config->log_hp_size = tmp;
1936 } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1937 if (tmp != MLX5_RCM_NONE &&
1938 tmp != MLX5_RCM_LIGHT &&
1939 tmp != MLX5_RCM_AGGR) {
1940 DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1944 config->reclaim_mode = tmp;
1945 } else if (strcmp(MLX5_SYS_MEM_EN, key) == 0) {
1946 config->sys_mem_en = !!tmp;
1947 } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
1948 config->decap_en = !!tmp;
1950 DRV_LOG(WARNING, "%s: unknown parameter", key);
1958 * Parse device parameters.
1961 * Pointer to device configuration structure.
1963 * Device arguments structure.
1966 * 0 on success, a negative errno value otherwise and rte_errno is set.
1969 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1971 const char **params = (const char *[]){
1972 MLX5_RXQ_CQE_COMP_EN,
1973 MLX5_RXQ_PKT_PAD_EN,
1975 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1976 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1977 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1980 MLX5_TXQ_INLINE_MIN,
1981 MLX5_TXQ_INLINE_MAX,
1982 MLX5_TXQ_INLINE_MPW,
1983 MLX5_TXQS_MIN_INLINE,
1986 MLX5_TXQ_MPW_HDR_DSEG_EN,
1987 MLX5_TXQ_MAX_INLINE_LEN,
1999 MLX5_MR_EXT_MEMSEG_EN,
2001 MLX5_MAX_DUMP_FILES_NUM,
2002 MLX5_LRO_TIMEOUT_USEC,
2003 RTE_DEVARGS_KEY_CLASS,
2010 struct rte_kvargs *kvlist;
2014 if (devargs == NULL)
2016 /* Following UGLY cast is done to pass checkpatch. */
2017 kvlist = rte_kvargs_parse(devargs->args, params);
2018 if (kvlist == NULL) {
2022 /* Process parameters. */
2023 for (i = 0; (params[i] != NULL); ++i) {
2024 if (rte_kvargs_count(kvlist, params[i])) {
2025 ret = rte_kvargs_process(kvlist, params[i],
2026 mlx5_args_check, config);
2029 rte_kvargs_free(kvlist);
2034 rte_kvargs_free(kvlist);
2039 * Configures the minimal amount of data to inline into WQE
2040 * while sending packets.
2042 * - the txq_inline_min has the maximal priority, if this
2043 * key is specified in devargs
2044 * - if DevX is enabled the inline mode is queried from the
2045 * device (HCA attributes and NIC vport context if needed).
2046 * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
2047 * and none (0 bytes) for other NICs
2050 * Verbs device parameters (name, port, switch_info) to spawn.
2052 * Device configuration parameters.
2055 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
2056 struct mlx5_dev_config *config)
2058 if (config->txq_inline_min != MLX5_ARG_UNSET) {
2059 /* Application defines size of inlined data explicitly. */
2060 switch (spawn->pci_dev->id.device_id) {
2061 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2062 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2063 if (config->txq_inline_min <
2064 (int)MLX5_INLINE_HSIZE_L2) {
2066 "txq_inline_mix aligned to minimal"
2067 " ConnectX-4 required value %d",
2068 (int)MLX5_INLINE_HSIZE_L2);
2069 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2075 if (config->hca_attr.eth_net_offloads) {
2076 /* We have DevX enabled, inline mode queried successfully. */
2077 switch (config->hca_attr.wqe_inline_mode) {
2078 case MLX5_CAP_INLINE_MODE_L2:
2079 /* outer L2 header must be inlined. */
2080 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2082 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
2083 /* No inline data are required by NIC. */
2084 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2085 config->hw_vlan_insert =
2086 config->hca_attr.wqe_vlan_insert;
2087 DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
2089 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
2090 /* inline mode is defined by NIC vport context. */
2091 if (!config->hca_attr.eth_virt)
2093 switch (config->hca_attr.vport_inline_mode) {
2094 case MLX5_INLINE_MODE_NONE:
2095 config->txq_inline_min =
2096 MLX5_INLINE_HSIZE_NONE;
2098 case MLX5_INLINE_MODE_L2:
2099 config->txq_inline_min =
2100 MLX5_INLINE_HSIZE_L2;
2102 case MLX5_INLINE_MODE_IP:
2103 config->txq_inline_min =
2104 MLX5_INLINE_HSIZE_L3;
2106 case MLX5_INLINE_MODE_TCP_UDP:
2107 config->txq_inline_min =
2108 MLX5_INLINE_HSIZE_L4;
2110 case MLX5_INLINE_MODE_INNER_L2:
2111 config->txq_inline_min =
2112 MLX5_INLINE_HSIZE_INNER_L2;
2114 case MLX5_INLINE_MODE_INNER_IP:
2115 config->txq_inline_min =
2116 MLX5_INLINE_HSIZE_INNER_L3;
2118 case MLX5_INLINE_MODE_INNER_TCP_UDP:
2119 config->txq_inline_min =
2120 MLX5_INLINE_HSIZE_INNER_L4;
2126 * We get here if we are unable to deduce
2127 * inline data size with DevX. Try PCI ID
2128 * to determine old NICs.
2130 switch (spawn->pci_dev->id.device_id) {
2131 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2132 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2133 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
2134 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
2135 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2136 config->hw_vlan_insert = 0;
2138 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
2139 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
2140 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
2141 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
2143 * These NICs support VLAN insertion from WQE and
2144 * report the wqe_vlan_insert flag. But there is the bug
2145 * and PFC control may be broken, so disable feature.
2147 config->hw_vlan_insert = 0;
2148 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2151 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2155 DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
2159 * Configures the metadata mask fields in the shared context.
2162 * Pointer to Ethernet device.
2165 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
2167 struct mlx5_priv *priv = dev->data->dev_private;
2168 struct mlx5_dev_ctx_shared *sh = priv->sh;
2169 uint32_t meta, mark, reg_c0;
2171 reg_c0 = ~priv->vport_meta_mask;
2172 switch (priv->config.dv_xmeta_en) {
2173 case MLX5_XMETA_MODE_LEGACY:
2175 mark = MLX5_FLOW_MARK_MASK;
2177 case MLX5_XMETA_MODE_META16:
2178 meta = reg_c0 >> rte_bsf32(reg_c0);
2179 mark = MLX5_FLOW_MARK_MASK;
2181 case MLX5_XMETA_MODE_META32:
2183 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
2191 if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
2192 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
2193 sh->dv_mark_mask, mark);
2195 sh->dv_mark_mask = mark;
2196 if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
2197 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
2198 sh->dv_meta_mask, meta);
2200 sh->dv_meta_mask = meta;
2201 if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
2202 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
2203 sh->dv_meta_mask, reg_c0);
2205 sh->dv_regc0_mask = reg_c0;
2206 DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
2207 DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
2208 DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
2209 DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
2213 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
2215 static const char *const dynf_names[] = {
2216 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
2217 RTE_MBUF_DYNFLAG_METADATA_NAME,
2218 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
2222 if (n < RTE_DIM(dynf_names))
2224 for (i = 0; i < RTE_DIM(dynf_names); i++) {
2225 if (names[i] == NULL)
2227 strcpy(names[i], dynf_names[i]);
2229 return RTE_DIM(dynf_names);
2233 * Comparison callback to sort device data.
2235 * This is meant to be used with qsort().
2238 * Pointer to pointer to first data object.
2240 * Pointer to pointer to second data object.
2243 * 0 if both objects are equal, less than 0 if the first argument is less
2244 * than the second, greater than 0 otherwise.
2247 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
2248 struct mlx5_dev_config *config)
2250 struct mlx5_dev_ctx_shared *sh = priv->sh;
2251 struct mlx5_dev_config *sh_conf = NULL;
2255 /* Nothing to compare for the single/first device. */
2256 if (sh->refcnt == 1)
2258 /* Find the device with shared context. */
2259 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
2260 struct mlx5_priv *opriv =
2261 rte_eth_devices[port_id].data->dev_private;
2263 if (opriv && opriv != priv && opriv->sh == sh) {
2264 sh_conf = &opriv->config;
2270 if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
2271 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
2272 " for shared %s context", sh->ibdev_name);
2276 if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
2277 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
2278 " for shared %s context", sh->ibdev_name);
2286 * Look for the ethernet device belonging to mlx5 driver.
2288 * @param[in] port_id
2289 * port_id to start looking for device.
2290 * @param[in] pci_dev
2291 * Pointer to the hint PCI device. When device is being probed
2292 * the its siblings (master and preceding representors might
2293 * not have assigned driver yet (because the mlx5_os_pci_probe()
2294 * is not completed yet, for this case match on hint PCI
2295 * device may be used to detect sibling device.
2298 * port_id of found device, RTE_MAX_ETHPORT if not found.
2301 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
2303 while (port_id < RTE_MAX_ETHPORTS) {
2304 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
2306 if (dev->state != RTE_ETH_DEV_UNUSED &&
2308 (dev->device == &pci_dev->device ||
2309 (dev->device->driver &&
2310 dev->device->driver->name &&
2311 !strcmp(dev->device->driver->name, MLX5_PCI_DRIVER_NAME))))
2315 if (port_id >= RTE_MAX_ETHPORTS)
2316 return RTE_MAX_ETHPORTS;
2321 * DPDK callback to remove a PCI device.
2323 * This function removes all Ethernet devices belong to a given PCI device.
2325 * @param[in] pci_dev
2326 * Pointer to the PCI device.
2329 * 0 on success, the function cannot fail.
2332 mlx5_pci_remove(struct rte_pci_device *pci_dev)
2337 RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
2339 * mlx5_dev_close() is not registered to secondary process,
2340 * call the close function explicitly for secondary process.
2342 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
2343 ret |= mlx5_dev_close(&rte_eth_devices[port_id]);
2345 ret |= rte_eth_dev_close(port_id);
2347 return ret == 0 ? 0 : -EIO;
2350 static const struct rte_pci_id mlx5_pci_id_map[] = {
2352 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2353 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
2356 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2357 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
2360 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2361 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
2364 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2365 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2368 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2369 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2372 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2373 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2376 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2377 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2380 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2381 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2384 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2385 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2388 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2389 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2392 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2393 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2396 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2397 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2400 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2401 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2404 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2405 PCI_DEVICE_ID_MELLANOX_CONNECTXVF)
2408 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2409 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2412 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2413 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2416 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2417 PCI_DEVICE_ID_MELLANOX_CONNECTX7)
2420 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2421 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF)
2428 static struct mlx5_pci_driver mlx5_driver = {
2429 .driver_class = MLX5_CLASS_NET,
2432 .name = MLX5_PCI_DRIVER_NAME,
2434 .id_table = mlx5_pci_id_map,
2435 .probe = mlx5_os_pci_probe,
2436 .remove = mlx5_pci_remove,
2437 .dma_map = mlx5_dma_map,
2438 .dma_unmap = mlx5_dma_unmap,
2439 .drv_flags = PCI_DRV_FLAGS,
2443 /* Initialize driver log type. */
2444 RTE_LOG_REGISTER_DEFAULT(mlx5_logtype, NOTICE)
2447 * Driver initialization routine.
2449 RTE_INIT(rte_mlx5_pmd_init)
2451 pthread_mutex_init(&mlx5_dev_ctx_list_mutex, NULL);
2453 /* Build the static tables for Verbs conversion. */
2454 mlx5_set_ptype_table();
2455 mlx5_set_cksum_table();
2456 mlx5_set_swp_types_table();
2458 mlx5_pci_driver_register(&mlx5_driver);
2461 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2462 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2463 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");