drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <errno.h>
  12
  13 #include <rte_malloc.h>
  14 #include <rte_ethdev_driver.h>
  15 #include <rte_ethdev_pci.h>
  16 #include <rte_pci.h>
  17 #include <rte_bus_pci.h>
  18 #include <rte_common.h>
  19 #include <rte_kvargs.h>
  20 #include <rte_rwlock.h>
  21 #include <rte_spinlock.h>
  22 #include <rte_string_fns.h>
  23 #include <rte_alarm.h>
  24
  25 #include <mlx5_glue.h>
  26 #include <mlx5_devx_cmds.h>
  27 #include <mlx5_common.h>
  28 #include <mlx5_common_os.h>
  29 #include <mlx5_common_mp.h>
  30 #include <mlx5_common_pci.h>
  31 #include <mlx5_malloc.h>
  32
  33 #include "mlx5_defs.h"
  34 #include "mlx5.h"
  35 #include "mlx5_utils.h"
  36 #include "mlx5_rxtx.h"
  37 #include "mlx5_autoconf.h"
  38 #include "mlx5_mr.h"
  39 #include "mlx5_flow.h"
  40 #include "rte_pmd_mlx5.h"
  41
  42 /* Device parameter to enable RX completion queue compression. */
  43 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  44
  45 /* Device parameter to enable RX completion entry padding to 128B. */
  46 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
  47
  48 /* Device parameter to enable padding Rx packet to cacheline size. */
  49 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  50
  51 /* Device parameter to enable Multi-Packet Rx queue. */
  52 #define MLX5_RX_MPRQ_EN "mprq_en"
  53
  54 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  55 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  56
  57 /* Device parameter to configure log 2 of the stride size for MPRQ. */
  58 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
  59
  60 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  61 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  62
  63 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  64 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  65
  66 /* Device parameter to configure inline send. Deprecated, ignored.*/
  67 #define MLX5_TXQ_INLINE "txq_inline"
  68
  69 /* Device parameter to limit packet size to inline with ordinary SEND. */
  70 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
  71
  72 /* Device parameter to configure minimal data size to inline. */
  73 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
  74
  75 /* Device parameter to limit packet size to inline with Enhanced MPW. */
  76 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
  77
  78 /*
  79  * Device parameter to configure the number of TX queues threshold for
  80  * enabling inline send.
  81  */
  82 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  83
  84 /*
  85  * Device parameter to configure the number of TX queues threshold for
  86  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
  87  */
  88 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
  89
  90 /* Device parameter to enable multi-packet send WQEs. */
  91 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
  92
  93 /*
  94  * Device parameter to force doorbell register mapping
  95  * to non-cahed region eliminating the extra write memory barrier.
  96  */
  97 #define MLX5_TX_DB_NC "tx_db_nc"
  98
  99 /*
 100  * Device parameter to include 2 dsegs in the title WQEBB.
 101  * Deprecated, ignored.
 102  */
 103 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
 104
 105 /*
 106  * Device parameter to limit the size of inlining packet.
 107  * Deprecated, ignored.
 108  */
 109 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
 110
 111 /*
 112  * Device parameter to enable Tx scheduling on timestamps
 113  * and specify the packet pacing granularity in nanoseconds.
 114  */
 115 #define MLX5_TX_PP "tx_pp"
 116
 117 /*
 118  * Device parameter to specify skew in nanoseconds on Tx datapath,
 119  * it represents the time between SQ start WQE processing and
 120  * appearing actual packet data on the wire.
 121  */
 122 #define MLX5_TX_SKEW "tx_skew"
 123
 124 /*
 125  * Device parameter to enable hardware Tx vector.
 126  * Deprecated, ignored (no vectorized Tx routines anymore).
 127  */
 128 #define MLX5_TX_VEC_EN "tx_vec_en"
 129
 130 /* Device parameter to enable hardware Rx vector. */
 131 #define MLX5_RX_VEC_EN "rx_vec_en"
 132
 133 /* Allow L3 VXLAN flow creation. */
 134 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 135
 136 /* Activate DV E-Switch flow steering. */
 137 #define MLX5_DV_ESW_EN "dv_esw_en"
 138
 139 /* Activate DV flow steering. */
 140 #define MLX5_DV_FLOW_EN "dv_flow_en"
 141
 142 /* Enable extensive flow metadata support. */
 143 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
 144
 145 /* Device parameter to let the user manage the lacp traffic of bonded device */
 146 #define MLX5_LACP_BY_USER "lacp_by_user"
 147
 148 /* Activate Netlink support in VF mode. */
 149 #define MLX5_VF_NL_EN "vf_nl_en"
 150
 151 /* Enable extending memsegs when creating a MR. */
 152 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 153
 154 /* Select port representors to instantiate. */
 155 #define MLX5_REPRESENTOR "representor"
 156
 157 /* Device parameter to configure the maximum number of dump files per queue. */
 158 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
 159
 160 /* Configure timeout of LRO session (in microseconds). */
 161 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
 162
 163 /*
 164  * Device parameter to configure the total data buffer size for a single
 165  * hairpin queue (logarithm value).
 166  */
 167 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
 168
 169 /* Flow memory reclaim mode. */
 170 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
 171
 172 /* The default memory allocator used in PMD. */
 173 #define MLX5_SYS_MEM_EN "sys_mem_en"
 174 /* Decap will be used or not. */
 175 #define MLX5_DECAP_EN "decap_en"
 176
 177 /* Shared memory between primary and secondary processes. */
 178 struct mlx5_shared_data *mlx5_shared_data;
 179
 180 /** Driver-specific log messages type. */
 181 int mlx5_logtype;
 182
 183 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
 184                                                 LIST_HEAD_INITIALIZER();
 185 static pthread_mutex_t mlx5_dev_ctx_list_mutex = PTHREAD_MUTEX_INITIALIZER;
 186
 187 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
 188 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 189         {
 190                 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
 191                 .trunk_size = 64,
 192                 .grow_trunk = 3,
 193                 .grow_shift = 2,
 194                 .need_lock = 1,
 195                 .release_mem_en = 1,
 196                 .malloc = mlx5_malloc,
 197                 .free = mlx5_free,
 198                 .type = "mlx5_encap_decap_ipool",
 199         },
 200         {
 201                 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
 202                 .trunk_size = 64,
 203                 .grow_trunk = 3,
 204                 .grow_shift = 2,
 205                 .need_lock = 1,
 206                 .release_mem_en = 1,
 207                 .malloc = mlx5_malloc,
 208                 .free = mlx5_free,
 209                 .type = "mlx5_push_vlan_ipool",
 210         },
 211         {
 212                 .size = sizeof(struct mlx5_flow_dv_tag_resource),
 213                 .trunk_size = 64,
 214                 .grow_trunk = 3,
 215                 .grow_shift = 2,
 216                 .need_lock = 1,
 217                 .release_mem_en = 1,
 218                 .malloc = mlx5_malloc,
 219                 .free = mlx5_free,
 220                 .type = "mlx5_tag_ipool",
 221         },
 222         {
 223                 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
 224                 .trunk_size = 64,
 225                 .grow_trunk = 3,
 226                 .grow_shift = 2,
 227                 .need_lock = 1,
 228                 .release_mem_en = 1,
 229                 .malloc = mlx5_malloc,
 230                 .free = mlx5_free,
 231                 .type = "mlx5_port_id_ipool",
 232         },
 233         {
 234                 .size = sizeof(struct mlx5_flow_tbl_data_entry),
 235                 .trunk_size = 64,
 236                 .grow_trunk = 3,
 237                 .grow_shift = 2,
 238                 .need_lock = 1,
 239                 .release_mem_en = 1,
 240                 .malloc = mlx5_malloc,
 241                 .free = mlx5_free,
 242                 .type = "mlx5_jump_ipool",
 243         },
 244         {
 245                 .size = sizeof(struct mlx5_flow_dv_sample_resource),
 246                 .trunk_size = 64,
 247                 .grow_trunk = 3,
 248                 .grow_shift = 2,
 249                 .need_lock = 1,
 250                 .release_mem_en = 1,
 251                 .malloc = mlx5_malloc,
 252                 .free = mlx5_free,
 253                 .type = "mlx5_sample_ipool",
 254         },
 255         {
 256                 .size = sizeof(struct mlx5_flow_dv_dest_array_resource),
 257                 .trunk_size = 64,
 258                 .grow_trunk = 3,
 259                 .grow_shift = 2,
 260                 .need_lock = 1,
 261                 .release_mem_en = 1,
 262                 .malloc = mlx5_malloc,
 263                 .free = mlx5_free,
 264                 .type = "mlx5_dest_array_ipool",
 265         },
 266 #endif
 267         {
 268                 .size = sizeof(struct mlx5_flow_meter),
 269                 .trunk_size = 64,
 270                 .grow_trunk = 3,
 271                 .grow_shift = 2,
 272                 .need_lock = 1,
 273                 .release_mem_en = 1,
 274                 .malloc = mlx5_malloc,
 275                 .free = mlx5_free,
 276                 .type = "mlx5_meter_ipool",
 277         },
 278         {
 279                 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
 280                 .trunk_size = 64,
 281                 .grow_trunk = 3,
 282                 .grow_shift = 2,
 283                 .need_lock = 1,
 284                 .release_mem_en = 1,
 285                 .malloc = mlx5_malloc,
 286                 .free = mlx5_free,
 287                 .type = "mlx5_mcp_ipool",
 288         },
 289         {
 290                 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
 291                 .trunk_size = 64,
 292                 .grow_trunk = 3,
 293                 .grow_shift = 2,
 294                 .need_lock = 1,
 295                 .release_mem_en = 1,
 296                 .malloc = mlx5_malloc,
 297                 .free = mlx5_free,
 298                 .type = "mlx5_hrxq_ipool",
 299         },
 300         {
 301                 /*
 302                  * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
 303                  * It set in run time according to PCI function configuration.
 304                  */
 305                 .size = 0,
 306                 .trunk_size = 64,
 307                 .grow_trunk = 3,
 308                 .grow_shift = 2,
 309                 .need_lock = 1,
 310                 .release_mem_en = 1,
 311                 .malloc = mlx5_malloc,
 312                 .free = mlx5_free,
 313                 .type = "mlx5_flow_handle_ipool",
 314         },
 315         {
 316                 .size = sizeof(struct rte_flow),
 317                 .trunk_size = 4096,
 318                 .need_lock = 1,
 319                 .release_mem_en = 1,
 320                 .malloc = mlx5_malloc,
 321                 .free = mlx5_free,
 322                 .type = "rte_flow_ipool",
 323         },
 324         {
 325                 .size = 0,
 326                 .need_lock = 1,
 327                 .type = "mlx5_flow_rss_id_ipool",
 328         },
 329         {
 330                 .size = 0,
 331                 .need_lock = 1,
 332                 .type = "mlx5_flow_tnl_flow_ipool",
 333         },
 334         {
 335                 .size = 0,
 336                 .need_lock = 1,
 337                 .type = "mlx5_flow_tnl_tbl_ipool",
 338         },
 339 };
 340
 341
 342 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
 343 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
 344
 345 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
 346
 347 /**
 348  * Initialize the ASO aging management structure.
 349  *
 350  * @param[in] sh
 351  *   Pointer to mlx5_dev_ctx_shared object to free
 352  *
 353  * @return
 354  *   0 on success, a negative errno value otherwise and rte_errno is set.
 355  */
 356 int
 357 mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh)
 358 {
 359         int err;
 360
 361         if (sh->aso_age_mng)
 362                 return 0;
 363         sh->aso_age_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->aso_age_mng),
 364                                       RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 365         if (!sh->aso_age_mng) {
 366                 DRV_LOG(ERR, "aso_age_mng allocation was failed.");
 367                 rte_errno = ENOMEM;
 368                 return -ENOMEM;
 369         }
 370         err = mlx5_aso_queue_init(sh);
 371         if (err) {
 372                 mlx5_free(sh->aso_age_mng);
 373                 return -1;
 374         }
 375         rte_spinlock_init(&sh->aso_age_mng->resize_sl);
 376         rte_spinlock_init(&sh->aso_age_mng->free_sl);
 377         LIST_INIT(&sh->aso_age_mng->free);
 378         return 0;
 379 }
 380
 381 /**
 382  * Close and release all the resources of the ASO aging management structure.
 383  *
 384  * @param[in] sh
 385  *   Pointer to mlx5_dev_ctx_shared object to free.
 386  */
 387 static void
 388 mlx5_flow_aso_age_mng_close(struct mlx5_dev_ctx_shared *sh)
 389 {
 390         int i, j;
 391
 392         mlx5_aso_queue_stop(sh);
 393         mlx5_aso_queue_uninit(sh);
 394         if (sh->aso_age_mng->pools) {
 395                 struct mlx5_aso_age_pool *pool;
 396
 397                 for (i = 0; i < sh->aso_age_mng->next; ++i) {
 398                         pool = sh->aso_age_mng->pools[i];
 399                         claim_zero(mlx5_devx_cmd_destroy
 400                                                 (pool->flow_hit_aso_obj));
 401                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j)
 402                                 if (pool->actions[j].dr_action)
 403                                         claim_zero
 404                                                 (mlx5_glue->destroy_flow_action
 405                                                   (pool->actions[j].dr_action));
 406                         mlx5_free(pool);
 407                 }
 408                 mlx5_free(sh->aso_age_mng->pools);
 409         }
 410         memset(&sh->aso_age_mng, 0, sizeof(sh->aso_age_mng));
 411 }
 412
 413 /**
 414  * Initialize the shared aging list information per port.
 415  *
 416  * @param[in] sh
 417  *   Pointer to mlx5_dev_ctx_shared object.
 418  */
 419 static void
 420 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
 421 {
 422         uint32_t i;
 423         struct mlx5_age_info *age_info;
 424
 425         for (i = 0; i < sh->max_port; i++) {
 426                 age_info = &sh->port[i].age_info;
 427                 age_info->flags = 0;
 428                 TAILQ_INIT(&age_info->aged_counters);
 429                 rte_spinlock_init(&age_info->aged_sl);
 430                 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
 431         }
 432 }
 433
 434 /**
 435  * Initialize the counters management structure.
 436  *
 437  * @param[in] sh
 438  *   Pointer to mlx5_dev_ctx_shared object to free
 439  */
 440 static void
 441 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
 442 {
 443         int i;
 444
 445         memset(&sh->cmng, 0, sizeof(sh->cmng));
 446         TAILQ_INIT(&sh->cmng.flow_counters);
 447         sh->cmng.min_id = MLX5_CNT_BATCH_OFFSET;
 448         sh->cmng.max_id = -1;
 449         sh->cmng.last_pool_idx = POOL_IDX_INVALID;
 450         rte_spinlock_init(&sh->cmng.pool_update_sl);
 451         for (i = 0; i < MLX5_COUNTER_TYPE_MAX; i++) {
 452                 TAILQ_INIT(&sh->cmng.counters[i]);
 453                 rte_spinlock_init(&sh->cmng.csl[i]);
 454         }
 455 }
 456
 457 /**
 458  * Destroy all the resources allocated for a counter memory management.
 459  *
 460  * @param[in] mng
 461  *   Pointer to the memory management structure.
 462  */
 463 static void
 464 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
 465 {
 466         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
 467
 468         LIST_REMOVE(mng, next);
 469         claim_zero(mlx5_devx_cmd_destroy(mng->dm));
 470         claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
 471         mlx5_free(mem);
 472 }
 473
 474 /**
 475  * Close and release all the resources of the counters management.
 476  *
 477  * @param[in] sh
 478  *   Pointer to mlx5_dev_ctx_shared object to free.
 479  */
 480 static void
 481 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
 482 {
 483         struct mlx5_counter_stats_mem_mng *mng;
 484         int i, j;
 485         int retries = 1024;
 486
 487         rte_errno = 0;
 488         while (--retries) {
 489                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
 490                 if (rte_errno != EINPROGRESS)
 491                         break;
 492                 rte_pause();
 493         }
 494
 495         if (sh->cmng.pools) {
 496                 struct mlx5_flow_counter_pool *pool;
 497                 uint16_t n_valid = sh->cmng.n_valid;
 498                 bool fallback = sh->cmng.counter_fallback;
 499
 500                 for (i = 0; i < n_valid; ++i) {
 501                         pool = sh->cmng.pools[i];
 502                         if (!fallback && pool->min_dcs)
 503                                 claim_zero(mlx5_devx_cmd_destroy
 504                                                                (pool->min_dcs));
 505                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
 506                                 struct mlx5_flow_counter *cnt =
 507                                                 MLX5_POOL_GET_CNT(pool, j);
 508
 509                                 if (cnt->action)
 510                                         claim_zero
 511                                          (mlx5_glue->destroy_flow_action
 512                                           (cnt->action));
 513                                 if (fallback && MLX5_POOL_GET_CNT
 514                                     (pool, j)->dcs_when_free)
 515                                         claim_zero(mlx5_devx_cmd_destroy
 516                                                    (cnt->dcs_when_free));
 517                         }
 518                         mlx5_free(pool);
 519                 }
 520                 mlx5_free(sh->cmng.pools);
 521         }
 522         mng = LIST_FIRST(&sh->cmng.mem_mngs);
 523         while (mng) {
 524                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
 525                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
 526         }
 527         memset(&sh->cmng, 0, sizeof(sh->cmng));
 528 }
 529
 530 /* Send FLOW_AGED event if needed. */
 531 void
 532 mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh)
 533 {
 534         struct mlx5_age_info *age_info;
 535         uint32_t i;
 536
 537         for (i = 0; i < sh->max_port; i++) {
 538                 age_info = &sh->port[i].age_info;
 539                 if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW))
 540                         continue;
 541                 if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER))
 542                         rte_eth_dev_callback_process
 543                                 (&rte_eth_devices[sh->port[i].devx_ih_port_id],
 544                                 RTE_ETH_EVENT_FLOW_AGED, NULL);
 545                 age_info->flags = 0;
 546         }
 547 }
 548
 549 /**
 550  * Initialize the flow resources' indexed mempool.
 551  *
 552  * @param[in] sh
 553  *   Pointer to mlx5_dev_ctx_shared object.
 554  * @param[in] sh
 555  *   Pointer to user dev config.
 556  */
 557 static void
 558 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
 559                        const struct mlx5_dev_config *config)
 560 {
 561         uint8_t i;
 562         struct mlx5_indexed_pool_config cfg;
 563
 564         for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
 565                 cfg = mlx5_ipool_cfg[i];
 566                 switch (i) {
 567                 default:
 568                         break;
 569                 /*
 570                  * Set MLX5_IPOOL_MLX5_FLOW ipool size
 571                  * according to PCI function flow configuration.
 572                  */
 573                 case MLX5_IPOOL_MLX5_FLOW:
 574                         cfg.size = config->dv_flow_en ?
 575                                 sizeof(struct mlx5_flow_handle) :
 576                                 MLX5_FLOW_HANDLE_VERBS_SIZE;
 577                         break;
 578                 }
 579                 if (config->reclaim_mode)
 580                         cfg.release_mem_en = 1;
 581                 sh->ipool[i] = mlx5_ipool_create(&cfg);
 582         }
 583 }
 584
 585 /**
 586  * Release the flow resources' indexed mempool.
 587  *
 588  * @param[in] sh
 589  *   Pointer to mlx5_dev_ctx_shared object.
 590  */
 591 static void
 592 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
 593 {
 594         uint8_t i;
 595
 596         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 597                 mlx5_ipool_destroy(sh->ipool[i]);
 598 }
 599
 600 /*
 601  * Check if dynamic flex parser for eCPRI already exists.
 602  *
 603  * @param dev
 604  *   Pointer to Ethernet device structure.
 605  *
 606  * @return
 607  *   true on exists, false on not.
 608  */
 609 bool
 610 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
 611 {
 612         struct mlx5_priv *priv = dev->data->dev_private;
 613         struct mlx5_flex_parser_profiles *prf =
 614                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 615
 616         return !!prf->obj;
 617 }
 618
 619 /*
 620  * Allocation of a flex parser for eCPRI. Once created, this parser related
 621  * resources will be held until the device is closed.
 622  *
 623  * @param dev
 624  *   Pointer to Ethernet device structure.
 625  *
 626  * @return
 627  *   0 on success, a negative errno value otherwise and rte_errno is set.
 628  */
 629 int
 630 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
 631 {
 632         struct mlx5_priv *priv = dev->data->dev_private;
 633         struct mlx5_flex_parser_profiles *prf =
 634                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 635         struct mlx5_devx_graph_node_attr node = {
 636                 .modify_field_select = 0,
 637         };
 638         uint32_t ids[8];
 639         int ret;
 640
 641         if (!priv->config.hca_attr.parse_graph_flex_node) {
 642                 DRV_LOG(ERR, "Dynamic flex parser is not supported "
 643                         "for device %s.", priv->dev_data->name);
 644                 return -ENOTSUP;
 645         }
 646         node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
 647         /* 8 bytes now: 4B common header + 4B message body header. */
 648         node.header_length_base_value = 0x8;
 649         /* After MAC layer: Ether / VLAN. */
 650         node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
 651         /* Type of compared condition should be 0xAEFE in the L2 layer. */
 652         node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
 653         /* Sample #0: type in common header. */
 654         node.sample[0].flow_match_sample_en = 1;
 655         /* Fixed offset. */
 656         node.sample[0].flow_match_sample_offset_mode = 0x0;
 657         /* Only the 2nd byte will be used. */
 658         node.sample[0].flow_match_sample_field_base_offset = 0x0;
 659         /* Sample #1: message payload. */
 660         node.sample[1].flow_match_sample_en = 1;
 661         /* Fixed offset. */
 662         node.sample[1].flow_match_sample_offset_mode = 0x0;
 663         /*
 664          * Only the first two bytes will be used right now, and its offset will
 665          * start after the common header that with the length of a DW(u32).
 666          */
 667         node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
 668         prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->ctx, &node);
 669         if (!prf->obj) {
 670                 DRV_LOG(ERR, "Failed to create flex parser node object.");
 671                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 672         }
 673         prf->num = 2;
 674         ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
 675         if (ret) {
 676                 DRV_LOG(ERR, "Failed to query sample IDs.");
 677                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 678         }
 679         prf->offset[0] = 0x0;
 680         prf->offset[1] = sizeof(uint32_t);
 681         prf->ids[0] = ids[0];
 682         prf->ids[1] = ids[1];
 683         return 0;
 684 }
 685
 686 /*
 687  * Destroy the flex parser node, including the parser itself, input / output
 688  * arcs and DW samples. Resources could be reused then.
 689  *
 690  * @param dev
 691  *   Pointer to Ethernet device structure.
 692  */
 693 static void
 694 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
 695 {
 696         struct mlx5_priv *priv = dev->data->dev_private;
 697         struct mlx5_flex_parser_profiles *prf =
 698                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 699
 700         if (prf->obj)
 701                 mlx5_devx_cmd_destroy(prf->obj);
 702         prf->obj = NULL;
 703 }
 704
 705 /*
 706  * Allocate Rx and Tx UARs in robust fashion.
 707  * This routine handles the following UAR allocation issues:
 708  *
 709  *  - tries to allocate the UAR with the most appropriate memory
 710  *    mapping type from the ones supported by the host
 711  *
 712  *  - tries to allocate the UAR with non-NULL base address
 713  *    OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
 714  *    UAR base address if UAR was not the first object in the UAR page.
 715  *    It caused the PMD failure and we should try to get another UAR
 716  *    till we get the first one with non-NULL base address returned.
 717  */
 718 static int
 719 mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh,
 720                      const struct mlx5_dev_config *config)
 721 {
 722         uint32_t uar_mapping, retry;
 723         int err = 0;
 724         void *base_addr;
 725
 726         for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
 727 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
 728                 /* Control the mapping type according to the settings. */
 729                 uar_mapping = (config->dbnc == MLX5_TXDB_NCACHED) ?
 730                               MLX5DV_UAR_ALLOC_TYPE_NC :
 731                               MLX5DV_UAR_ALLOC_TYPE_BF;
 732 #else
 733                 RTE_SET_USED(config);
 734                 /*
 735                  * It seems we have no way to control the memory mapping type
 736                  * for the UAR, the default "Write-Combining" type is supposed.
 737                  * The UAR initialization on queue creation queries the
 738                  * actual mapping type done by Verbs/kernel and setups the
 739                  * PMD datapath accordingly.
 740                  */
 741                 uar_mapping = 0;
 742 #endif
 743                 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, uar_mapping);
 744 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
 745                 if (!sh->tx_uar &&
 746                     uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
 747                         if (config->dbnc == MLX5_TXDB_CACHED ||
 748                             config->dbnc == MLX5_TXDB_HEURISTIC)
 749                                 DRV_LOG(WARNING, "Devarg tx_db_nc setting "
 750                                                  "is not supported by DevX");
 751                         /*
 752                          * In some environments like virtual machine
 753                          * the Write Combining mapped might be not supported
 754                          * and UAR allocation fails. We try "Non-Cached"
 755                          * mapping for the case. The tx_burst routines take
 756                          * the UAR mapping type into account on UAR setup
 757                          * on queue creation.
 758                          */
 759                         DRV_LOG(WARNING, "Failed to allocate Tx DevX UAR (BF)");
 760                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
 761                         sh->tx_uar = mlx5_glue->devx_alloc_uar
 762                                                         (sh->ctx, uar_mapping);
 763                 } else if (!sh->tx_uar &&
 764                            uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) {
 765                         if (config->dbnc == MLX5_TXDB_NCACHED)
 766                                 DRV_LOG(WARNING, "Devarg tx_db_nc settings "
 767                                                  "is not supported by DevX");
 768                         /*
 769                          * If Verbs/kernel does not support "Non-Cached"
 770                          * try the "Write-Combining".
 771                          */
 772                         DRV_LOG(WARNING, "Failed to allocate Tx DevX UAR (NC)");
 773                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;
 774                         sh->tx_uar = mlx5_glue->devx_alloc_uar
 775                                                         (sh->ctx, uar_mapping);
 776                 }
 777 #endif
 778                 if (!sh->tx_uar) {
 779                         DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (BF/NC)");
 780                         err = ENOMEM;
 781                         goto exit;
 782                 }
 783                 base_addr = mlx5_os_get_devx_uar_base_addr(sh->tx_uar);
 784                 if (base_addr)
 785                         break;
 786                 /*
 787                  * The UARs are allocated by rdma_core within the
 788                  * IB device context, on context closure all UARs
 789                  * will be freed, should be no memory/object leakage.
 790                  */
 791                 DRV_LOG(WARNING, "Retrying to allocate Tx DevX UAR");
 792                 sh->tx_uar = NULL;
 793         }
 794         /* Check whether we finally succeeded with valid UAR allocation. */
 795         if (!sh->tx_uar) {
 796                 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (NULL base)");
 797                 err = ENOMEM;
 798                 goto exit;
 799         }
 800         for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
 801                 uar_mapping = 0;
 802                 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
 803                                                         (sh->ctx, uar_mapping);
 804 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
 805                 if (!sh->devx_rx_uar &&
 806                     uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
 807                         /*
 808                          * Rx UAR is used to control interrupts only,
 809                          * should be no datapath noticeable impact,
 810                          * can try "Non-Cached" mapping safely.
 811                          */
 812                         DRV_LOG(WARNING, "Failed to allocate Rx DevX UAR (BF)");
 813                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
 814                         sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
 815                                                         (sh->ctx, uar_mapping);
 816                 }
 817 #endif
 818                 if (!sh->devx_rx_uar) {
 819                         DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (BF/NC)");
 820                         err = ENOMEM;
 821                         goto exit;
 822                 }
 823                 base_addr = mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar);
 824                 if (base_addr)
 825                         break;
 826                 /*
 827                  * The UARs are allocated by rdma_core within the
 828                  * IB device context, on context closure all UARs
 829                  * will be freed, should be no memory/object leakage.
 830                  */
 831                 DRV_LOG(WARNING, "Retrying to allocate Rx DevX UAR");
 832                 sh->devx_rx_uar = NULL;
 833         }
 834         /* Check whether we finally succeeded with valid UAR allocation. */
 835         if (!sh->devx_rx_uar) {
 836                 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (NULL base)");
 837                 err = ENOMEM;
 838         }
 839 exit:
 840         return err;
 841 }
 842
 843 /**
 844  * Allocate shared device context. If there is multiport device the
 845  * master and representors will share this context, if there is single
 846  * port dedicated device, the context will be used by only given
 847  * port due to unification.
 848  *
 849  * Routine first searches the context for the specified device name,
 850  * if found the shared context assumed and reference counter is incremented.
 851  * If no context found the new one is created and initialized with specified
 852  * device context and parameters.
 853  *
 854  * @param[in] spawn
 855  *   Pointer to the device attributes (name, port, etc).
 856  * @param[in] config
 857  *   Pointer to device configuration structure.
 858  *
 859  * @return
 860  *   Pointer to mlx5_dev_ctx_shared object on success,
 861  *   otherwise NULL and rte_errno is set.
 862  */
 863 struct mlx5_dev_ctx_shared *
 864 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
 865                            const struct mlx5_dev_config *config)
 866 {
 867         struct mlx5_dev_ctx_shared *sh;
 868         int err = 0;
 869         uint32_t i;
 870         struct mlx5_devx_tis_attr tis_attr = { 0 };
 871
 872         MLX5_ASSERT(spawn);
 873         /* Secondary process should not create the shared context. */
 874         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 875         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
 876         /* Search for IB context by device name. */
 877         LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
 878                 if (!strcmp(sh->ibdev_name,
 879                         mlx5_os_get_dev_device_name(spawn->phys_dev))) {
 880                         sh->refcnt++;
 881                         goto exit;
 882                 }
 883         }
 884         /* No device found, we have to create new shared context. */
 885         MLX5_ASSERT(spawn->max_port);
 886         sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
 887                          sizeof(struct mlx5_dev_ctx_shared) +
 888                          spawn->max_port *
 889                          sizeof(struct mlx5_dev_shared_port),
 890                          RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 891         if (!sh) {
 892                 DRV_LOG(ERR, "shared context allocation failure");
 893                 rte_errno  = ENOMEM;
 894                 goto exit;
 895         }
 896         err = mlx5_os_open_device(spawn, config, sh);
 897         if (!sh->ctx)
 898                 goto error;
 899         err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
 900         if (err) {
 901                 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
 902                 goto error;
 903         }
 904         sh->refcnt = 1;
 905         sh->max_port = spawn->max_port;
 906         strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
 907                 sizeof(sh->ibdev_name) - 1);
 908         strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
 909                 sizeof(sh->ibdev_path) - 1);
 910         /*
 911          * Setting port_id to max unallowed value means
 912          * there is no interrupt subhandler installed for
 913          * the given port index i.
 914          */
 915         for (i = 0; i < sh->max_port; i++) {
 916                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
 917                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
 918         }
 919         sh->pd = mlx5_glue->alloc_pd(sh->ctx);
 920         if (sh->pd == NULL) {
 921                 DRV_LOG(ERR, "PD allocation failure");
 922                 err = ENOMEM;
 923                 goto error;
 924         }
 925         if (sh->devx) {
 926                 /* Query the EQN for this core. */
 927                 err = mlx5_glue->devx_query_eqn(sh->ctx, 0, &sh->eqn);
 928                 if (err) {
 929                         rte_errno = errno;
 930                         DRV_LOG(ERR, "Failed to query event queue number %d.",
 931                                 rte_errno);
 932                         goto error;
 933                 }
 934                 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
 935                 if (err) {
 936                         DRV_LOG(ERR, "Fail to extract pdn from PD");
 937                         goto error;
 938                 }
 939                 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
 940                 if (!sh->td) {
 941                         DRV_LOG(ERR, "TD allocation failure");
 942                         err = ENOMEM;
 943                         goto error;
 944                 }
 945                 tis_attr.transport_domain = sh->td->id;
 946                 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
 947                 if (!sh->tis) {
 948                         DRV_LOG(ERR, "TIS allocation failure");
 949                         err = ENOMEM;
 950                         goto error;
 951                 }
 952                 err = mlx5_alloc_rxtx_uars(sh, config);
 953                 if (err)
 954                         goto error;
 955                 MLX5_ASSERT(sh->tx_uar);
 956                 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar));
 957
 958                 MLX5_ASSERT(sh->devx_rx_uar);
 959                 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar));
 960         }
 961 #ifndef RTE_ARCH_64
 962         /* Initialize UAR access locks for 32bit implementations. */
 963         rte_spinlock_init(&sh->uar_lock_cq);
 964         for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
 965                 rte_spinlock_init(&sh->uar_lock[i]);
 966 #endif
 967         /*
 968          * Once the device is added to the list of memory event
 969          * callback, its global MR cache table cannot be expanded
 970          * on the fly because of deadlock. If it overflows, lookup
 971          * should be done by searching MR list linearly, which is slow.
 972          *
 973          * At this point the device is not added to the memory
 974          * event list yet, context is just being created.
 975          */
 976         err = mlx5_mr_btree_init(&sh->share_cache.cache,
 977                                  MLX5_MR_BTREE_CACHE_N * 2,
 978                                  spawn->pci_dev->device.numa_node);
 979         if (err) {
 980                 err = rte_errno;
 981                 goto error;
 982         }
 983         mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
 984                               &sh->share_cache.dereg_mr_cb);
 985         mlx5_os_dev_shared_handler_install(sh);
 986         sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
 987         if (!sh->cnt_id_tbl) {
 988                 err = rte_errno;
 989                 goto error;
 990         }
 991         mlx5_flow_aging_init(sh);
 992         mlx5_flow_counters_mng_init(sh);
 993         mlx5_flow_ipool_create(sh, config);
 994         /* Add device to memory callback list. */
 995         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 996         LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
 997                          sh, mem_event_cb);
 998         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 999         /* Add context to the global device list. */
1000         LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
1001 exit:
1002         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1003         return sh;
1004 error:
1005         pthread_mutex_destroy(&sh->txpp.mutex);
1006         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1007         MLX5_ASSERT(sh);
1008         if (sh->cnt_id_tbl)
1009                 mlx5_l3t_destroy(sh->cnt_id_tbl);
1010         if (sh->tis)
1011                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1012         if (sh->td)
1013                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1014         if (sh->devx_rx_uar)
1015                 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1016         if (sh->tx_uar)
1017                 mlx5_glue->devx_free_uar(sh->tx_uar);
1018         if (sh->pd)
1019                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
1020         if (sh->ctx)
1021                 claim_zero(mlx5_glue->close_device(sh->ctx));
1022         mlx5_free(sh);
1023         MLX5_ASSERT(err > 0);
1024         rte_errno = err;
1025         return NULL;
1026 }
1027
1028 /**
1029  * Free shared IB device context. Decrement counter and if zero free
1030  * all allocated resources and close handles.
1031  *
1032  * @param[in] sh
1033  *   Pointer to mlx5_dev_ctx_shared object to free
1034  */
1035 void
1036 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
1037 {
1038         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1039 #ifdef RTE_LIBRTE_MLX5_DEBUG
1040         /* Check the object presence in the list. */
1041         struct mlx5_dev_ctx_shared *lctx;
1042
1043         LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
1044                 if (lctx == sh)
1045                         break;
1046         MLX5_ASSERT(lctx);
1047         if (lctx != sh) {
1048                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
1049                 goto exit;
1050         }
1051 #endif
1052         MLX5_ASSERT(sh);
1053         MLX5_ASSERT(sh->refcnt);
1054         /* Secondary process should not free the shared context. */
1055         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1056         if (--sh->refcnt)
1057                 goto exit;
1058         /* Remove from memory callback device list. */
1059         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1060         LIST_REMOVE(sh, mem_event_cb);
1061         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1062         /* Release created Memory Regions. */
1063         mlx5_mr_release_cache(&sh->share_cache);
1064         /* Remove context from the global device list. */
1065         LIST_REMOVE(sh, next);
1066         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1067         /*
1068          *  Ensure there is no async event handler installed.
1069          *  Only primary process handles async device events.
1070          **/
1071         mlx5_flow_counters_mng_close(sh);
1072         if (sh->aso_age_mng) {
1073                 mlx5_flow_aso_age_mng_close(sh);
1074                 sh->aso_age_mng = NULL;
1075         }
1076         mlx5_flow_ipool_destroy(sh);
1077         mlx5_os_dev_shared_handler_uninstall(sh);
1078         if (sh->cnt_id_tbl) {
1079                 mlx5_l3t_destroy(sh->cnt_id_tbl);
1080                 sh->cnt_id_tbl = NULL;
1081         }
1082         if (sh->tx_uar) {
1083                 mlx5_glue->devx_free_uar(sh->tx_uar);
1084                 sh->tx_uar = NULL;
1085         }
1086         if (sh->pd)
1087                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
1088         if (sh->tis)
1089                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1090         if (sh->td)
1091                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1092         if (sh->devx_rx_uar)
1093                 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1094         if (sh->ctx)
1095                 claim_zero(mlx5_glue->close_device(sh->ctx));
1096         pthread_mutex_destroy(&sh->txpp.mutex);
1097         mlx5_free(sh);
1098         return;
1099 exit:
1100         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1101 }
1102
1103 /**
1104  * Destroy table hash list.
1105  *
1106  * @param[in] priv
1107  *   Pointer to the private device data structure.
1108  */
1109 void
1110 mlx5_free_table_hash_list(struct mlx5_priv *priv)
1111 {
1112         struct mlx5_dev_ctx_shared *sh = priv->sh;
1113
1114         if (!sh->flow_tbls)
1115                 return;
1116         mlx5_hlist_destroy(sh->flow_tbls);
1117 }
1118
1119 /**
1120  * Initialize flow table hash list and create the root tables entry
1121  * for each domain.
1122  *
1123  * @param[in] priv
1124  *   Pointer to the private device data structure.
1125  *
1126  * @return
1127  *   Zero on success, positive error code otherwise.
1128  */
1129 int
1130 mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused)
1131 {
1132         int err = 0;
1133         /* Tables are only used in DV and DR modes. */
1134 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1135         struct mlx5_dev_ctx_shared *sh = priv->sh;
1136         char s[MLX5_HLIST_NAMESIZE];
1137
1138         MLX5_ASSERT(sh);
1139         snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1140         sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE,
1141                                           0, 0, flow_dv_tbl_create_cb, NULL,
1142                                           flow_dv_tbl_remove_cb);
1143         if (!sh->flow_tbls) {
1144                 DRV_LOG(ERR, "flow tables with hash creation failed.");
1145                 err = ENOMEM;
1146                 return err;
1147         }
1148         sh->flow_tbls->ctx = sh;
1149 #ifndef HAVE_MLX5DV_DR
1150         struct rte_flow_error error;
1151         struct rte_eth_dev *dev = &rte_eth_devices[priv->dev_data->port_id];
1152
1153         /*
1154          * In case we have not DR support, the zero tables should be created
1155          * because DV expect to see them even if they cannot be created by
1156          * RDMA-CORE.
1157          */
1158         if (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0, NULL, 0, 1, &error) ||
1159             !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0, NULL, 0, 1, &error) ||
1160             !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0, NULL, 0, 1, &error)) {
1161                 err = ENOMEM;
1162                 goto error;
1163         }
1164         return err;
1165 error:
1166         mlx5_free_table_hash_list(priv);
1167 #endif /* HAVE_MLX5DV_DR */
1168 #endif
1169         return err;
1170 }
1171
1172 /**
1173  * Retrieve integer value from environment variable.
1174  *
1175  * @param[in] name
1176  *   Environment variable name.
1177  *
1178  * @return
1179  *   Integer value, 0 if the variable is not set.
1180  */
1181 int
1182 mlx5_getenv_int(const char *name)
1183 {
1184         const char *val = getenv(name);
1185
1186         if (val == NULL)
1187                 return 0;
1188         return atoi(val);
1189 }
1190
1191 /**
1192  * DPDK callback to add udp tunnel port
1193  *
1194  * @param[in] dev
1195  *   A pointer to eth_dev
1196  * @param[in] udp_tunnel
1197  *   A pointer to udp tunnel
1198  *
1199  * @return
1200  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1201  */
1202 int
1203 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1204                          struct rte_eth_udp_tunnel *udp_tunnel)
1205 {
1206         MLX5_ASSERT(udp_tunnel != NULL);
1207         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1208             udp_tunnel->udp_port == 4789)
1209                 return 0;
1210         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1211             udp_tunnel->udp_port == 4790)
1212                 return 0;
1213         return -ENOTSUP;
1214 }
1215
1216 /**
1217  * Initialize process private data structure.
1218  *
1219  * @param dev
1220  *   Pointer to Ethernet device structure.
1221  *
1222  * @return
1223  *   0 on success, a negative errno value otherwise and rte_errno is set.
1224  */
1225 int
1226 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1227 {
1228         struct mlx5_priv *priv = dev->data->dev_private;
1229         struct mlx5_proc_priv *ppriv;
1230         size_t ppriv_size;
1231
1232         /*
1233          * UAR register table follows the process private structure. BlueFlame
1234          * registers for Tx queues are stored in the table.
1235          */
1236         ppriv_size =
1237                 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1238         ppriv = mlx5_malloc(MLX5_MEM_RTE, ppriv_size, RTE_CACHE_LINE_SIZE,
1239                             dev->device->numa_node);
1240         if (!ppriv) {
1241                 rte_errno = ENOMEM;
1242                 return -rte_errno;
1243         }
1244         ppriv->uar_table_sz = ppriv_size;
1245         dev->process_private = ppriv;
1246         return 0;
1247 }
1248
1249 /**
1250  * Un-initialize process private data structure.
1251  *
1252  * @param dev
1253  *   Pointer to Ethernet device structure.
1254  */
1255 static void
1256 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1257 {
1258         if (!dev->process_private)
1259                 return;
1260         mlx5_free(dev->process_private);
1261         dev->process_private = NULL;
1262 }
1263
1264 /**
1265  * DPDK callback to close the device.
1266  *
1267  * Destroy all queues and objects, free memory.
1268  *
1269  * @param dev
1270  *   Pointer to Ethernet device structure.
1271  */
1272 int
1273 mlx5_dev_close(struct rte_eth_dev *dev)
1274 {
1275         struct mlx5_priv *priv = dev->data->dev_private;
1276         unsigned int i;
1277         int ret;
1278
1279         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1280                 /* Check if process_private released. */
1281                 if (!dev->process_private)
1282                         return 0;
1283                 mlx5_tx_uar_uninit_secondary(dev);
1284                 mlx5_proc_priv_uninit(dev);
1285                 rte_eth_dev_release_port(dev);
1286                 return 0;
1287         }
1288         if (!priv->sh)
1289                 return 0;
1290         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1291                 dev->data->port_id,
1292                 ((priv->sh->ctx != NULL) ?
1293                 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1294         /*
1295          * If default mreg copy action is removed at the stop stage,
1296          * the search will return none and nothing will be done anymore.
1297          */
1298         mlx5_flow_stop_default(dev);
1299         mlx5_traffic_disable(dev);
1300         /*
1301          * If all the flows are already flushed in the device stop stage,
1302          * then this will return directly without any action.
1303          */
1304         mlx5_flow_list_flush(dev, &priv->flows, true);
1305         mlx5_shared_action_flush(dev);
1306         mlx5_flow_meter_flush(dev, NULL);
1307         /* Prevent crashes when queues are still in use. */
1308         dev->rx_pkt_burst = removed_rx_burst;
1309         dev->tx_pkt_burst = removed_tx_burst;
1310         rte_wmb();
1311         /* Disable datapath on secondary process. */
1312         mlx5_mp_os_req_stop_rxtx(dev);
1313         /* Free the eCPRI flex parser resource. */
1314         mlx5_flex_parser_ecpri_release(dev);
1315         if (priv->rxqs != NULL) {
1316                 /* XXX race condition if mlx5_rx_burst() is still running. */
1317                 usleep(1000);
1318                 for (i = 0; (i != priv->rxqs_n); ++i)
1319                         mlx5_rxq_release(dev, i);
1320                 priv->rxqs_n = 0;
1321                 priv->rxqs = NULL;
1322         }
1323         if (priv->txqs != NULL) {
1324                 /* XXX race condition if mlx5_tx_burst() is still running. */
1325                 usleep(1000);
1326                 for (i = 0; (i != priv->txqs_n); ++i)
1327                         mlx5_txq_release(dev, i);
1328                 priv->txqs_n = 0;
1329                 priv->txqs = NULL;
1330         }
1331         mlx5_proc_priv_uninit(dev);
1332         if (priv->drop_queue.hrxq)
1333                 mlx5_drop_action_destroy(dev);
1334         if (priv->mreg_cp_tbl)
1335                 mlx5_hlist_destroy(priv->mreg_cp_tbl);
1336         mlx5_mprq_free_mp(dev);
1337         mlx5_os_free_shared_dr(priv);
1338         if (priv->rss_conf.rss_key != NULL)
1339                 mlx5_free(priv->rss_conf.rss_key);
1340         if (priv->reta_idx != NULL)
1341                 mlx5_free(priv->reta_idx);
1342         if (priv->config.vf)
1343                 mlx5_os_mac_addr_flush(dev);
1344         if (priv->nl_socket_route >= 0)
1345                 close(priv->nl_socket_route);
1346         if (priv->nl_socket_rdma >= 0)
1347                 close(priv->nl_socket_rdma);
1348         if (priv->vmwa_context)
1349                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1350         ret = mlx5_hrxq_verify(dev);
1351         if (ret)
1352                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1353                         dev->data->port_id);
1354         ret = mlx5_ind_table_obj_verify(dev);
1355         if (ret)
1356                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1357                         dev->data->port_id);
1358         ret = mlx5_rxq_obj_verify(dev);
1359         if (ret)
1360                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1361                         dev->data->port_id);
1362         ret = mlx5_rxq_verify(dev);
1363         if (ret)
1364                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1365                         dev->data->port_id);
1366         ret = mlx5_txq_obj_verify(dev);
1367         if (ret)
1368                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1369                         dev->data->port_id);
1370         ret = mlx5_txq_verify(dev);
1371         if (ret)
1372                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1373                         dev->data->port_id);
1374         ret = mlx5_flow_verify(dev);
1375         if (ret)
1376                 DRV_LOG(WARNING, "port %u some flows still remain",
1377                         dev->data->port_id);
1378         mlx5_cache_list_destroy(&priv->hrxqs);
1379         /*
1380          * Free the shared context in last turn, because the cleanup
1381          * routines above may use some shared fields, like
1382          * mlx5_os_mac_addr_flush() uses ibdev_path for retrieveing
1383          * ifindex if Netlink fails.
1384          */
1385         mlx5_free_shared_dev_ctx(priv->sh);
1386         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1387                 unsigned int c = 0;
1388                 uint16_t port_id;
1389
1390                 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1391                         struct mlx5_priv *opriv =
1392                                 rte_eth_devices[port_id].data->dev_private;
1393
1394                         if (!opriv ||
1395                             opriv->domain_id != priv->domain_id ||
1396                             &rte_eth_devices[port_id] == dev)
1397                                 continue;
1398                         ++c;
1399                         break;
1400                 }
1401                 if (!c)
1402                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1403         }
1404         memset(priv, 0, sizeof(*priv));
1405         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1406         /*
1407          * Reset mac_addrs to NULL such that it is not freed as part of
1408          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1409          * it is freed when dev_private is freed.
1410          */
1411         dev->data->mac_addrs = NULL;
1412         return 0;
1413 }
1414
1415 /**
1416  * Verify and store value for device argument.
1417  *
1418  * @param[in] key
1419  *   Key argument to verify.
1420  * @param[in] val
1421  *   Value associated with key.
1422  * @param opaque
1423  *   User data.
1424  *
1425  * @return
1426  *   0 on success, a negative errno value otherwise and rte_errno is set.
1427  */
1428 static int
1429 mlx5_args_check(const char *key, const char *val, void *opaque)
1430 {
1431         struct mlx5_dev_config *config = opaque;
1432         unsigned long mod;
1433         signed long tmp;
1434
1435         /* No-op, port representors are processed in mlx5_dev_spawn(). */
1436         if (!strcmp(MLX5_REPRESENTOR, key))
1437                 return 0;
1438         errno = 0;
1439         tmp = strtol(val, NULL, 0);
1440         if (errno) {
1441                 rte_errno = errno;
1442                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1443                 return -rte_errno;
1444         }
1445         if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1446                 /* Negative values are acceptable for some keys only. */
1447                 rte_errno = EINVAL;
1448                 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1449                 return -rte_errno;
1450         }
1451         mod = tmp >= 0 ? tmp : -tmp;
1452         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1453                 if (tmp > MLX5_CQE_RESP_FORMAT_L34H_STRIDX) {
1454                         DRV_LOG(ERR, "invalid CQE compression "
1455                                      "format parameter");
1456                         rte_errno = EINVAL;
1457                         return -rte_errno;
1458                 }
1459                 config->cqe_comp = !!tmp;
1460                 config->cqe_comp_fmt = tmp;
1461         } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1462                 config->cqe_pad = !!tmp;
1463         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1464                 config->hw_padding = !!tmp;
1465         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1466                 config->mprq.enabled = !!tmp;
1467         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1468                 config->mprq.stride_num_n = tmp;
1469         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1470                 config->mprq.stride_size_n = tmp;
1471         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1472                 config->mprq.max_memcpy_len = tmp;
1473         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1474                 config->mprq.min_rxqs_num = tmp;
1475         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1476                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1477                                  " converted to txq_inline_max", key);
1478                 config->txq_inline_max = tmp;
1479         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1480                 config->txq_inline_max = tmp;
1481         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1482                 config->txq_inline_min = tmp;
1483         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1484                 config->txq_inline_mpw = tmp;
1485         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1486                 config->txqs_inline = tmp;
1487         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1488                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1489         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1490                 config->mps = !!tmp;
1491         } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1492                 if (tmp != MLX5_TXDB_CACHED &&
1493                     tmp != MLX5_TXDB_NCACHED &&
1494                     tmp != MLX5_TXDB_HEURISTIC) {
1495                         DRV_LOG(ERR, "invalid Tx doorbell "
1496                                      "mapping parameter");
1497                         rte_errno = EINVAL;
1498                         return -rte_errno;
1499                 }
1500                 config->dbnc = tmp;
1501         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1502                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1503         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1504                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1505                                  " converted to txq_inline_mpw", key);
1506                 config->txq_inline_mpw = tmp;
1507         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1508                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1509         } else if (strcmp(MLX5_TX_PP, key) == 0) {
1510                 if (!mod) {
1511                         DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1512                         rte_errno = EINVAL;
1513                         return -rte_errno;
1514                 }
1515                 config->tx_pp = tmp;
1516         } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1517                 config->tx_skew = tmp;
1518         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1519                 config->rx_vec_en = !!tmp;
1520         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1521                 config->l3_vxlan_en = !!tmp;
1522         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1523                 config->vf_nl_en = !!tmp;
1524         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1525                 config->dv_esw_en = !!tmp;
1526         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1527                 config->dv_flow_en = !!tmp;
1528         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1529                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1530                     tmp != MLX5_XMETA_MODE_META16 &&
1531                     tmp != MLX5_XMETA_MODE_META32 &&
1532                     tmp != MLX5_XMETA_MODE_MISS_INFO) {
1533                         DRV_LOG(ERR, "invalid extensive "
1534                                      "metadata parameter");
1535                         rte_errno = EINVAL;
1536                         return -rte_errno;
1537                 }
1538                 if (tmp != MLX5_XMETA_MODE_MISS_INFO)
1539                         config->dv_xmeta_en = tmp;
1540                 else
1541                         config->dv_miss_info = 1;
1542         } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1543                 config->lacp_by_user = !!tmp;
1544         } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1545                 config->mr_ext_memseg_en = !!tmp;
1546         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1547                 config->max_dump_files_num = tmp;
1548         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1549                 config->lro.timeout = tmp;
1550         } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1551                 DRV_LOG(DEBUG, "class argument is %s.", val);
1552         } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1553                 config->log_hp_size = tmp;
1554         } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1555                 if (tmp != MLX5_RCM_NONE &&
1556                     tmp != MLX5_RCM_LIGHT &&
1557                     tmp != MLX5_RCM_AGGR) {
1558                         DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1559                         rte_errno = EINVAL;
1560                         return -rte_errno;
1561                 }
1562                 config->reclaim_mode = tmp;
1563         } else if (strcmp(MLX5_SYS_MEM_EN, key) == 0) {
1564                 config->sys_mem_en = !!tmp;
1565         } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
1566                 config->decap_en = !!tmp;
1567         } else {
1568                 DRV_LOG(WARNING, "%s: unknown parameter", key);
1569                 rte_errno = EINVAL;
1570                 return -rte_errno;
1571         }
1572         return 0;
1573 }
1574
1575 /**
1576  * Parse device parameters.
1577  *
1578  * @param config
1579  *   Pointer to device configuration structure.
1580  * @param devargs
1581  *   Device arguments structure.
1582  *
1583  * @return
1584  *   0 on success, a negative errno value otherwise and rte_errno is set.
1585  */
1586 int
1587 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1588 {
1589         const char **params = (const char *[]){
1590                 MLX5_RXQ_CQE_COMP_EN,
1591                 MLX5_RXQ_CQE_PAD_EN,
1592                 MLX5_RXQ_PKT_PAD_EN,
1593                 MLX5_RX_MPRQ_EN,
1594                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1595                 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1596                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1597                 MLX5_RXQS_MIN_MPRQ,
1598                 MLX5_TXQ_INLINE,
1599                 MLX5_TXQ_INLINE_MIN,
1600                 MLX5_TXQ_INLINE_MAX,
1601                 MLX5_TXQ_INLINE_MPW,
1602                 MLX5_TXQS_MIN_INLINE,
1603                 MLX5_TXQS_MAX_VEC,
1604                 MLX5_TXQ_MPW_EN,
1605                 MLX5_TXQ_MPW_HDR_DSEG_EN,
1606                 MLX5_TXQ_MAX_INLINE_LEN,
1607                 MLX5_TX_DB_NC,
1608                 MLX5_TX_PP,
1609                 MLX5_TX_SKEW,
1610                 MLX5_TX_VEC_EN,
1611                 MLX5_RX_VEC_EN,
1612                 MLX5_L3_VXLAN_EN,
1613                 MLX5_VF_NL_EN,
1614                 MLX5_DV_ESW_EN,
1615                 MLX5_DV_FLOW_EN,
1616                 MLX5_DV_XMETA_EN,
1617                 MLX5_LACP_BY_USER,
1618                 MLX5_MR_EXT_MEMSEG_EN,
1619                 MLX5_REPRESENTOR,
1620                 MLX5_MAX_DUMP_FILES_NUM,
1621                 MLX5_LRO_TIMEOUT_USEC,
1622                 MLX5_CLASS_ARG_NAME,
1623                 MLX5_HP_BUF_SIZE,
1624                 MLX5_RECLAIM_MEM,
1625                 MLX5_SYS_MEM_EN,
1626                 MLX5_DECAP_EN,
1627                 NULL,
1628         };
1629         struct rte_kvargs *kvlist;
1630         int ret = 0;
1631         int i;
1632
1633         if (devargs == NULL)
1634                 return 0;
1635         /* Following UGLY cast is done to pass checkpatch. */
1636         kvlist = rte_kvargs_parse(devargs->args, params);
1637         if (kvlist == NULL) {
1638                 rte_errno = EINVAL;
1639                 return -rte_errno;
1640         }
1641         /* Process parameters. */
1642         for (i = 0; (params[i] != NULL); ++i) {
1643                 if (rte_kvargs_count(kvlist, params[i])) {
1644                         ret = rte_kvargs_process(kvlist, params[i],
1645                                                  mlx5_args_check, config);
1646                         if (ret) {
1647                                 rte_errno = EINVAL;
1648                                 rte_kvargs_free(kvlist);
1649                                 return -rte_errno;
1650                         }
1651                 }
1652         }
1653         rte_kvargs_free(kvlist);
1654         return 0;
1655 }
1656
1657 /**
1658  * Configures the minimal amount of data to inline into WQE
1659  * while sending packets.
1660  *
1661  * - the txq_inline_min has the maximal priority, if this
1662  *   key is specified in devargs
1663  * - if DevX is enabled the inline mode is queried from the
1664  *   device (HCA attributes and NIC vport context if needed).
1665  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1666  *   and none (0 bytes) for other NICs
1667  *
1668  * @param spawn
1669  *   Verbs device parameters (name, port, switch_info) to spawn.
1670  * @param config
1671  *   Device configuration parameters.
1672  */
1673 void
1674 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1675                     struct mlx5_dev_config *config)
1676 {
1677         if (config->txq_inline_min != MLX5_ARG_UNSET) {
1678                 /* Application defines size of inlined data explicitly. */
1679                 switch (spawn->pci_dev->id.device_id) {
1680                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1681                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1682                         if (config->txq_inline_min <
1683                                        (int)MLX5_INLINE_HSIZE_L2) {
1684                                 DRV_LOG(DEBUG,
1685                                         "txq_inline_mix aligned to minimal"
1686                                         " ConnectX-4 required value %d",
1687                                         (int)MLX5_INLINE_HSIZE_L2);
1688                                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1689                         }
1690                         break;
1691                 }
1692                 goto exit;
1693         }
1694         if (config->hca_attr.eth_net_offloads) {
1695                 /* We have DevX enabled, inline mode queried successfully. */
1696                 switch (config->hca_attr.wqe_inline_mode) {
1697                 case MLX5_CAP_INLINE_MODE_L2:
1698                         /* outer L2 header must be inlined. */
1699                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1700                         goto exit;
1701                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1702                         /* No inline data are required by NIC. */
1703                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1704                         config->hw_vlan_insert =
1705                                 config->hca_attr.wqe_vlan_insert;
1706                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1707                         goto exit;
1708                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1709                         /* inline mode is defined by NIC vport context. */
1710                         if (!config->hca_attr.eth_virt)
1711                                 break;
1712                         switch (config->hca_attr.vport_inline_mode) {
1713                         case MLX5_INLINE_MODE_NONE:
1714                                 config->txq_inline_min =
1715                                         MLX5_INLINE_HSIZE_NONE;
1716                                 goto exit;
1717                         case MLX5_INLINE_MODE_L2:
1718                                 config->txq_inline_min =
1719                                         MLX5_INLINE_HSIZE_L2;
1720                                 goto exit;
1721                         case MLX5_INLINE_MODE_IP:
1722                                 config->txq_inline_min =
1723                                         MLX5_INLINE_HSIZE_L3;
1724                                 goto exit;
1725                         case MLX5_INLINE_MODE_TCP_UDP:
1726                                 config->txq_inline_min =
1727                                         MLX5_INLINE_HSIZE_L4;
1728                                 goto exit;
1729                         case MLX5_INLINE_MODE_INNER_L2:
1730                                 config->txq_inline_min =
1731                                         MLX5_INLINE_HSIZE_INNER_L2;
1732                                 goto exit;
1733                         case MLX5_INLINE_MODE_INNER_IP:
1734                                 config->txq_inline_min =
1735                                         MLX5_INLINE_HSIZE_INNER_L3;
1736                                 goto exit;
1737                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
1738                                 config->txq_inline_min =
1739                                         MLX5_INLINE_HSIZE_INNER_L4;
1740                                 goto exit;
1741                         }
1742                 }
1743         }
1744         /*
1745          * We get here if we are unable to deduce
1746          * inline data size with DevX. Try PCI ID
1747          * to determine old NICs.
1748          */
1749         switch (spawn->pci_dev->id.device_id) {
1750         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1751         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1752         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1753         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1754                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1755                 config->hw_vlan_insert = 0;
1756                 break;
1757         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1758         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1759         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1760         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1761                 /*
1762                  * These NICs support VLAN insertion from WQE and
1763                  * report the wqe_vlan_insert flag. But there is the bug
1764                  * and PFC control may be broken, so disable feature.
1765                  */
1766                 config->hw_vlan_insert = 0;
1767                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1768                 break;
1769         default:
1770                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1771                 break;
1772         }
1773 exit:
1774         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1775 }
1776
1777 /**
1778  * Configures the metadata mask fields in the shared context.
1779  *
1780  * @param [in] dev
1781  *   Pointer to Ethernet device.
1782  */
1783 void
1784 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1785 {
1786         struct mlx5_priv *priv = dev->data->dev_private;
1787         struct mlx5_dev_ctx_shared *sh = priv->sh;
1788         uint32_t meta, mark, reg_c0;
1789
1790         reg_c0 = ~priv->vport_meta_mask;
1791         switch (priv->config.dv_xmeta_en) {
1792         case MLX5_XMETA_MODE_LEGACY:
1793                 meta = UINT32_MAX;
1794                 mark = MLX5_FLOW_MARK_MASK;
1795                 break;
1796         case MLX5_XMETA_MODE_META16:
1797                 meta = reg_c0 >> rte_bsf32(reg_c0);
1798                 mark = MLX5_FLOW_MARK_MASK;
1799                 break;
1800         case MLX5_XMETA_MODE_META32:
1801                 meta = UINT32_MAX;
1802                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1803                 break;
1804         default:
1805                 meta = 0;
1806                 mark = 0;
1807                 MLX5_ASSERT(false);
1808                 break;
1809         }
1810         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
1811                 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
1812                                  sh->dv_mark_mask, mark);
1813         else
1814                 sh->dv_mark_mask = mark;
1815         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
1816                 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
1817                                  sh->dv_meta_mask, meta);
1818         else
1819                 sh->dv_meta_mask = meta;
1820         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
1821                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
1822                                  sh->dv_meta_mask, reg_c0);
1823         else
1824                 sh->dv_regc0_mask = reg_c0;
1825         DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
1826         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
1827         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
1828         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
1829 }
1830
1831 int
1832 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
1833 {
1834         static const char *const dynf_names[] = {
1835                 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
1836                 RTE_MBUF_DYNFLAG_METADATA_NAME,
1837                 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
1838         };
1839         unsigned int i;
1840
1841         if (n < RTE_DIM(dynf_names))
1842                 return -ENOMEM;
1843         for (i = 0; i < RTE_DIM(dynf_names); i++) {
1844                 if (names[i] == NULL)
1845                         return -EINVAL;
1846                 strcpy(names[i], dynf_names[i]);
1847         }
1848         return RTE_DIM(dynf_names);
1849 }
1850
1851 /**
1852  * Comparison callback to sort device data.
1853  *
1854  * This is meant to be used with qsort().
1855  *
1856  * @param a[in]
1857  *   Pointer to pointer to first data object.
1858  * @param b[in]
1859  *   Pointer to pointer to second data object.
1860  *
1861  * @return
1862  *   0 if both objects are equal, less than 0 if the first argument is less
1863  *   than the second, greater than 0 otherwise.
1864  */
1865 int
1866 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
1867                               struct mlx5_dev_config *config)
1868 {
1869         struct mlx5_dev_ctx_shared *sh = priv->sh;
1870         struct mlx5_dev_config *sh_conf = NULL;
1871         uint16_t port_id;
1872
1873         MLX5_ASSERT(sh);
1874         /* Nothing to compare for the single/first device. */
1875         if (sh->refcnt == 1)
1876                 return 0;
1877         /* Find the device with shared context. */
1878         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1879                 struct mlx5_priv *opriv =
1880                         rte_eth_devices[port_id].data->dev_private;
1881
1882                 if (opriv && opriv != priv && opriv->sh == sh) {
1883                         sh_conf = &opriv->config;
1884                         break;
1885                 }
1886         }
1887         if (!sh_conf)
1888                 return 0;
1889         if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
1890                 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
1891                              " for shared %s context", sh->ibdev_name);
1892                 rte_errno = EINVAL;
1893                 return rte_errno;
1894         }
1895         if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
1896                 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
1897                              " for shared %s context", sh->ibdev_name);
1898                 rte_errno = EINVAL;
1899                 return rte_errno;
1900         }
1901         return 0;
1902 }
1903
1904 /**
1905  * Look for the ethernet device belonging to mlx5 driver.
1906  *
1907  * @param[in] port_id
1908  *   port_id to start looking for device.
1909  * @param[in] pci_dev
1910  *   Pointer to the hint PCI device. When device is being probed
1911  *   the its siblings (master and preceding representors might
1912  *   not have assigned driver yet (because the mlx5_os_pci_probe()
1913  *   is not completed yet, for this case match on hint PCI
1914  *   device may be used to detect sibling device.
1915  *
1916  * @return
1917  *   port_id of found device, RTE_MAX_ETHPORT if not found.
1918  */
1919 uint16_t
1920 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
1921 {
1922         while (port_id < RTE_MAX_ETHPORTS) {
1923                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
1924
1925                 if (dev->state != RTE_ETH_DEV_UNUSED &&
1926                     dev->device &&
1927                     (dev->device == &pci_dev->device ||
1928                      (dev->device->driver &&
1929                      dev->device->driver->name &&
1930                      !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
1931                         break;
1932                 port_id++;
1933         }
1934         if (port_id >= RTE_MAX_ETHPORTS)
1935                 return RTE_MAX_ETHPORTS;
1936         return port_id;
1937 }
1938
1939 /**
1940  * DPDK callback to remove a PCI device.
1941  *
1942  * This function removes all Ethernet devices belong to a given PCI device.
1943  *
1944  * @param[in] pci_dev
1945  *   Pointer to the PCI device.
1946  *
1947  * @return
1948  *   0 on success, the function cannot fail.
1949  */
1950 static int
1951 mlx5_pci_remove(struct rte_pci_device *pci_dev)
1952 {
1953         uint16_t port_id;
1954         int ret = 0;
1955
1956         RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
1957                 /*
1958                  * mlx5_dev_close() is not registered to secondary process,
1959                  * call the close function explicitly for secondary process.
1960                  */
1961                 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
1962                         ret |= mlx5_dev_close(&rte_eth_devices[port_id]);
1963                 else
1964                         ret |= rte_eth_dev_close(port_id);
1965         }
1966         return ret == 0 ? 0 : -EIO;
1967 }
1968
1969 static const struct rte_pci_id mlx5_pci_id_map[] = {
1970         {
1971                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1972                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1973         },
1974         {
1975                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1976                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1977         },
1978         {
1979                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1980                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1981         },
1982         {
1983                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1984                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
1985         },
1986         {
1987                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1988                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
1989         },
1990         {
1991                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1992                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
1993         },
1994         {
1995                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1996                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
1997         },
1998         {
1999                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2000                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2001         },
2002         {
2003                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2004                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2005         },
2006         {
2007                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2008                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2009         },
2010         {
2011                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2012                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2013         },
2014         {
2015                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2016                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2017         },
2018         {
2019                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2020                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2021         },
2022         {
2023                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2024                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
2025         },
2026         {
2027                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2028                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2029         },
2030         {
2031                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2032                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2033         },
2034         {
2035                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2036                                 PCI_DEVICE_ID_MELLANOX_CONNECTX7)
2037         },
2038         {
2039                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2040                                 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF)
2041         },
2042         {
2043                 .vendor_id = 0
2044         }
2045 };
2046
2047 static struct mlx5_pci_driver mlx5_driver = {
2048         .driver_class = MLX5_CLASS_NET,
2049         .pci_driver = {
2050                 .driver = {
2051                         .name = MLX5_DRIVER_NAME,
2052                 },
2053                 .id_table = mlx5_pci_id_map,
2054                 .probe = mlx5_os_pci_probe,
2055                 .remove = mlx5_pci_remove,
2056                 .dma_map = mlx5_dma_map,
2057                 .dma_unmap = mlx5_dma_unmap,
2058                 .drv_flags = PCI_DRV_FLAGS,
2059         },
2060 };
2061
2062 /* Initialize driver log type. */
2063 RTE_LOG_REGISTER(mlx5_logtype, pmd.net.mlx5, NOTICE)
2064
2065 /**
2066  * Driver initialization routine.
2067  */
2068 RTE_INIT(rte_mlx5_pmd_init)
2069 {
2070         mlx5_common_init();
2071         /* Build the static tables for Verbs conversion. */
2072         mlx5_set_ptype_table();
2073         mlx5_set_cksum_table();
2074         mlx5_set_swp_types_table();
2075         if (mlx5_glue)
2076                 mlx5_pci_driver_register(&mlx5_driver);
2077 }
2078
2079 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2080 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2081 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");