1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
13 #include <rte_malloc.h>
14 #include <ethdev_driver.h>
16 #include <rte_bus_pci.h>
17 #include <rte_common.h>
18 #include <rte_kvargs.h>
19 #include <rte_rwlock.h>
20 #include <rte_spinlock.h>
21 #include <rte_string_fns.h>
22 #include <rte_alarm.h>
23 #include <rte_cycles.h>
25 #include <mlx5_glue.h>
26 #include <mlx5_devx_cmds.h>
27 #include <mlx5_common.h>
28 #include <mlx5_common_os.h>
29 #include <mlx5_common_mp.h>
30 #include <mlx5_malloc.h>
32 #include "mlx5_defs.h"
34 #include "mlx5_utils.h"
35 #include "mlx5_rxtx.h"
38 #include "mlx5_autoconf.h"
40 #include "mlx5_flow.h"
41 #include "mlx5_flow_os.h"
42 #include "rte_pmd_mlx5.h"
44 #define MLX5_ETH_DRIVER_NAME mlx5_eth
46 /* Driver type key for new device global syntax. */
47 #define MLX5_DRIVER_KEY "driver"
49 /* Device parameter to enable RX completion queue compression. */
50 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
52 /* Device parameter to enable padding Rx packet to cacheline size. */
53 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
55 /* Device parameter to enable Multi-Packet Rx queue. */
56 #define MLX5_RX_MPRQ_EN "mprq_en"
58 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
59 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
61 /* Device parameter to configure log 2 of the stride size for MPRQ. */
62 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
64 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
65 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
67 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
68 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
70 /* Device parameter to configure inline send. Deprecated, ignored.*/
71 #define MLX5_TXQ_INLINE "txq_inline"
73 /* Device parameter to limit packet size to inline with ordinary SEND. */
74 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
76 /* Device parameter to configure minimal data size to inline. */
77 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
79 /* Device parameter to limit packet size to inline with Enhanced MPW. */
80 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
83 * Device parameter to configure the number of TX queues threshold for
84 * enabling inline send.
86 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
89 * Device parameter to configure the number of TX queues threshold for
90 * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
92 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
94 /* Device parameter to enable multi-packet send WQEs. */
95 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
98 * Device parameter to force doorbell register mapping
99 * to non-cahed region eliminating the extra write memory barrier.
101 #define MLX5_TX_DB_NC "tx_db_nc"
104 * Device parameter to include 2 dsegs in the title WQEBB.
105 * Deprecated, ignored.
107 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
110 * Device parameter to limit the size of inlining packet.
111 * Deprecated, ignored.
113 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
116 * Device parameter to enable Tx scheduling on timestamps
117 * and specify the packet pacing granularity in nanoseconds.
119 #define MLX5_TX_PP "tx_pp"
122 * Device parameter to specify skew in nanoseconds on Tx datapath,
123 * it represents the time between SQ start WQE processing and
124 * appearing actual packet data on the wire.
126 #define MLX5_TX_SKEW "tx_skew"
129 * Device parameter to enable hardware Tx vector.
130 * Deprecated, ignored (no vectorized Tx routines anymore).
132 #define MLX5_TX_VEC_EN "tx_vec_en"
134 /* Device parameter to enable hardware Rx vector. */
135 #define MLX5_RX_VEC_EN "rx_vec_en"
137 /* Allow L3 VXLAN flow creation. */
138 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
140 /* Activate DV E-Switch flow steering. */
141 #define MLX5_DV_ESW_EN "dv_esw_en"
143 /* Activate DV flow steering. */
144 #define MLX5_DV_FLOW_EN "dv_flow_en"
146 /* Enable extensive flow metadata support. */
147 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
149 /* Device parameter to let the user manage the lacp traffic of bonded device */
150 #define MLX5_LACP_BY_USER "lacp_by_user"
152 /* Activate Netlink support in VF mode. */
153 #define MLX5_VF_NL_EN "vf_nl_en"
155 /* Enable extending memsegs when creating a MR. */
156 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
158 /* Select port representors to instantiate. */
159 #define MLX5_REPRESENTOR "representor"
161 /* Device parameter to configure the maximum number of dump files per queue. */
162 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
164 /* Configure timeout of LRO session (in microseconds). */
165 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
168 * Device parameter to configure the total data buffer size for a single
169 * hairpin queue (logarithm value).
171 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
173 /* Flow memory reclaim mode. */
174 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
176 /* The default memory allocator used in PMD. */
177 #define MLX5_SYS_MEM_EN "sys_mem_en"
178 /* Decap will be used or not. */
179 #define MLX5_DECAP_EN "decap_en"
181 /* Device parameter to configure allow or prevent duplicate rules pattern. */
182 #define MLX5_ALLOW_DUPLICATE_PATTERN "allow_duplicate_pattern"
184 /* Device parameter to configure implicit registration of mempool memory. */
185 #define MLX5_MR_MEMPOOL_REG_EN "mr_mempool_reg_en"
187 /* Shared memory between primary and secondary processes. */
188 struct mlx5_shared_data *mlx5_shared_data;
190 /** Driver-specific log messages type. */
193 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
194 LIST_HEAD_INITIALIZER();
195 static pthread_mutex_t mlx5_dev_ctx_list_mutex;
196 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
197 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
198 [MLX5_IPOOL_DECAP_ENCAP] = {
199 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
205 .malloc = mlx5_malloc,
207 .type = "mlx5_encap_decap_ipool",
209 [MLX5_IPOOL_PUSH_VLAN] = {
210 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
216 .malloc = mlx5_malloc,
218 .type = "mlx5_push_vlan_ipool",
221 .size = sizeof(struct mlx5_flow_dv_tag_resource),
227 .per_core_cache = (1 << 16),
228 .malloc = mlx5_malloc,
230 .type = "mlx5_tag_ipool",
232 [MLX5_IPOOL_PORT_ID] = {
233 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
239 .malloc = mlx5_malloc,
241 .type = "mlx5_port_id_ipool",
243 [MLX5_IPOOL_JUMP] = {
244 .size = sizeof(struct mlx5_flow_tbl_data_entry),
250 .malloc = mlx5_malloc,
252 .type = "mlx5_jump_ipool",
254 [MLX5_IPOOL_SAMPLE] = {
255 .size = sizeof(struct mlx5_flow_dv_sample_resource),
261 .malloc = mlx5_malloc,
263 .type = "mlx5_sample_ipool",
265 [MLX5_IPOOL_DEST_ARRAY] = {
266 .size = sizeof(struct mlx5_flow_dv_dest_array_resource),
272 .malloc = mlx5_malloc,
274 .type = "mlx5_dest_array_ipool",
276 [MLX5_IPOOL_TUNNEL_ID] = {
277 .size = sizeof(struct mlx5_flow_tunnel),
278 .trunk_size = MLX5_MAX_TUNNELS,
281 .type = "mlx5_tunnel_offload",
283 [MLX5_IPOOL_TNL_TBL_ID] = {
286 .type = "mlx5_flow_tnl_tbl_ipool",
291 * The ipool index should grow continually from small to big,
292 * for meter idx, so not set grow_trunk to avoid meter index
293 * not jump continually.
295 .size = sizeof(struct mlx5_legacy_flow_meter),
299 .malloc = mlx5_malloc,
301 .type = "mlx5_meter_ipool",
304 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
310 .malloc = mlx5_malloc,
312 .type = "mlx5_mcp_ipool",
314 [MLX5_IPOOL_HRXQ] = {
315 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
321 .malloc = mlx5_malloc,
323 .type = "mlx5_hrxq_ipool",
325 [MLX5_IPOOL_MLX5_FLOW] = {
327 * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
328 * It set in run time according to PCI function configuration.
336 .per_core_cache = 1 << 19,
337 .malloc = mlx5_malloc,
339 .type = "mlx5_flow_handle_ipool",
341 [MLX5_IPOOL_RTE_FLOW] = {
342 .size = sizeof(struct rte_flow),
346 .malloc = mlx5_malloc,
348 .type = "rte_flow_ipool",
350 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID] = {
353 .type = "mlx5_flow_rss_id_ipool",
355 [MLX5_IPOOL_RSS_SHARED_ACTIONS] = {
356 .size = sizeof(struct mlx5_shared_action_rss),
362 .malloc = mlx5_malloc,
364 .type = "mlx5_shared_action_rss",
366 [MLX5_IPOOL_MTR_POLICY] = {
368 * The ipool index should grow continually from small to big,
369 * for policy idx, so not set grow_trunk to avoid policy index
370 * not jump continually.
372 .size = sizeof(struct mlx5_flow_meter_sub_policy),
376 .malloc = mlx5_malloc,
378 .type = "mlx5_meter_policy_ipool",
383 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
384 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
386 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 1024
389 * Decide whether representor ID is a HPF(host PF) port on BF2.
392 * Pointer to Ethernet device structure.
395 * Non-zero if HPF, otherwise 0.
398 mlx5_is_hpf(struct rte_eth_dev *dev)
400 struct mlx5_priv *priv = dev->data->dev_private;
401 uint16_t repr = MLX5_REPRESENTOR_REPR(priv->representor_id);
402 int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
404 return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_VF &&
405 MLX5_REPRESENTOR_REPR(-1) == repr;
409 * Decide whether representor ID is a SF port representor.
412 * Pointer to Ethernet device structure.
415 * Non-zero if HPF, otherwise 0.
418 mlx5_is_sf_repr(struct rte_eth_dev *dev)
420 struct mlx5_priv *priv = dev->data->dev_private;
421 int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
423 return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_SF;
427 * Initialize the ASO aging management structure.
430 * Pointer to mlx5_dev_ctx_shared object to free
433 * 0 on success, a negative errno value otherwise and rte_errno is set.
436 mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh)
442 sh->aso_age_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->aso_age_mng),
443 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
444 if (!sh->aso_age_mng) {
445 DRV_LOG(ERR, "aso_age_mng allocation was failed.");
449 err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_FLOW_HIT);
451 mlx5_free(sh->aso_age_mng);
454 rte_spinlock_init(&sh->aso_age_mng->resize_sl);
455 rte_spinlock_init(&sh->aso_age_mng->free_sl);
456 LIST_INIT(&sh->aso_age_mng->free);
461 * Close and release all the resources of the ASO aging management structure.
464 * Pointer to mlx5_dev_ctx_shared object to free.
467 mlx5_flow_aso_age_mng_close(struct mlx5_dev_ctx_shared *sh)
471 mlx5_aso_flow_hit_queue_poll_stop(sh);
472 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_FLOW_HIT);
473 if (sh->aso_age_mng->pools) {
474 struct mlx5_aso_age_pool *pool;
476 for (i = 0; i < sh->aso_age_mng->next; ++i) {
477 pool = sh->aso_age_mng->pools[i];
478 claim_zero(mlx5_devx_cmd_destroy
479 (pool->flow_hit_aso_obj));
480 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j)
481 if (pool->actions[j].dr_action)
483 (mlx5_flow_os_destroy_flow_action
484 (pool->actions[j].dr_action));
487 mlx5_free(sh->aso_age_mng->pools);
489 mlx5_free(sh->aso_age_mng);
493 * Initialize the shared aging list information per port.
496 * Pointer to mlx5_dev_ctx_shared object.
499 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
502 struct mlx5_age_info *age_info;
504 for (i = 0; i < sh->max_port; i++) {
505 age_info = &sh->port[i].age_info;
507 TAILQ_INIT(&age_info->aged_counters);
508 LIST_INIT(&age_info->aged_aso);
509 rte_spinlock_init(&age_info->aged_sl);
510 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
515 * Initialize the counters management structure.
518 * Pointer to mlx5_dev_ctx_shared object to free
521 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
523 struct mlx5_hca_attr *attr = &sh->cdev->config.hca_attr;
526 memset(&sh->cmng, 0, sizeof(sh->cmng));
527 TAILQ_INIT(&sh->cmng.flow_counters);
528 sh->cmng.min_id = MLX5_CNT_BATCH_OFFSET;
529 sh->cmng.max_id = -1;
530 sh->cmng.last_pool_idx = POOL_IDX_INVALID;
531 rte_spinlock_init(&sh->cmng.pool_update_sl);
532 for (i = 0; i < MLX5_COUNTER_TYPE_MAX; i++) {
533 TAILQ_INIT(&sh->cmng.counters[i]);
534 rte_spinlock_init(&sh->cmng.csl[i]);
536 if (sh->devx && !haswell_broadwell_cpu) {
537 sh->cmng.relaxed_ordering_write = attr->relaxed_ordering_write;
538 sh->cmng.relaxed_ordering_read = attr->relaxed_ordering_read;
543 * Destroy all the resources allocated for a counter memory management.
546 * Pointer to the memory management structure.
549 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
551 uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
553 LIST_REMOVE(mng, next);
554 claim_zero(mlx5_devx_cmd_destroy(mng->dm));
555 claim_zero(mlx5_os_umem_dereg(mng->umem));
560 * Close and release all the resources of the counters management.
563 * Pointer to mlx5_dev_ctx_shared object to free.
566 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
568 struct mlx5_counter_stats_mem_mng *mng;
574 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
575 if (rte_errno != EINPROGRESS)
580 if (sh->cmng.pools) {
581 struct mlx5_flow_counter_pool *pool;
582 uint16_t n_valid = sh->cmng.n_valid;
583 bool fallback = sh->cmng.counter_fallback;
585 for (i = 0; i < n_valid; ++i) {
586 pool = sh->cmng.pools[i];
587 if (!fallback && pool->min_dcs)
588 claim_zero(mlx5_devx_cmd_destroy
590 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
591 struct mlx5_flow_counter *cnt =
592 MLX5_POOL_GET_CNT(pool, j);
596 (mlx5_flow_os_destroy_flow_action
598 if (fallback && MLX5_POOL_GET_CNT
599 (pool, j)->dcs_when_free)
600 claim_zero(mlx5_devx_cmd_destroy
601 (cnt->dcs_when_free));
605 mlx5_free(sh->cmng.pools);
607 mng = LIST_FIRST(&sh->cmng.mem_mngs);
609 mlx5_flow_destroy_counter_stat_mem_mng(mng);
610 mng = LIST_FIRST(&sh->cmng.mem_mngs);
612 memset(&sh->cmng, 0, sizeof(sh->cmng));
616 * Initialize the aso flow meters management structure.
619 * Pointer to mlx5_dev_ctx_shared object to free
622 mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh)
625 sh->mtrmng = mlx5_malloc(MLX5_MEM_ZERO,
627 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
630 "meter management allocation was failed.");
634 if (sh->meter_aso_en) {
635 rte_spinlock_init(&sh->mtrmng->pools_mng.mtrsl);
636 LIST_INIT(&sh->mtrmng->pools_mng.meters);
638 sh->mtrmng->def_policy_id = MLX5_INVALID_POLICY_ID;
644 * Close and release all the resources of
645 * the ASO flow meter management structure.
648 * Pointer to mlx5_dev_ctx_shared object to free.
651 mlx5_aso_flow_mtrs_mng_close(struct mlx5_dev_ctx_shared *sh)
653 struct mlx5_aso_mtr_pool *mtr_pool;
654 struct mlx5_flow_mtr_mng *mtrmng = sh->mtrmng;
656 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
657 struct mlx5_aso_mtr *aso_mtr;
659 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
661 if (sh->meter_aso_en) {
662 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_POLICER);
663 idx = mtrmng->pools_mng.n_valid;
665 mtr_pool = mtrmng->pools_mng.pools[idx];
666 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
667 for (i = 0; i < MLX5_ASO_MTRS_PER_POOL; i++) {
668 aso_mtr = &mtr_pool->mtrs[i];
669 if (aso_mtr->fm.meter_action)
671 (mlx5_glue->destroy_flow_action
672 (aso_mtr->fm.meter_action));
674 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
675 claim_zero(mlx5_devx_cmd_destroy
676 (mtr_pool->devx_obj));
677 mtrmng->pools_mng.n_valid--;
680 mlx5_free(sh->mtrmng->pools_mng.pools);
682 mlx5_free(sh->mtrmng);
686 /* Send FLOW_AGED event if needed. */
688 mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh)
690 struct mlx5_age_info *age_info;
693 for (i = 0; i < sh->max_port; i++) {
694 age_info = &sh->port[i].age_info;
695 if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW))
697 MLX5_AGE_UNSET(age_info, MLX5_AGE_EVENT_NEW);
698 if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER)) {
699 MLX5_AGE_UNSET(age_info, MLX5_AGE_TRIGGER);
700 rte_eth_dev_callback_process
701 (&rte_eth_devices[sh->port[i].devx_ih_port_id],
702 RTE_ETH_EVENT_FLOW_AGED, NULL);
708 * Initialize the ASO connection tracking structure.
711 * Pointer to mlx5_dev_ctx_shared object.
714 * 0 on success, a negative errno value otherwise and rte_errno is set.
717 mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh)
723 sh->ct_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->ct_mng),
724 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
726 DRV_LOG(ERR, "ASO CT management allocation failed.");
730 err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
732 mlx5_free(sh->ct_mng);
733 /* rte_errno should be extracted from the failure. */
737 rte_spinlock_init(&sh->ct_mng->ct_sl);
738 rte_rwlock_init(&sh->ct_mng->resize_rwl);
739 LIST_INIT(&sh->ct_mng->free_cts);
744 * Close and release all the resources of the
745 * ASO connection tracking management structure.
748 * Pointer to mlx5_dev_ctx_shared object to free.
751 mlx5_flow_aso_ct_mng_close(struct mlx5_dev_ctx_shared *sh)
753 struct mlx5_aso_ct_pools_mng *mng = sh->ct_mng;
754 struct mlx5_aso_ct_pool *ct_pool;
755 struct mlx5_aso_ct_action *ct;
761 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
765 ct_pool = mng->pools[idx];
766 for (i = 0; i < MLX5_ASO_CT_ACTIONS_PER_POOL; i++) {
767 ct = &ct_pool->actions[i];
768 val = __atomic_fetch_sub(&ct->refcnt, 1,
770 MLX5_ASSERT(val == 1);
773 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
774 if (ct->dr_action_orig)
775 claim_zero(mlx5_glue->destroy_flow_action
776 (ct->dr_action_orig));
777 if (ct->dr_action_rply)
778 claim_zero(mlx5_glue->destroy_flow_action
779 (ct->dr_action_rply));
782 claim_zero(mlx5_devx_cmd_destroy(ct_pool->devx_obj));
784 DRV_LOG(DEBUG, "%u ASO CT objects are being used in the pool %u",
788 /* in case of failure. */
791 mlx5_free(mng->pools);
793 /* Management structure must be cleared to 0s during allocation. */
798 * Initialize the flow resources' indexed mempool.
801 * Pointer to mlx5_dev_ctx_shared object.
803 * Pointer to user dev config.
806 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
807 const struct mlx5_dev_config *config)
810 struct mlx5_indexed_pool_config cfg;
812 for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
813 cfg = mlx5_ipool_cfg[i];
818 * Set MLX5_IPOOL_MLX5_FLOW ipool size
819 * according to PCI function flow configuration.
821 case MLX5_IPOOL_MLX5_FLOW:
822 cfg.size = config->dv_flow_en ?
823 sizeof(struct mlx5_flow_handle) :
824 MLX5_FLOW_HANDLE_VERBS_SIZE;
827 if (config->reclaim_mode) {
828 cfg.release_mem_en = 1;
829 cfg.per_core_cache = 0;
831 cfg.release_mem_en = 0;
833 sh->ipool[i] = mlx5_ipool_create(&cfg);
839 * Release the flow resources' indexed mempool.
842 * Pointer to mlx5_dev_ctx_shared object.
845 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
849 for (i = 0; i < MLX5_IPOOL_MAX; ++i)
850 mlx5_ipool_destroy(sh->ipool[i]);
851 for (i = 0; i < MLX5_MAX_MODIFY_NUM; ++i)
852 if (sh->mdh_ipools[i])
853 mlx5_ipool_destroy(sh->mdh_ipools[i]);
857 * Check if dynamic flex parser for eCPRI already exists.
860 * Pointer to Ethernet device structure.
863 * true on exists, false on not.
866 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
868 struct mlx5_priv *priv = dev->data->dev_private;
869 struct mlx5_flex_parser_profiles *prf =
870 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
876 * Allocation of a flex parser for eCPRI. Once created, this parser related
877 * resources will be held until the device is closed.
880 * Pointer to Ethernet device structure.
883 * 0 on success, a negative errno value otherwise and rte_errno is set.
886 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
888 struct mlx5_priv *priv = dev->data->dev_private;
889 struct mlx5_flex_parser_profiles *prf =
890 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
891 struct mlx5_devx_graph_node_attr node = {
892 .modify_field_select = 0,
897 if (!priv->config.hca_attr.parse_graph_flex_node) {
898 DRV_LOG(ERR, "Dynamic flex parser is not supported "
899 "for device %s.", priv->dev_data->name);
902 node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
903 /* 8 bytes now: 4B common header + 4B message body header. */
904 node.header_length_base_value = 0x8;
905 /* After MAC layer: Ether / VLAN. */
906 node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
907 /* Type of compared condition should be 0xAEFE in the L2 layer. */
908 node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
909 /* Sample #0: type in common header. */
910 node.sample[0].flow_match_sample_en = 1;
912 node.sample[0].flow_match_sample_offset_mode = 0x0;
913 /* Only the 2nd byte will be used. */
914 node.sample[0].flow_match_sample_field_base_offset = 0x0;
915 /* Sample #1: message payload. */
916 node.sample[1].flow_match_sample_en = 1;
918 node.sample[1].flow_match_sample_offset_mode = 0x0;
920 * Only the first two bytes will be used right now, and its offset will
921 * start after the common header that with the length of a DW(u32).
923 node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
924 prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->cdev->ctx, &node);
926 DRV_LOG(ERR, "Failed to create flex parser node object.");
927 return (rte_errno == 0) ? -ENODEV : -rte_errno;
930 ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
932 DRV_LOG(ERR, "Failed to query sample IDs.");
933 return (rte_errno == 0) ? -ENODEV : -rte_errno;
935 prf->offset[0] = 0x0;
936 prf->offset[1] = sizeof(uint32_t);
937 prf->ids[0] = ids[0];
938 prf->ids[1] = ids[1];
943 * Destroy the flex parser node, including the parser itself, input / output
944 * arcs and DW samples. Resources could be reused then.
947 * Pointer to Ethernet device structure.
950 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
952 struct mlx5_priv *priv = dev->data->dev_private;
953 struct mlx5_flex_parser_profiles *prf =
954 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
957 mlx5_devx_cmd_destroy(prf->obj);
962 mlx5_get_supported_sw_parsing_offloads(const struct mlx5_hca_attr *attr)
964 uint32_t sw_parsing_offloads = 0;
967 sw_parsing_offloads |= MLX5_SW_PARSING_CAP;
969 sw_parsing_offloads |= MLX5_SW_PARSING_CSUM_CAP;
972 sw_parsing_offloads |= MLX5_SW_PARSING_TSO_CAP;
974 return sw_parsing_offloads;
978 mlx5_get_supported_tunneling_offloads(const struct mlx5_hca_attr *attr)
980 uint32_t tn_offloads = 0;
982 if (attr->tunnel_stateless_vxlan)
983 tn_offloads |= MLX5_TUNNELED_OFFLOADS_VXLAN_CAP;
984 if (attr->tunnel_stateless_gre)
985 tn_offloads |= MLX5_TUNNELED_OFFLOADS_GRE_CAP;
986 if (attr->tunnel_stateless_geneve_rx)
987 tn_offloads |= MLX5_TUNNELED_OFFLOADS_GENEVE_CAP;
992 * Allocate Rx and Tx UARs in robust fashion.
993 * This routine handles the following UAR allocation issues:
995 * - tries to allocate the UAR with the most appropriate memory
996 * mapping type from the ones supported by the host
998 * - tries to allocate the UAR with non-NULL base address
999 * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
1000 * UAR base address if UAR was not the first object in the UAR page.
1001 * It caused the PMD failure and we should try to get another UAR
1002 * till we get the first one with non-NULL base address returned.
1005 mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh,
1006 const struct mlx5_common_dev_config *config)
1008 uint32_t uar_mapping, retry;
1012 for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
1013 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
1014 /* Control the mapping type according to the settings. */
1015 uar_mapping = (config->dbnc == MLX5_TXDB_NCACHED) ?
1016 MLX5DV_UAR_ALLOC_TYPE_NC :
1017 MLX5DV_UAR_ALLOC_TYPE_BF;
1019 RTE_SET_USED(config);
1021 * It seems we have no way to control the memory mapping type
1022 * for the UAR, the default "Write-Combining" type is supposed.
1023 * The UAR initialization on queue creation queries the
1024 * actual mapping type done by Verbs/kernel and setups the
1025 * PMD datapath accordingly.
1029 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->cdev->ctx,
1031 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
1033 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
1034 if (config->dbnc == MLX5_TXDB_CACHED ||
1035 config->dbnc == MLX5_TXDB_HEURISTIC)
1036 DRV_LOG(WARNING, "Devarg tx_db_nc setting "
1037 "is not supported by DevX");
1039 * In some environments like virtual machine
1040 * the Write Combining mapped might be not supported
1041 * and UAR allocation fails. We try "Non-Cached"
1042 * mapping for the case. The tx_burst routines take
1043 * the UAR mapping type into account on UAR setup
1044 * on queue creation.
1046 DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (BF)");
1047 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
1048 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->cdev->ctx,
1050 } else if (!sh->tx_uar &&
1051 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) {
1052 if (config->dbnc == MLX5_TXDB_NCACHED)
1053 DRV_LOG(WARNING, "Devarg tx_db_nc settings "
1054 "is not supported by DevX");
1056 * If Verbs/kernel does not support "Non-Cached"
1057 * try the "Write-Combining".
1059 DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (NC)");
1060 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;
1061 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->cdev->ctx,
1066 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (BF/NC)");
1070 base_addr = mlx5_os_get_devx_uar_base_addr(sh->tx_uar);
1074 * The UARs are allocated by rdma_core within the
1075 * IB device context, on context closure all UARs
1076 * will be freed, should be no memory/object leakage.
1078 DRV_LOG(DEBUG, "Retrying to allocate Tx DevX UAR");
1081 /* Check whether we finally succeeded with valid UAR allocation. */
1083 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (NULL base)");
1087 for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
1089 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar(sh->cdev->ctx,
1091 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
1092 if (!sh->devx_rx_uar &&
1093 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
1095 * Rx UAR is used to control interrupts only,
1096 * should be no datapath noticeable impact,
1097 * can try "Non-Cached" mapping safely.
1099 DRV_LOG(DEBUG, "Failed to allocate Rx DevX UAR (BF)");
1100 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
1101 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
1102 (sh->cdev->ctx, uar_mapping);
1105 if (!sh->devx_rx_uar) {
1106 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (BF/NC)");
1110 base_addr = mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar);
1114 * The UARs are allocated by rdma_core within the
1115 * IB device context, on context closure all UARs
1116 * will be freed, should be no memory/object leakage.
1118 DRV_LOG(DEBUG, "Retrying to allocate Rx DevX UAR");
1119 sh->devx_rx_uar = NULL;
1121 /* Check whether we finally succeeded with valid UAR allocation. */
1122 if (!sh->devx_rx_uar) {
1123 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (NULL base)");
1131 * Unregister the mempool from the protection domain.
1134 * Pointer to the device shared context.
1136 * Mempool being unregistered.
1139 mlx5_dev_ctx_shared_mempool_unregister(struct mlx5_dev_ctx_shared *sh,
1140 struct rte_mempool *mp)
1142 struct mlx5_mp_id mp_id;
1144 mlx5_mp_id_init(&mp_id, 0);
1145 if (mlx5_mr_mempool_unregister(&sh->share_cache, mp, &mp_id) < 0)
1146 DRV_LOG(WARNING, "Failed to unregister mempool %s for PD %p: %s",
1147 mp->name, sh->cdev->pd, rte_strerror(rte_errno));
1151 * rte_mempool_walk() callback to register mempools
1152 * for the protection domain.
1155 * The mempool being walked.
1157 * Pointer to the device shared context.
1160 mlx5_dev_ctx_shared_mempool_register_cb(struct rte_mempool *mp, void *arg)
1162 struct mlx5_dev_ctx_shared *sh = arg;
1163 struct mlx5_mp_id mp_id;
1166 mlx5_mp_id_init(&mp_id, 0);
1167 ret = mlx5_mr_mempool_register(&sh->share_cache, sh->cdev->pd, mp,
1169 if (ret < 0 && rte_errno != EEXIST)
1170 DRV_LOG(ERR, "Failed to register existing mempool %s for PD %p: %s",
1171 mp->name, sh->cdev->pd, rte_strerror(rte_errno));
1175 * rte_mempool_walk() callback to unregister mempools
1176 * from the protection domain.
1179 * The mempool being walked.
1181 * Pointer to the device shared context.
1184 mlx5_dev_ctx_shared_mempool_unregister_cb(struct rte_mempool *mp, void *arg)
1186 mlx5_dev_ctx_shared_mempool_unregister
1187 ((struct mlx5_dev_ctx_shared *)arg, mp);
1191 * Mempool life cycle callback for Ethernet devices.
1194 * Mempool life cycle event.
1196 * Associated mempool.
1198 * Pointer to a device shared context.
1201 mlx5_dev_ctx_shared_mempool_event_cb(enum rte_mempool_event event,
1202 struct rte_mempool *mp, void *arg)
1204 struct mlx5_dev_ctx_shared *sh = arg;
1205 struct mlx5_mp_id mp_id;
1208 case RTE_MEMPOOL_EVENT_READY:
1209 mlx5_mp_id_init(&mp_id, 0);
1210 if (mlx5_mr_mempool_register(&sh->share_cache, sh->cdev->pd, mp,
1212 DRV_LOG(ERR, "Failed to register new mempool %s for PD %p: %s",
1213 mp->name, sh->cdev->pd,
1214 rte_strerror(rte_errno));
1216 case RTE_MEMPOOL_EVENT_DESTROY:
1217 mlx5_dev_ctx_shared_mempool_unregister(sh, mp);
1223 * Callback used when implicit mempool registration is disabled
1224 * in order to track Rx mempool destruction.
1227 * Mempool life cycle event.
1229 * An Rx mempool registered explicitly when the port is started.
1231 * Pointer to a device shared context.
1234 mlx5_dev_ctx_shared_rx_mempool_event_cb(enum rte_mempool_event event,
1235 struct rte_mempool *mp, void *arg)
1237 struct mlx5_dev_ctx_shared *sh = arg;
1239 if (event == RTE_MEMPOOL_EVENT_DESTROY)
1240 mlx5_dev_ctx_shared_mempool_unregister(sh, mp);
1244 mlx5_dev_ctx_shared_mempool_subscribe(struct rte_eth_dev *dev)
1246 struct mlx5_priv *priv = dev->data->dev_private;
1247 struct mlx5_dev_ctx_shared *sh = priv->sh;
1250 /* Check if we only need to track Rx mempool destruction. */
1251 if (!sh->cdev->config.mr_mempool_reg_en) {
1252 ret = rte_mempool_event_callback_register
1253 (mlx5_dev_ctx_shared_rx_mempool_event_cb, sh);
1254 return ret == 0 || rte_errno == EEXIST ? 0 : ret;
1256 /* Callback for this shared context may be already registered. */
1257 ret = rte_mempool_event_callback_register
1258 (mlx5_dev_ctx_shared_mempool_event_cb, sh);
1259 if (ret != 0 && rte_errno != EEXIST)
1261 /* Register mempools only once for this shared context. */
1263 rte_mempool_walk(mlx5_dev_ctx_shared_mempool_register_cb, sh);
1268 * Allocate shared device context. If there is multiport device the
1269 * master and representors will share this context, if there is single
1270 * port dedicated device, the context will be used by only given
1271 * port due to unification.
1273 * Routine first searches the context for the specified device name,
1274 * if found the shared context assumed and reference counter is incremented.
1275 * If no context found the new one is created and initialized with specified
1276 * device context and parameters.
1279 * Pointer to the device attributes (name, port, etc).
1281 * Pointer to device configuration structure.
1284 * Pointer to mlx5_dev_ctx_shared object on success,
1285 * otherwise NULL and rte_errno is set.
1287 struct mlx5_dev_ctx_shared *
1288 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
1289 const struct mlx5_dev_config *config)
1291 struct mlx5_dev_ctx_shared *sh;
1294 struct mlx5_devx_tis_attr tis_attr = { 0 };
1297 /* Secondary process should not create the shared context. */
1298 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1299 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1300 /* Search for IB context by device name. */
1301 LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
1302 if (!strcmp(sh->ibdev_name, spawn->phys_dev_name)) {
1307 /* No device found, we have to create new shared context. */
1308 MLX5_ASSERT(spawn->max_port);
1309 sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
1310 sizeof(struct mlx5_dev_ctx_shared) +
1312 sizeof(struct mlx5_dev_shared_port),
1313 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
1315 DRV_LOG(ERR, "shared context allocation failure");
1319 pthread_mutex_init(&sh->txpp.mutex, NULL);
1320 sh->numa_node = spawn->cdev->dev->numa_node;
1321 sh->cdev = spawn->cdev;
1322 sh->devx = sh->cdev->config.devx;
1323 if (spawn->bond_info)
1324 sh->bond = *spawn->bond_info;
1325 err = mlx5_os_get_dev_attr(sh->cdev, &sh->device_attr);
1327 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
1331 sh->max_port = spawn->max_port;
1332 sh->reclaim_mode = config->reclaim_mode;
1333 strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->cdev->ctx),
1334 sizeof(sh->ibdev_name) - 1);
1335 strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->cdev->ctx),
1336 sizeof(sh->ibdev_path) - 1);
1338 * Setting port_id to max unallowed value means
1339 * there is no interrupt subhandler installed for
1340 * the given port index i.
1342 for (i = 0; i < sh->max_port; i++) {
1343 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
1344 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
1347 sh->td = mlx5_devx_cmd_create_td(sh->cdev->ctx);
1349 DRV_LOG(ERR, "TD allocation failure");
1353 tis_attr.transport_domain = sh->td->id;
1354 sh->tis = mlx5_devx_cmd_create_tis(sh->cdev->ctx, &tis_attr);
1356 DRV_LOG(ERR, "TIS allocation failure");
1360 err = mlx5_alloc_rxtx_uars(sh, &sh->cdev->config);
1363 MLX5_ASSERT(sh->tx_uar);
1364 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar));
1366 MLX5_ASSERT(sh->devx_rx_uar);
1367 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar));
1370 /* Initialize UAR access locks for 32bit implementations. */
1371 rte_spinlock_init(&sh->uar_lock_cq);
1372 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
1373 rte_spinlock_init(&sh->uar_lock[i]);
1376 * Once the device is added to the list of memory event
1377 * callback, its global MR cache table cannot be expanded
1378 * on the fly because of deadlock. If it overflows, lookup
1379 * should be done by searching MR list linearly, which is slow.
1381 * At this point the device is not added to the memory
1382 * event list yet, context is just being created.
1384 err = mlx5_mr_btree_init(&sh->share_cache.cache,
1385 MLX5_MR_BTREE_CACHE_N * 2,
1391 mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
1392 &sh->share_cache.dereg_mr_cb);
1393 mlx5_os_dev_shared_handler_install(sh);
1394 if (LIST_EMPTY(&mlx5_dev_ctx_list)) {
1395 err = mlx5_flow_os_init_workspace_once();
1399 mlx5_flow_aging_init(sh);
1400 mlx5_flow_counters_mng_init(sh);
1401 mlx5_flow_ipool_create(sh, config);
1402 /* Add device to memory callback list. */
1403 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1404 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
1406 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1407 /* Add context to the global device list. */
1408 LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
1409 rte_spinlock_init(&sh->geneve_tlv_opt_sl);
1411 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1414 pthread_mutex_destroy(&sh->txpp.mutex);
1415 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1417 if (sh->share_cache.cache.table)
1418 mlx5_mr_btree_free(&sh->share_cache.cache);
1420 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1422 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1423 if (sh->devx_rx_uar)
1424 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1426 mlx5_glue->devx_free_uar(sh->tx_uar);
1428 MLX5_ASSERT(err > 0);
1434 * Free shared IB device context. Decrement counter and if zero free
1435 * all allocated resources and close handles.
1438 * Pointer to mlx5_dev_ctx_shared object to free
1441 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
1445 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1446 #ifdef RTE_LIBRTE_MLX5_DEBUG
1447 /* Check the object presence in the list. */
1448 struct mlx5_dev_ctx_shared *lctx;
1450 LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
1455 DRV_LOG(ERR, "Freeing non-existing shared IB context");
1460 MLX5_ASSERT(sh->refcnt);
1461 /* Secondary process should not free the shared context. */
1462 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1465 /* Stop watching for mempool events and unregister all mempools. */
1466 ret = rte_mempool_event_callback_unregister
1467 (mlx5_dev_ctx_shared_mempool_event_cb, sh);
1468 if (ret < 0 && rte_errno == ENOENT)
1469 ret = rte_mempool_event_callback_unregister
1470 (mlx5_dev_ctx_shared_rx_mempool_event_cb, sh);
1472 rte_mempool_walk(mlx5_dev_ctx_shared_mempool_unregister_cb,
1474 /* Remove from memory callback device list. */
1475 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1476 LIST_REMOVE(sh, mem_event_cb);
1477 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1478 /* Release created Memory Regions. */
1479 mlx5_mr_release_cache(&sh->share_cache);
1480 /* Remove context from the global device list. */
1481 LIST_REMOVE(sh, next);
1482 /* Release flow workspaces objects on the last device. */
1483 if (LIST_EMPTY(&mlx5_dev_ctx_list))
1484 mlx5_flow_os_release_workspace();
1485 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1487 * Ensure there is no async event handler installed.
1488 * Only primary process handles async device events.
1490 mlx5_flow_counters_mng_close(sh);
1491 if (sh->aso_age_mng) {
1492 mlx5_flow_aso_age_mng_close(sh);
1493 sh->aso_age_mng = NULL;
1496 mlx5_aso_flow_mtrs_mng_close(sh);
1497 mlx5_flow_ipool_destroy(sh);
1498 mlx5_os_dev_shared_handler_uninstall(sh);
1500 mlx5_glue->devx_free_uar(sh->tx_uar);
1504 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1506 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1507 if (sh->devx_rx_uar)
1508 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1509 MLX5_ASSERT(sh->geneve_tlv_option_resource == NULL);
1510 pthread_mutex_destroy(&sh->txpp.mutex);
1514 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1518 * Destroy table hash list.
1521 * Pointer to the private device data structure.
1524 mlx5_free_table_hash_list(struct mlx5_priv *priv)
1526 struct mlx5_dev_ctx_shared *sh = priv->sh;
1530 mlx5_hlist_destroy(sh->flow_tbls);
1531 sh->flow_tbls = NULL;
1535 * Initialize flow table hash list and create the root tables entry
1539 * Pointer to the private device data structure.
1542 * Zero on success, positive error code otherwise.
1545 mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused)
1548 /* Tables are only used in DV and DR modes. */
1549 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
1550 struct mlx5_dev_ctx_shared *sh = priv->sh;
1551 char s[MLX5_NAME_SIZE];
1554 snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1555 sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE,
1557 flow_dv_tbl_create_cb,
1558 flow_dv_tbl_match_cb,
1559 flow_dv_tbl_remove_cb,
1560 flow_dv_tbl_clone_cb,
1561 flow_dv_tbl_clone_free_cb);
1562 if (!sh->flow_tbls) {
1563 DRV_LOG(ERR, "flow tables with hash creation failed.");
1567 #ifndef HAVE_MLX5DV_DR
1568 struct rte_flow_error error;
1569 struct rte_eth_dev *dev = &rte_eth_devices[priv->dev_data->port_id];
1572 * In case we have not DR support, the zero tables should be created
1573 * because DV expect to see them even if they cannot be created by
1576 if (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0,
1577 NULL, 0, 1, 0, &error) ||
1578 !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0,
1579 NULL, 0, 1, 0, &error) ||
1580 !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0,
1581 NULL, 0, 1, 0, &error)) {
1587 mlx5_free_table_hash_list(priv);
1588 #endif /* HAVE_MLX5DV_DR */
1594 * Retrieve integer value from environment variable.
1597 * Environment variable name.
1600 * Integer value, 0 if the variable is not set.
1603 mlx5_getenv_int(const char *name)
1605 const char *val = getenv(name);
1613 * DPDK callback to add udp tunnel port
1616 * A pointer to eth_dev
1617 * @param[in] udp_tunnel
1618 * A pointer to udp tunnel
1621 * 0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1624 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1625 struct rte_eth_udp_tunnel *udp_tunnel)
1627 MLX5_ASSERT(udp_tunnel != NULL);
1628 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1629 udp_tunnel->udp_port == 4789)
1631 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1632 udp_tunnel->udp_port == 4790)
1638 * Initialize process private data structure.
1641 * Pointer to Ethernet device structure.
1644 * 0 on success, a negative errno value otherwise and rte_errno is set.
1647 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1649 struct mlx5_priv *priv = dev->data->dev_private;
1650 struct mlx5_proc_priv *ppriv;
1653 mlx5_proc_priv_uninit(dev);
1655 * UAR register table follows the process private structure. BlueFlame
1656 * registers for Tx queues are stored in the table.
1659 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1660 ppriv = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, ppriv_size,
1661 RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1666 ppriv->uar_table_sz = priv->txqs_n;
1667 dev->process_private = ppriv;
1672 * Un-initialize process private data structure.
1675 * Pointer to Ethernet device structure.
1678 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1680 if (!dev->process_private)
1682 mlx5_free(dev->process_private);
1683 dev->process_private = NULL;
1687 * DPDK callback to close the device.
1689 * Destroy all queues and objects, free memory.
1692 * Pointer to Ethernet device structure.
1695 mlx5_dev_close(struct rte_eth_dev *dev)
1697 struct mlx5_priv *priv = dev->data->dev_private;
1701 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1702 /* Check if process_private released. */
1703 if (!dev->process_private)
1705 mlx5_tx_uar_uninit_secondary(dev);
1706 mlx5_proc_priv_uninit(dev);
1707 rte_eth_dev_release_port(dev);
1712 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1714 ((priv->sh->cdev->ctx != NULL) ?
1715 mlx5_os_get_ctx_device_name(priv->sh->cdev->ctx) : ""));
1717 * If default mreg copy action is removed at the stop stage,
1718 * the search will return none and nothing will be done anymore.
1720 mlx5_flow_stop_default(dev);
1721 mlx5_traffic_disable(dev);
1723 * If all the flows are already flushed in the device stop stage,
1724 * then this will return directly without any action.
1726 mlx5_flow_list_flush(dev, MLX5_FLOW_TYPE_GEN, true);
1727 mlx5_action_handle_flush(dev);
1728 mlx5_flow_meter_flush(dev, NULL);
1729 /* Prevent crashes when queues are still in use. */
1730 dev->rx_pkt_burst = removed_rx_burst;
1731 dev->tx_pkt_burst = removed_tx_burst;
1733 /* Disable datapath on secondary process. */
1734 mlx5_mp_os_req_stop_rxtx(dev);
1735 /* Free the eCPRI flex parser resource. */
1736 mlx5_flex_parser_ecpri_release(dev);
1737 if (priv->rxqs != NULL) {
1738 /* XXX race condition if mlx5_rx_burst() is still running. */
1739 rte_delay_us_sleep(1000);
1740 for (i = 0; (i != priv->rxqs_n); ++i)
1741 mlx5_rxq_release(dev, i);
1745 if (priv->representor) {
1746 /* Each representor has a dedicated interrupts handler */
1747 mlx5_free(dev->intr_handle);
1748 dev->intr_handle = NULL;
1750 if (priv->txqs != NULL) {
1751 /* XXX race condition if mlx5_tx_burst() is still running. */
1752 rte_delay_us_sleep(1000);
1753 for (i = 0; (i != priv->txqs_n); ++i)
1754 mlx5_txq_release(dev, i);
1758 mlx5_proc_priv_uninit(dev);
1759 if (priv->q_counters) {
1760 mlx5_devx_cmd_destroy(priv->q_counters);
1761 priv->q_counters = NULL;
1763 if (priv->drop_queue.hrxq)
1764 mlx5_drop_action_destroy(dev);
1765 if (priv->mreg_cp_tbl)
1766 mlx5_hlist_destroy(priv->mreg_cp_tbl);
1767 mlx5_mprq_free_mp(dev);
1768 if (priv->sh->ct_mng)
1769 mlx5_flow_aso_ct_mng_close(priv->sh);
1770 mlx5_os_free_shared_dr(priv);
1771 if (priv->rss_conf.rss_key != NULL)
1772 mlx5_free(priv->rss_conf.rss_key);
1773 if (priv->reta_idx != NULL)
1774 mlx5_free(priv->reta_idx);
1775 if (priv->config.vf)
1776 mlx5_os_mac_addr_flush(dev);
1777 if (priv->nl_socket_route >= 0)
1778 close(priv->nl_socket_route);
1779 if (priv->nl_socket_rdma >= 0)
1780 close(priv->nl_socket_rdma);
1781 if (priv->vmwa_context)
1782 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1783 ret = mlx5_hrxq_verify(dev);
1785 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1786 dev->data->port_id);
1787 ret = mlx5_ind_table_obj_verify(dev);
1789 DRV_LOG(WARNING, "port %u some indirection table still remain",
1790 dev->data->port_id);
1791 ret = mlx5_rxq_obj_verify(dev);
1793 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1794 dev->data->port_id);
1795 ret = mlx5_rxq_verify(dev);
1797 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1798 dev->data->port_id);
1799 ret = mlx5_txq_obj_verify(dev);
1801 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1802 dev->data->port_id);
1803 ret = mlx5_txq_verify(dev);
1805 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1806 dev->data->port_id);
1807 ret = mlx5_flow_verify(dev);
1809 DRV_LOG(WARNING, "port %u some flows still remain",
1810 dev->data->port_id);
1812 mlx5_list_destroy(priv->hrxqs);
1814 * Free the shared context in last turn, because the cleanup
1815 * routines above may use some shared fields, like
1816 * mlx5_os_mac_addr_flush() uses ibdev_path for retrieveing
1817 * ifindex if Netlink fails.
1819 mlx5_free_shared_dev_ctx(priv->sh);
1820 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1824 MLX5_ETH_FOREACH_DEV(port_id, dev->device) {
1825 struct mlx5_priv *opriv =
1826 rte_eth_devices[port_id].data->dev_private;
1829 opriv->domain_id != priv->domain_id ||
1830 &rte_eth_devices[port_id] == dev)
1836 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1838 memset(priv, 0, sizeof(*priv));
1839 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1841 * Reset mac_addrs to NULL such that it is not freed as part of
1842 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1843 * it is freed when dev_private is freed.
1845 dev->data->mac_addrs = NULL;
1849 const struct eth_dev_ops mlx5_dev_ops = {
1850 .dev_configure = mlx5_dev_configure,
1851 .dev_start = mlx5_dev_start,
1852 .dev_stop = mlx5_dev_stop,
1853 .dev_set_link_down = mlx5_set_link_down,
1854 .dev_set_link_up = mlx5_set_link_up,
1855 .dev_close = mlx5_dev_close,
1856 .promiscuous_enable = mlx5_promiscuous_enable,
1857 .promiscuous_disable = mlx5_promiscuous_disable,
1858 .allmulticast_enable = mlx5_allmulticast_enable,
1859 .allmulticast_disable = mlx5_allmulticast_disable,
1860 .link_update = mlx5_link_update,
1861 .stats_get = mlx5_stats_get,
1862 .stats_reset = mlx5_stats_reset,
1863 .xstats_get = mlx5_xstats_get,
1864 .xstats_reset = mlx5_xstats_reset,
1865 .xstats_get_names = mlx5_xstats_get_names,
1866 .fw_version_get = mlx5_fw_version_get,
1867 .dev_infos_get = mlx5_dev_infos_get,
1868 .representor_info_get = mlx5_representor_info_get,
1869 .read_clock = mlx5_txpp_read_clock,
1870 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1871 .vlan_filter_set = mlx5_vlan_filter_set,
1872 .rx_queue_setup = mlx5_rx_queue_setup,
1873 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1874 .tx_queue_setup = mlx5_tx_queue_setup,
1875 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1876 .rx_queue_release = mlx5_rx_queue_release,
1877 .tx_queue_release = mlx5_tx_queue_release,
1878 .rx_queue_start = mlx5_rx_queue_start,
1879 .rx_queue_stop = mlx5_rx_queue_stop,
1880 .tx_queue_start = mlx5_tx_queue_start,
1881 .tx_queue_stop = mlx5_tx_queue_stop,
1882 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1883 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1884 .mac_addr_remove = mlx5_mac_addr_remove,
1885 .mac_addr_add = mlx5_mac_addr_add,
1886 .mac_addr_set = mlx5_mac_addr_set,
1887 .set_mc_addr_list = mlx5_set_mc_addr_list,
1888 .mtu_set = mlx5_dev_set_mtu,
1889 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1890 .vlan_offload_set = mlx5_vlan_offload_set,
1891 .reta_update = mlx5_dev_rss_reta_update,
1892 .reta_query = mlx5_dev_rss_reta_query,
1893 .rss_hash_update = mlx5_rss_hash_update,
1894 .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1895 .flow_ops_get = mlx5_flow_ops_get,
1896 .rxq_info_get = mlx5_rxq_info_get,
1897 .txq_info_get = mlx5_txq_info_get,
1898 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1899 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1900 .rx_queue_intr_enable = mlx5_rx_intr_enable,
1901 .rx_queue_intr_disable = mlx5_rx_intr_disable,
1902 .is_removed = mlx5_is_removed,
1903 .udp_tunnel_port_add = mlx5_udp_tunnel_port_add,
1904 .get_module_info = mlx5_get_module_info,
1905 .get_module_eeprom = mlx5_get_module_eeprom,
1906 .hairpin_cap_get = mlx5_hairpin_cap_get,
1907 .mtr_ops_get = mlx5_flow_meter_ops_get,
1908 .hairpin_bind = mlx5_hairpin_bind,
1909 .hairpin_unbind = mlx5_hairpin_unbind,
1910 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1911 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1912 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1913 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1914 .get_monitor_addr = mlx5_get_monitor_addr,
1917 /* Available operations from secondary process. */
1918 const struct eth_dev_ops mlx5_dev_sec_ops = {
1919 .stats_get = mlx5_stats_get,
1920 .stats_reset = mlx5_stats_reset,
1921 .xstats_get = mlx5_xstats_get,
1922 .xstats_reset = mlx5_xstats_reset,
1923 .xstats_get_names = mlx5_xstats_get_names,
1924 .fw_version_get = mlx5_fw_version_get,
1925 .dev_infos_get = mlx5_dev_infos_get,
1926 .representor_info_get = mlx5_representor_info_get,
1927 .read_clock = mlx5_txpp_read_clock,
1928 .rx_queue_start = mlx5_rx_queue_start,
1929 .rx_queue_stop = mlx5_rx_queue_stop,
1930 .tx_queue_start = mlx5_tx_queue_start,
1931 .tx_queue_stop = mlx5_tx_queue_stop,
1932 .rxq_info_get = mlx5_rxq_info_get,
1933 .txq_info_get = mlx5_txq_info_get,
1934 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1935 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1936 .get_module_info = mlx5_get_module_info,
1937 .get_module_eeprom = mlx5_get_module_eeprom,
1940 /* Available operations in flow isolated mode. */
1941 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1942 .dev_configure = mlx5_dev_configure,
1943 .dev_start = mlx5_dev_start,
1944 .dev_stop = mlx5_dev_stop,
1945 .dev_set_link_down = mlx5_set_link_down,
1946 .dev_set_link_up = mlx5_set_link_up,
1947 .dev_close = mlx5_dev_close,
1948 .promiscuous_enable = mlx5_promiscuous_enable,
1949 .promiscuous_disable = mlx5_promiscuous_disable,
1950 .allmulticast_enable = mlx5_allmulticast_enable,
1951 .allmulticast_disable = mlx5_allmulticast_disable,
1952 .link_update = mlx5_link_update,
1953 .stats_get = mlx5_stats_get,
1954 .stats_reset = mlx5_stats_reset,
1955 .xstats_get = mlx5_xstats_get,
1956 .xstats_reset = mlx5_xstats_reset,
1957 .xstats_get_names = mlx5_xstats_get_names,
1958 .fw_version_get = mlx5_fw_version_get,
1959 .dev_infos_get = mlx5_dev_infos_get,
1960 .representor_info_get = mlx5_representor_info_get,
1961 .read_clock = mlx5_txpp_read_clock,
1962 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1963 .vlan_filter_set = mlx5_vlan_filter_set,
1964 .rx_queue_setup = mlx5_rx_queue_setup,
1965 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1966 .tx_queue_setup = mlx5_tx_queue_setup,
1967 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1968 .rx_queue_release = mlx5_rx_queue_release,
1969 .tx_queue_release = mlx5_tx_queue_release,
1970 .rx_queue_start = mlx5_rx_queue_start,
1971 .rx_queue_stop = mlx5_rx_queue_stop,
1972 .tx_queue_start = mlx5_tx_queue_start,
1973 .tx_queue_stop = mlx5_tx_queue_stop,
1974 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1975 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1976 .mac_addr_remove = mlx5_mac_addr_remove,
1977 .mac_addr_add = mlx5_mac_addr_add,
1978 .mac_addr_set = mlx5_mac_addr_set,
1979 .set_mc_addr_list = mlx5_set_mc_addr_list,
1980 .mtu_set = mlx5_dev_set_mtu,
1981 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1982 .vlan_offload_set = mlx5_vlan_offload_set,
1983 .flow_ops_get = mlx5_flow_ops_get,
1984 .rxq_info_get = mlx5_rxq_info_get,
1985 .txq_info_get = mlx5_txq_info_get,
1986 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1987 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1988 .rx_queue_intr_enable = mlx5_rx_intr_enable,
1989 .rx_queue_intr_disable = mlx5_rx_intr_disable,
1990 .is_removed = mlx5_is_removed,
1991 .get_module_info = mlx5_get_module_info,
1992 .get_module_eeprom = mlx5_get_module_eeprom,
1993 .hairpin_cap_get = mlx5_hairpin_cap_get,
1994 .mtr_ops_get = mlx5_flow_meter_ops_get,
1995 .hairpin_bind = mlx5_hairpin_bind,
1996 .hairpin_unbind = mlx5_hairpin_unbind,
1997 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1998 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1999 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
2000 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
2001 .get_monitor_addr = mlx5_get_monitor_addr,
2005 * Verify and store value for device argument.
2008 * Key argument to verify.
2010 * Value associated with key.
2015 * 0 on success, a negative errno value otherwise and rte_errno is set.
2018 mlx5_args_check(const char *key, const char *val, void *opaque)
2020 struct mlx5_dev_config *config = opaque;
2024 /* No-op, port representors are processed in mlx5_dev_spawn(). */
2025 if (!strcmp(MLX5_DRIVER_KEY, key) || !strcmp(MLX5_REPRESENTOR, key) ||
2026 !strcmp(MLX5_SYS_MEM_EN, key) || !strcmp(MLX5_TX_DB_NC, key) ||
2027 !strcmp(MLX5_MR_MEMPOOL_REG_EN, key) ||
2028 !strcmp(MLX5_MR_EXT_MEMSEG_EN, key))
2031 tmp = strtol(val, NULL, 0);
2034 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
2037 if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
2038 /* Negative values are acceptable for some keys only. */
2040 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
2043 mod = tmp >= 0 ? tmp : -tmp;
2044 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
2045 if (tmp > MLX5_CQE_RESP_FORMAT_L34H_STRIDX) {
2046 DRV_LOG(ERR, "invalid CQE compression "
2047 "format parameter");
2051 config->cqe_comp = !!tmp;
2052 config->cqe_comp_fmt = tmp;
2053 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
2054 config->hw_padding = !!tmp;
2055 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
2056 config->mprq.enabled = !!tmp;
2057 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
2058 config->mprq.stride_num_n = tmp;
2059 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
2060 config->mprq.stride_size_n = tmp;
2061 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
2062 config->mprq.max_memcpy_len = tmp;
2063 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
2064 config->mprq.min_rxqs_num = tmp;
2065 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
2066 DRV_LOG(WARNING, "%s: deprecated parameter,"
2067 " converted to txq_inline_max", key);
2068 config->txq_inline_max = tmp;
2069 } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
2070 config->txq_inline_max = tmp;
2071 } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
2072 config->txq_inline_min = tmp;
2073 } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
2074 config->txq_inline_mpw = tmp;
2075 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
2076 config->txqs_inline = tmp;
2077 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
2078 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
2079 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
2080 config->mps = !!tmp;
2081 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
2082 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
2083 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
2084 DRV_LOG(WARNING, "%s: deprecated parameter,"
2085 " converted to txq_inline_mpw", key);
2086 config->txq_inline_mpw = tmp;
2087 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
2088 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
2089 } else if (strcmp(MLX5_TX_PP, key) == 0) {
2091 DRV_LOG(ERR, "Zero Tx packet pacing parameter");
2095 config->tx_pp = tmp;
2096 } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
2097 config->tx_skew = tmp;
2098 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
2099 config->rx_vec_en = !!tmp;
2100 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
2101 config->l3_vxlan_en = !!tmp;
2102 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
2103 config->vf_nl_en = !!tmp;
2104 } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
2105 config->dv_esw_en = !!tmp;
2106 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
2107 config->dv_flow_en = !!tmp;
2108 } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
2109 if (tmp != MLX5_XMETA_MODE_LEGACY &&
2110 tmp != MLX5_XMETA_MODE_META16 &&
2111 tmp != MLX5_XMETA_MODE_META32 &&
2112 tmp != MLX5_XMETA_MODE_MISS_INFO) {
2113 DRV_LOG(ERR, "invalid extensive "
2114 "metadata parameter");
2118 if (tmp != MLX5_XMETA_MODE_MISS_INFO)
2119 config->dv_xmeta_en = tmp;
2121 config->dv_miss_info = 1;
2122 } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
2123 config->lacp_by_user = !!tmp;
2124 } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
2125 config->max_dump_files_num = tmp;
2126 } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
2127 config->lro.timeout = tmp;
2128 } else if (strcmp(RTE_DEVARGS_KEY_CLASS, key) == 0) {
2129 DRV_LOG(DEBUG, "class argument is %s.", val);
2130 } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
2131 config->log_hp_size = tmp;
2132 } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
2133 if (tmp != MLX5_RCM_NONE &&
2134 tmp != MLX5_RCM_LIGHT &&
2135 tmp != MLX5_RCM_AGGR) {
2136 DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
2140 config->reclaim_mode = tmp;
2141 } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
2142 config->decap_en = !!tmp;
2143 } else if (strcmp(MLX5_ALLOW_DUPLICATE_PATTERN, key) == 0) {
2144 config->allow_duplicate_pattern = !!tmp;
2146 DRV_LOG(WARNING, "%s: unknown parameter", key);
2154 * Parse device parameters.
2157 * Pointer to device configuration structure.
2159 * Device arguments structure.
2162 * 0 on success, a negative errno value otherwise and rte_errno is set.
2165 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
2167 const char **params = (const char *[]){
2169 MLX5_RXQ_CQE_COMP_EN,
2170 MLX5_RXQ_PKT_PAD_EN,
2172 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
2173 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
2174 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
2177 MLX5_TXQ_INLINE_MIN,
2178 MLX5_TXQ_INLINE_MAX,
2179 MLX5_TXQ_INLINE_MPW,
2180 MLX5_TXQS_MIN_INLINE,
2183 MLX5_TXQ_MPW_HDR_DSEG_EN,
2184 MLX5_TXQ_MAX_INLINE_LEN,
2196 MLX5_MR_EXT_MEMSEG_EN,
2198 MLX5_MAX_DUMP_FILES_NUM,
2199 MLX5_LRO_TIMEOUT_USEC,
2200 RTE_DEVARGS_KEY_CLASS,
2205 MLX5_ALLOW_DUPLICATE_PATTERN,
2206 MLX5_MR_MEMPOOL_REG_EN,
2209 struct rte_kvargs *kvlist;
2213 if (devargs == NULL)
2215 /* Following UGLY cast is done to pass checkpatch. */
2216 kvlist = rte_kvargs_parse(devargs->args, params);
2217 if (kvlist == NULL) {
2221 /* Process parameters. */
2222 for (i = 0; (params[i] != NULL); ++i) {
2223 if (rte_kvargs_count(kvlist, params[i])) {
2224 ret = rte_kvargs_process(kvlist, params[i],
2225 mlx5_args_check, config);
2228 rte_kvargs_free(kvlist);
2233 rte_kvargs_free(kvlist);
2238 * Configures the minimal amount of data to inline into WQE
2239 * while sending packets.
2241 * - the txq_inline_min has the maximal priority, if this
2242 * key is specified in devargs
2243 * - if DevX is enabled the inline mode is queried from the
2244 * device (HCA attributes and NIC vport context if needed).
2245 * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
2246 * and none (0 bytes) for other NICs
2249 * Verbs device parameters (name, port, switch_info) to spawn.
2251 * Device configuration parameters.
2254 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
2255 struct mlx5_dev_config *config)
2257 if (config->txq_inline_min != MLX5_ARG_UNSET) {
2258 /* Application defines size of inlined data explicitly. */
2259 if (spawn->pci_dev != NULL) {
2260 switch (spawn->pci_dev->id.device_id) {
2261 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2262 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2263 if (config->txq_inline_min <
2264 (int)MLX5_INLINE_HSIZE_L2) {
2266 "txq_inline_mix aligned to minimal ConnectX-4 required value %d",
2267 (int)MLX5_INLINE_HSIZE_L2);
2268 config->txq_inline_min =
2269 MLX5_INLINE_HSIZE_L2;
2276 if (config->hca_attr.eth_net_offloads) {
2277 /* We have DevX enabled, inline mode queried successfully. */
2278 switch (config->hca_attr.wqe_inline_mode) {
2279 case MLX5_CAP_INLINE_MODE_L2:
2280 /* outer L2 header must be inlined. */
2281 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2283 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
2284 /* No inline data are required by NIC. */
2285 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2286 config->hw_vlan_insert =
2287 config->hca_attr.wqe_vlan_insert;
2288 DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
2290 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
2291 /* inline mode is defined by NIC vport context. */
2292 if (!config->hca_attr.eth_virt)
2294 switch (config->hca_attr.vport_inline_mode) {
2295 case MLX5_INLINE_MODE_NONE:
2296 config->txq_inline_min =
2297 MLX5_INLINE_HSIZE_NONE;
2299 case MLX5_INLINE_MODE_L2:
2300 config->txq_inline_min =
2301 MLX5_INLINE_HSIZE_L2;
2303 case MLX5_INLINE_MODE_IP:
2304 config->txq_inline_min =
2305 MLX5_INLINE_HSIZE_L3;
2307 case MLX5_INLINE_MODE_TCP_UDP:
2308 config->txq_inline_min =
2309 MLX5_INLINE_HSIZE_L4;
2311 case MLX5_INLINE_MODE_INNER_L2:
2312 config->txq_inline_min =
2313 MLX5_INLINE_HSIZE_INNER_L2;
2315 case MLX5_INLINE_MODE_INNER_IP:
2316 config->txq_inline_min =
2317 MLX5_INLINE_HSIZE_INNER_L3;
2319 case MLX5_INLINE_MODE_INNER_TCP_UDP:
2320 config->txq_inline_min =
2321 MLX5_INLINE_HSIZE_INNER_L4;
2326 if (spawn->pci_dev == NULL) {
2327 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2331 * We get here if we are unable to deduce
2332 * inline data size with DevX. Try PCI ID
2333 * to determine old NICs.
2335 switch (spawn->pci_dev->id.device_id) {
2336 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2337 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2338 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
2339 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
2340 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2341 config->hw_vlan_insert = 0;
2343 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
2344 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
2345 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
2346 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
2348 * These NICs support VLAN insertion from WQE and
2349 * report the wqe_vlan_insert flag. But there is the bug
2350 * and PFC control may be broken, so disable feature.
2352 config->hw_vlan_insert = 0;
2353 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2356 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2360 DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
2364 * Configures the metadata mask fields in the shared context.
2367 * Pointer to Ethernet device.
2370 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
2372 struct mlx5_priv *priv = dev->data->dev_private;
2373 struct mlx5_dev_ctx_shared *sh = priv->sh;
2374 uint32_t meta, mark, reg_c0;
2376 reg_c0 = ~priv->vport_meta_mask;
2377 switch (priv->config.dv_xmeta_en) {
2378 case MLX5_XMETA_MODE_LEGACY:
2380 mark = MLX5_FLOW_MARK_MASK;
2382 case MLX5_XMETA_MODE_META16:
2383 meta = reg_c0 >> rte_bsf32(reg_c0);
2384 mark = MLX5_FLOW_MARK_MASK;
2386 case MLX5_XMETA_MODE_META32:
2388 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
2396 if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
2397 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
2398 sh->dv_mark_mask, mark);
2400 sh->dv_mark_mask = mark;
2401 if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
2402 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
2403 sh->dv_meta_mask, meta);
2405 sh->dv_meta_mask = meta;
2406 if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
2407 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
2408 sh->dv_meta_mask, reg_c0);
2410 sh->dv_regc0_mask = reg_c0;
2411 DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
2412 DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
2413 DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
2414 DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
2418 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
2420 static const char *const dynf_names[] = {
2421 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
2422 RTE_MBUF_DYNFLAG_METADATA_NAME,
2423 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
2427 if (n < RTE_DIM(dynf_names))
2429 for (i = 0; i < RTE_DIM(dynf_names); i++) {
2430 if (names[i] == NULL)
2432 strcpy(names[i], dynf_names[i]);
2434 return RTE_DIM(dynf_names);
2438 * Comparison callback to sort device data.
2440 * This is meant to be used with qsort().
2443 * Pointer to pointer to first data object.
2445 * Pointer to pointer to second data object.
2448 * 0 if both objects are equal, less than 0 if the first argument is less
2449 * than the second, greater than 0 otherwise.
2452 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
2453 struct mlx5_dev_config *config,
2454 struct rte_device *dpdk_dev)
2456 struct mlx5_dev_ctx_shared *sh = priv->sh;
2457 struct mlx5_dev_config *sh_conf = NULL;
2461 /* Nothing to compare for the single/first device. */
2462 if (sh->refcnt == 1)
2464 /* Find the device with shared context. */
2465 MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) {
2466 struct mlx5_priv *opriv =
2467 rte_eth_devices[port_id].data->dev_private;
2469 if (opriv && opriv != priv && opriv->sh == sh) {
2470 sh_conf = &opriv->config;
2476 if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
2477 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
2478 " for shared %s context", sh->ibdev_name);
2482 if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
2483 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
2484 " for shared %s context", sh->ibdev_name);
2492 * Look for the ethernet device belonging to mlx5 driver.
2494 * @param[in] port_id
2495 * port_id to start looking for device.
2497 * Pointer to the hint device. When device is being probed
2498 * the its siblings (master and preceding representors might
2499 * not have assigned driver yet (because the mlx5_os_pci_probe()
2500 * is not completed yet, for this case match on hint
2501 * device may be used to detect sibling device.
2504 * port_id of found device, RTE_MAX_ETHPORT if not found.
2507 mlx5_eth_find_next(uint16_t port_id, struct rte_device *odev)
2509 while (port_id < RTE_MAX_ETHPORTS) {
2510 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
2512 if (dev->state != RTE_ETH_DEV_UNUSED &&
2514 (dev->device == odev ||
2515 (dev->device->driver &&
2516 dev->device->driver->name &&
2517 ((strcmp(dev->device->driver->name,
2518 MLX5_PCI_DRIVER_NAME) == 0) ||
2519 (strcmp(dev->device->driver->name,
2520 MLX5_AUXILIARY_DRIVER_NAME) == 0)))))
2524 if (port_id >= RTE_MAX_ETHPORTS)
2525 return RTE_MAX_ETHPORTS;
2530 * Callback to remove a device.
2532 * This function removes all Ethernet devices belong to a given device.
2535 * Pointer to the generic device.
2538 * 0 on success, the function cannot fail.
2541 mlx5_net_remove(struct mlx5_common_device *cdev)
2546 RTE_ETH_FOREACH_DEV_OF(port_id, cdev->dev) {
2548 * mlx5_dev_close() is not registered to secondary process,
2549 * call the close function explicitly for secondary process.
2551 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
2552 ret |= mlx5_dev_close(&rte_eth_devices[port_id]);
2554 ret |= rte_eth_dev_close(port_id);
2556 return ret == 0 ? 0 : -EIO;
2559 static const struct rte_pci_id mlx5_pci_id_map[] = {
2561 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2562 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
2565 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2566 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
2569 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2570 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
2573 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2574 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2577 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2578 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2581 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2582 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2585 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2586 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2589 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2590 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2593 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2594 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2597 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2598 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2601 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2602 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2605 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2606 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2609 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2610 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2613 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2614 PCI_DEVICE_ID_MELLANOX_CONNECTXVF)
2617 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2618 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2621 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2622 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2625 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2626 PCI_DEVICE_ID_MELLANOX_CONNECTX7)
2629 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2630 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF)
2637 static struct mlx5_class_driver mlx5_net_driver = {
2638 .drv_class = MLX5_CLASS_ETH,
2639 .name = RTE_STR(MLX5_ETH_DRIVER_NAME),
2640 .id_table = mlx5_pci_id_map,
2641 .probe = mlx5_os_net_probe,
2642 .remove = mlx5_net_remove,
2643 .dma_map = mlx5_net_dma_map,
2644 .dma_unmap = mlx5_net_dma_unmap,
2650 /* Initialize driver log type. */
2651 RTE_LOG_REGISTER_DEFAULT(mlx5_logtype, NOTICE)
2654 * Driver initialization routine.
2656 RTE_INIT(rte_mlx5_pmd_init)
2658 pthread_mutex_init(&mlx5_dev_ctx_list_mutex, NULL);
2660 /* Build the static tables for Verbs conversion. */
2661 mlx5_set_ptype_table();
2662 mlx5_set_cksum_table();
2663 mlx5_set_swp_types_table();
2665 mlx5_class_driver_register(&mlx5_net_driver);
2668 RTE_PMD_EXPORT_NAME(MLX5_ETH_DRIVER_NAME, __COUNTER__);
2669 RTE_PMD_REGISTER_PCI_TABLE(MLX5_ETH_DRIVER_NAME, mlx5_pci_id_map);
2670 RTE_PMD_REGISTER_KMOD_DEP(MLX5_ETH_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib");