1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_H_
7 #define RTE_PMD_MLX5_H_
13 #include <netinet/in.h>
14 #include <sys/queue.h>
17 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
19 #pragma GCC diagnostic ignored "-Wpedantic"
21 #include <infiniband/verbs.h>
23 #pragma GCC diagnostic error "-Wpedantic"
27 #include <rte_ether.h>
28 #include <rte_ethdev_driver.h>
29 #include <rte_rwlock.h>
30 #include <rte_interrupts.h>
31 #include <rte_errno.h>
34 #include "mlx5_utils.h"
36 #include "mlx5_rxtx.h"
37 #include "mlx5_autoconf.h"
38 #include "mlx5_defs.h"
41 PCI_VENDOR_ID_MELLANOX = 0x15b3,
45 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013,
46 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014,
47 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015,
48 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016,
49 PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017,
50 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018,
51 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019,
52 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a,
53 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF = 0xa2d2,
54 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF = 0xa2d3,
57 /** Switch information returned by mlx5_nl_switch_info(). */
58 struct mlx5_switch_info {
59 uint32_t master:1; /**< Master device. */
60 uint32_t representor:1; /**< Representor device. */
61 int32_t port_name; /**< Representor port name. */
62 uint64_t switch_id; /**< Switch identifier. */
65 LIST_HEAD(mlx5_dev_list, priv);
67 /* Shared memory between primary and secondary processes. */
68 struct mlx5_shared_data {
69 struct mlx5_dev_list mem_event_cb_list;
70 rte_rwlock_t mem_event_rwlock;
73 extern struct mlx5_shared_data *mlx5_shared_data;
75 struct mlx5_counter_ctrl {
76 /* Name of the counter. */
77 char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE];
78 /* Name of the counter on the device table. */
79 char ctr_name[RTE_ETH_XSTATS_NAME_SIZE];
80 uint32_t ib:1; /**< Nonzero for IB counters. */
83 struct mlx5_xstats_ctrl {
84 /* Number of device stats. */
86 /* Number of device stats identified by PMD. */
87 uint16_t mlx5_stats_n;
88 /* Index in the device counters table. */
89 uint16_t dev_table_idx[MLX5_MAX_XSTATS];
90 uint64_t base[MLX5_MAX_XSTATS];
91 struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS];
95 TAILQ_HEAD(mlx5_flows, rte_flow);
97 /* Default PMD specific parameter value. */
98 #define MLX5_ARG_UNSET (-1)
101 * Device configuration structure.
103 * Merged configuration from:
105 * - Device capabilities,
106 * - User device parameters disabled features.
108 struct mlx5_dev_config {
109 unsigned int hw_csum:1; /* Checksum offload is supported. */
110 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */
111 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */
112 unsigned int hw_padding:1; /* End alignment padding is supported. */
113 unsigned int vf:1; /* This is a VF. */
114 unsigned int tunnel_en:1;
115 /* Whether tunnel stateless offloads are supported. */
116 unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */
117 unsigned int flow_counter_en:1; /* Whether flow counter is supported. */
118 unsigned int cqe_comp:1; /* CQE compression is enabled. */
119 unsigned int tso:1; /* Whether TSO is supported. */
120 unsigned int tx_vec_en:1; /* Tx vector is enabled. */
121 unsigned int rx_vec_en:1; /* Rx vector is enabled. */
122 unsigned int mpw_hdr_dseg:1; /* Enable DSEGs in the title WQEBB. */
123 unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */
124 unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */
125 unsigned int dv_flow_en:1; /* Enable DV flow. */
126 unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */
128 unsigned int enabled:1; /* Whether MPRQ is enabled. */
129 unsigned int stride_num_n; /* Number of strides. */
130 unsigned int min_stride_size_n; /* Min size of a stride. */
131 unsigned int max_stride_size_n; /* Max size of a stride. */
132 unsigned int max_memcpy_len;
133 /* Maximum packet size to memcpy Rx packets. */
134 unsigned int min_rxqs_num;
135 /* Rx queue count threshold to enable MPRQ. */
136 } mprq; /* Configurations for Multi-Packet RQ. */
137 int mps; /* Multi-packet send supported mode. */
138 unsigned int flow_prio; /* Number of flow priorities. */
139 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */
140 unsigned int ind_table_max_size; /* Maximum indirection table size. */
141 int txq_inline; /* Maximum packet size for inlining. */
142 int txqs_inline; /* Queue number threshold for inlining. */
143 int inline_max_packet_sz; /* Max packet size for inlining. */
147 * Type of objet being allocated.
149 enum mlx5_verbs_alloc_type {
150 MLX5_VERBS_ALLOC_TYPE_NONE,
151 MLX5_VERBS_ALLOC_TYPE_TX_QUEUE,
152 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE,
156 * Verbs allocator needs a context to know in the callback which kind of
157 * resources it is allocating.
159 struct mlx5_verbs_alloc_ctx {
160 enum mlx5_verbs_alloc_type type; /* Kind of object being allocated. */
161 const void *obj; /* Pointer to the DPDK object. */
164 LIST_HEAD(mlx5_mr_list, mlx5_mr);
166 /* Flow drop context necessary due to Verbs API. */
168 struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */
169 struct mlx5_rxq_ibv *rxq; /* Verbs Rx queue. */
175 LIST_ENTRY(priv) mem_event_cb; /* Called by memory event callback. */
176 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */
177 struct ibv_context *ctx; /* Verbs context. */
178 struct ibv_device_attr_ex device_attr; /* Device properties. */
179 struct ibv_pd *pd; /* Protection Domain. */
180 char ibdev_name[IBV_SYSFS_NAME_MAX]; /* IB device name. */
181 char ibdev_path[IBV_SYSFS_PATH_MAX]; /* IB device path for secondary */
182 struct ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */
183 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES);
184 /* Bit-field of MAC addresses owned by the PMD. */
185 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */
186 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */
187 /* Device properties. */
188 uint16_t mtu; /* Configured MTU. */
189 unsigned int isolated:1; /* Whether isolated mode is enabled. */
190 unsigned int representor:1; /* Device is a port representor. */
191 uint16_t domain_id; /* Switch domain identifier. */
192 int32_t representor_id; /* Port representor identifier. */
194 unsigned int rxqs_n; /* RX queues array size. */
195 unsigned int txqs_n; /* TX queues array size. */
196 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */
197 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */
198 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
199 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */
200 struct rte_intr_handle intr_handle; /* Interrupt handler. */
201 unsigned int (*reta_idx)[]; /* RETA index table. */
202 unsigned int reta_idx_n; /* RETA index size. */
203 struct mlx5_drop drop_queue; /* Flow drop queues. */
204 struct mlx5_flows flows; /* RTE Flow rules. */
205 struct mlx5_flows ctrl_flows; /* Control flow rules. */
206 LIST_HEAD(counters, mlx5_flow_counter) flow_counters;
209 uint32_t dev_gen; /* Generation number to flush local caches. */
210 rte_rwlock_t rwlock; /* MR Lock. */
211 struct mlx5_mr_btree cache; /* Global MR cache table. */
212 struct mlx5_mr_list mr_list; /* Registered MR list. */
213 struct mlx5_mr_list mr_free_list; /* Freed MR list. */
215 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */
216 LIST_HEAD(rxqibv, mlx5_rxq_ibv) rxqsibv; /* Verbs Rx queues. */
217 LIST_HEAD(hrxq, mlx5_hrxq) hrxqs; /* Verbs Hash Rx queues. */
218 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */
219 LIST_HEAD(txqibv, mlx5_txq_ibv) txqsibv; /* Verbs Tx queues. */
220 /* Verbs Indirection tables. */
221 LIST_HEAD(ind_tables, mlx5_ind_table_ibv) ind_tbls;
222 LIST_HEAD(matchers, mlx5_flow_dv_matcher) matchers;
223 uint32_t link_speed_capa; /* Link speed capabilities. */
224 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */
225 int primary_socket; /* Unix socket for primary process. */
226 void *uar_base; /* Reserved address space for UAR mapping */
227 struct rte_intr_handle intr_handle_socket; /* Interrupt handler. */
228 struct mlx5_dev_config config; /* Device configuration. */
229 struct mlx5_verbs_alloc_ctx verbs_alloc_ctx;
230 /* Context for Verbs allocator. */
231 int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */
232 int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */
233 uint32_t nl_sn; /* Netlink message sequence number. */
235 rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */
236 rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX];
237 /* UAR same-page access control required in 32bit implementations. */
239 struct mnl_socket *mnl_socket; /* Libmnl socket. */
242 #define PORT_ID(priv) ((priv)->dev_data->port_id)
243 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)])
247 int mlx5_getenv_int(const char *);
251 int mlx5_get_ifname(const struct rte_eth_dev *dev, char (*ifname)[IF_NAMESIZE]);
252 unsigned int mlx5_ifindex(const struct rte_eth_dev *dev);
253 int mlx5_ifreq(const struct rte_eth_dev *dev, int req, struct ifreq *ifr);
254 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu);
255 int mlx5_set_flags(struct rte_eth_dev *dev, unsigned int keep,
257 int mlx5_dev_configure(struct rte_eth_dev *dev);
258 void mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info);
259 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev);
260 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete);
261 int mlx5_force_link_status_change(struct rte_eth_dev *dev, int status);
262 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
263 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev,
264 struct rte_eth_fc_conf *fc_conf);
265 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev,
266 struct rte_eth_fc_conf *fc_conf);
267 int mlx5_ibv_device_to_pci_addr(const struct ibv_device *device,
268 struct rte_pci_addr *pci_addr);
269 void mlx5_dev_link_status_handler(void *arg);
270 void mlx5_dev_interrupt_handler(void *arg);
271 void mlx5_dev_interrupt_handler_uninstall(struct rte_eth_dev *dev);
272 void mlx5_dev_interrupt_handler_install(struct rte_eth_dev *dev);
273 int mlx5_set_link_down(struct rte_eth_dev *dev);
274 int mlx5_set_link_up(struct rte_eth_dev *dev);
275 int mlx5_is_removed(struct rte_eth_dev *dev);
276 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev);
277 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev);
278 unsigned int mlx5_dev_to_port_id(const struct rte_device *dev,
280 unsigned int port_list_n);
281 int mlx5_sysfs_switch_info(unsigned int ifindex,
282 struct mlx5_switch_info *info);
286 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[ETHER_ADDR_LEN]);
287 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
288 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac,
289 uint32_t index, uint32_t vmdq);
290 int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr);
291 int mlx5_set_mc_addr_list(struct rte_eth_dev *dev,
292 struct ether_addr *mc_addr_set, uint32_t nb_mc_addr);
296 int mlx5_rss_hash_update(struct rte_eth_dev *dev,
297 struct rte_eth_rss_conf *rss_conf);
298 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev,
299 struct rte_eth_rss_conf *rss_conf);
300 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size);
301 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev,
302 struct rte_eth_rss_reta_entry64 *reta_conf,
304 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev,
305 struct rte_eth_rss_reta_entry64 *reta_conf,
310 void mlx5_promiscuous_enable(struct rte_eth_dev *dev);
311 void mlx5_promiscuous_disable(struct rte_eth_dev *dev);
312 void mlx5_allmulticast_enable(struct rte_eth_dev *dev);
313 void mlx5_allmulticast_disable(struct rte_eth_dev *dev);
317 void mlx5_xstats_init(struct rte_eth_dev *dev);
318 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
319 void mlx5_stats_reset(struct rte_eth_dev *dev);
320 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats,
322 void mlx5_xstats_reset(struct rte_eth_dev *dev);
323 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
324 struct rte_eth_xstat_name *xstats_names,
329 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
330 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on);
331 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask);
335 int mlx5_dev_start(struct rte_eth_dev *dev);
336 void mlx5_dev_stop(struct rte_eth_dev *dev);
337 int mlx5_traffic_enable(struct rte_eth_dev *dev);
338 void mlx5_traffic_disable(struct rte_eth_dev *dev);
339 int mlx5_traffic_restart(struct rte_eth_dev *dev);
343 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
344 void mlx5_flow_print(struct rte_flow *flow);
345 int mlx5_flow_validate(struct rte_eth_dev *dev,
346 const struct rte_flow_attr *attr,
347 const struct rte_flow_item items[],
348 const struct rte_flow_action actions[],
349 struct rte_flow_error *error);
350 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev,
351 const struct rte_flow_attr *attr,
352 const struct rte_flow_item items[],
353 const struct rte_flow_action actions[],
354 struct rte_flow_error *error);
355 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow,
356 struct rte_flow_error *error);
357 void mlx5_flow_list_flush(struct rte_eth_dev *dev, struct mlx5_flows *list);
358 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error);
359 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow,
360 const struct rte_flow_action *action, void *data,
361 struct rte_flow_error *error);
362 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable,
363 struct rte_flow_error *error);
364 int mlx5_dev_filter_ctrl(struct rte_eth_dev *dev,
365 enum rte_filter_type filter_type,
366 enum rte_filter_op filter_op,
368 int mlx5_flow_start(struct rte_eth_dev *dev, struct mlx5_flows *list);
369 void mlx5_flow_stop(struct rte_eth_dev *dev, struct mlx5_flows *list);
370 int mlx5_flow_verify(struct rte_eth_dev *dev);
371 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev,
372 struct rte_flow_item_eth *eth_spec,
373 struct rte_flow_item_eth *eth_mask,
374 struct rte_flow_item_vlan *vlan_spec,
375 struct rte_flow_item_vlan *vlan_mask);
376 int mlx5_ctrl_flow(struct rte_eth_dev *dev,
377 struct rte_flow_item_eth *eth_spec,
378 struct rte_flow_item_eth *eth_mask);
379 int mlx5_flow_create_drop_queue(struct rte_eth_dev *dev);
380 void mlx5_flow_delete_drop_queue(struct rte_eth_dev *dev);
384 int mlx5_socket_init(struct rte_eth_dev *priv);
385 void mlx5_socket_uninit(struct rte_eth_dev *priv);
386 void mlx5_socket_handle(struct rte_eth_dev *priv);
387 int mlx5_socket_connect(struct rte_eth_dev *priv);
391 int mlx5_nl_init(int protocol);
392 int mlx5_nl_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac,
394 int mlx5_nl_mac_addr_remove(struct rte_eth_dev *dev, struct ether_addr *mac,
396 void mlx5_nl_mac_addr_sync(struct rte_eth_dev *dev);
397 void mlx5_nl_mac_addr_flush(struct rte_eth_dev *dev);
398 int mlx5_nl_promisc(struct rte_eth_dev *dev, int enable);
399 int mlx5_nl_allmulti(struct rte_eth_dev *dev, int enable);
400 unsigned int mlx5_nl_ifindex(int nl, const char *name);
401 int mlx5_nl_switch_info(int nl, unsigned int ifindex,
402 struct mlx5_switch_info *info);
404 #endif /* RTE_PMD_MLX5_H_ */