1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_H_
7 #define RTE_PMD_MLX5_H_
14 #include <netinet/in.h>
15 #include <sys/queue.h>
18 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
20 #pragma GCC diagnostic ignored "-Wpedantic"
22 #include <infiniband/verbs.h>
24 #pragma GCC diagnostic error "-Wpedantic"
28 #include <rte_ether.h>
29 #include <rte_ethdev_driver.h>
30 #include <rte_rwlock.h>
31 #include <rte_interrupts.h>
32 #include <rte_errno.h>
35 #include "mlx5_utils.h"
37 #include "mlx5_autoconf.h"
38 #include "mlx5_defs.h"
39 #include "mlx5_glue.h"
41 #include "mlx5_devx_cmds.h"
44 PCI_VENDOR_ID_MELLANOX = 0x15b3,
48 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013,
49 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014,
50 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015,
51 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016,
52 PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017,
53 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018,
54 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019,
55 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a,
56 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF = 0xa2d2,
57 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF = 0xa2d3,
58 PCI_DEVICE_ID_MELLANOX_CONNECTX6 = 0x101b,
59 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF = 0x101c,
60 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX = 0x101d,
61 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF = 0x101e,
64 /* Request types for IPC. */
65 enum mlx5_mp_req_type {
66 MLX5_MP_REQ_VERBS_CMD_FD = 1,
67 MLX5_MP_REQ_CREATE_MR,
68 MLX5_MP_REQ_START_RXTX,
69 MLX5_MP_REQ_STOP_RXTX,
70 MLX5_MP_REQ_QUEUE_STATE_MODIFY,
73 struct mlx5_mp_arg_queue_state_modify {
74 uint8_t is_wq; /* Set if WQ. */
75 uint16_t queue_id; /* DPDK queue ID. */
76 enum ibv_wq_state state; /* WQ requested state. */
79 /* Pameters for IPC. */
80 struct mlx5_mp_param {
81 enum mlx5_mp_req_type type;
86 uintptr_t addr; /* MLX5_MP_REQ_CREATE_MR */
87 struct mlx5_mp_arg_queue_state_modify state_modify;
88 /* MLX5_MP_REQ_QUEUE_STATE_MODIFY */
92 /** Request timeout for IPC. */
93 #define MLX5_MP_REQ_TIMEOUT_SEC 5
95 /** Key string for IPC. */
96 #define MLX5_MP_NAME "net_mlx5_mp"
98 /* Recognized Infiniband device physical port name types. */
99 enum mlx5_phys_port_name_type {
100 MLX5_PHYS_PORT_NAME_TYPE_NOTSET = 0, /* Not set. */
101 MLX5_PHYS_PORT_NAME_TYPE_LEGACY, /* before kernel ver < 5.0 */
102 MLX5_PHYS_PORT_NAME_TYPE_UPLINK, /* p0, kernel ver >= 5.0 */
103 MLX5_PHYS_PORT_NAME_TYPE_PFVF, /* pf0vf0, kernel ver >= 5.0 */
104 MLX5_PHYS_PORT_NAME_TYPE_UNKNOWN, /* Unrecognized. */
107 /** Switch information returned by mlx5_nl_switch_info(). */
108 struct mlx5_switch_info {
109 uint32_t master:1; /**< Master device. */
110 uint32_t representor:1; /**< Representor device. */
111 enum mlx5_phys_port_name_type name_type; /** < Port name type. */
112 int32_t pf_num; /**< PF number (valid for pfxvfx format only). */
113 int32_t port_name; /**< Representor port name. */
114 uint64_t switch_id; /**< Switch identifier. */
117 LIST_HEAD(mlx5_dev_list, mlx5_ibv_shared);
119 /* Shared data between primary and secondary processes. */
120 struct mlx5_shared_data {
122 /* Global spinlock for primary and secondary processes. */
123 int init_done; /* Whether primary has done initialization. */
124 unsigned int secondary_cnt; /* Number of secondary processes init'd. */
125 struct mlx5_dev_list mem_event_cb_list;
126 rte_rwlock_t mem_event_rwlock;
129 /* Per-process data structure, not visible to other processes. */
130 struct mlx5_local_data {
131 int init_done; /* Whether a secondary has done initialization. */
134 extern struct mlx5_shared_data *mlx5_shared_data;
136 struct mlx5_counter_ctrl {
137 /* Name of the counter. */
138 char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE];
139 /* Name of the counter on the device table. */
140 char ctr_name[RTE_ETH_XSTATS_NAME_SIZE];
141 uint32_t ib:1; /**< Nonzero for IB counters. */
144 struct mlx5_xstats_ctrl {
145 /* Number of device stats. */
147 /* Number of device stats identified by PMD. */
148 uint16_t mlx5_stats_n;
149 /* Index in the device counters table. */
150 uint16_t dev_table_idx[MLX5_MAX_XSTATS];
151 uint64_t base[MLX5_MAX_XSTATS];
152 struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS];
155 struct mlx5_stats_ctrl {
156 /* Base for imissed counter. */
157 uint64_t imissed_base;
161 TAILQ_HEAD(mlx5_flows, rte_flow);
163 /* Default PMD specific parameter value. */
164 #define MLX5_ARG_UNSET (-1)
166 #define MLX5_LRO_SUPPORTED(dev) \
167 (((struct mlx5_priv *)((dev)->data->dev_private))->config.lro.supported)
169 /* Maximal size of coalesced segment for LRO is set in chunks of 256 Bytes. */
170 #define MLX5_LRO_SEG_CHUNK_SIZE 256u
172 /* Maximal size of aggregated LRO packet. */
173 #define MLX5_MAX_LRO_SIZE (UINT8_MAX * MLX5_LRO_SEG_CHUNK_SIZE)
175 /* LRO configurations structure. */
176 struct mlx5_lro_config {
177 uint32_t supported:1; /* Whether LRO is supported. */
178 uint32_t timeout; /* User configuration. */
182 * Device configuration structure.
184 * Merged configuration from:
186 * - Device capabilities,
187 * - User device parameters disabled features.
189 struct mlx5_dev_config {
190 unsigned int hw_csum:1; /* Checksum offload is supported. */
191 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */
192 unsigned int hw_vlan_insert:1; /* VLAN insertion in WQE is supported. */
193 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */
194 unsigned int hw_padding:1; /* End alignment padding is supported. */
195 unsigned int vf:1; /* This is a VF. */
196 unsigned int tunnel_en:1;
197 /* Whether tunnel stateless offloads are supported. */
198 unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */
199 unsigned int cqe_comp:1; /* CQE compression is enabled. */
200 unsigned int cqe_pad:1; /* CQE padding is enabled. */
201 unsigned int tso:1; /* Whether TSO is supported. */
202 unsigned int rx_vec_en:1; /* Rx vector is enabled. */
203 unsigned int mr_ext_memseg_en:1;
204 /* Whether memseg should be extended for MR creation. */
205 unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */
206 unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */
207 unsigned int dv_esw_en:1; /* Enable E-Switch DV flow. */
208 unsigned int dv_flow_en:1; /* Enable DV flow. */
209 unsigned int dv_xmeta_en:2; /* Enable extensive flow metadata. */
210 unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */
211 unsigned int devx:1; /* Whether devx interface is available or not. */
212 unsigned int dest_tir:1; /* Whether advanced DR API is available. */
214 unsigned int enabled:1; /* Whether MPRQ is enabled. */
215 unsigned int stride_num_n; /* Number of strides. */
216 unsigned int min_stride_size_n; /* Min size of a stride. */
217 unsigned int max_stride_size_n; /* Max size of a stride. */
218 unsigned int max_memcpy_len;
219 /* Maximum packet size to memcpy Rx packets. */
220 unsigned int min_rxqs_num;
221 /* Rx queue count threshold to enable MPRQ. */
222 } mprq; /* Configurations for Multi-Packet RQ. */
223 int mps; /* Multi-packet send supported mode. */
224 int dbnc; /* Skip doorbell register write barrier. */
225 unsigned int flow_prio; /* Number of flow priorities. */
226 enum modify_reg flow_mreg_c[MLX5_MREG_C_NUM];
227 /* Availibility of mreg_c's. */
228 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */
229 unsigned int ind_table_max_size; /* Maximum indirection table size. */
230 unsigned int max_dump_files_num; /* Maximum dump files per queue. */
231 int txqs_inline; /* Queue number threshold for inlining. */
232 int txq_inline_min; /* Minimal amount of data bytes to inline. */
233 int txq_inline_max; /* Max packet size for inlining with SEND. */
234 int txq_inline_mpw; /* Max packet size for inlining with eMPW. */
235 struct mlx5_hca_attr hca_attr; /* HCA attributes. */
236 struct mlx5_lro_config lro; /* LRO configuration. */
241 * Type of object being allocated.
243 enum mlx5_verbs_alloc_type {
244 MLX5_VERBS_ALLOC_TYPE_NONE,
245 MLX5_VERBS_ALLOC_TYPE_TX_QUEUE,
246 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE,
249 /* VLAN netdev for VLAN workaround. */
250 struct mlx5_vlan_dev {
252 uint32_t ifindex; /**< Own interface index. */
255 /* Structure for VF VLAN workaround. */
256 struct mlx5_vf_vlan {
262 * Array of VLAN devices created on the base of VF
263 * used for workaround in virtual environments.
265 struct mlx5_vlan_vmwa_context {
269 struct rte_eth_dev *dev;
270 struct mlx5_vlan_dev vlan_dev[4096];
274 * Verbs allocator needs a context to know in the callback which kind of
275 * resources it is allocating.
277 struct mlx5_verbs_alloc_ctx {
278 enum mlx5_verbs_alloc_type type; /* Kind of object being allocated. */
279 const void *obj; /* Pointer to the DPDK object. */
282 LIST_HEAD(mlx5_mr_list, mlx5_mr);
284 /* Flow drop context necessary due to Verbs API. */
286 struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */
287 struct mlx5_rxq_obj *rxq; /* Rx queue object. */
290 #define MLX5_COUNTERS_PER_POOL 512
291 #define MLX5_MAX_PENDING_QUERIES 4
293 struct mlx5_flow_counter_pool;
295 struct flow_counter_stats {
300 /* Counters information. */
301 struct mlx5_flow_counter {
302 TAILQ_ENTRY(mlx5_flow_counter) next;
303 /**< Pointer to the next flow counter structure. */
304 uint32_t shared:1; /**< Share counter ID with other flow rules. */
306 /**< Whether the counter was allocated by batch command. */
307 uint32_t ref_cnt:30; /**< Reference counter. */
308 uint32_t id; /**< Counter ID. */
309 union { /**< Holds the counters for the rule. */
310 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42)
311 struct ibv_counter_set *cs;
312 #elif defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
313 struct ibv_counters *cs;
315 struct mlx5_devx_obj *dcs; /**< Counter Devx object. */
316 struct mlx5_flow_counter_pool *pool; /**< The counter pool. */
319 uint64_t hits; /**< Reset value of hits packets. */
320 int64_t query_gen; /**< Generation of the last release. */
322 uint64_t bytes; /**< Reset value of bytes. */
323 void *action; /**< Pointer to the dv action. */
326 TAILQ_HEAD(mlx5_counters, mlx5_flow_counter);
328 /* Counter pool structure - query is in pool resolution. */
329 struct mlx5_flow_counter_pool {
330 TAILQ_ENTRY(mlx5_flow_counter_pool) next;
331 struct mlx5_counters counters; /* Free counter list. */
333 struct mlx5_devx_obj *min_dcs;
334 rte_atomic64_t a64_dcs;
336 /* The devx object of the minimum counter ID. */
337 rte_atomic64_t query_gen;
338 uint32_t n_counters: 16; /* Number of devx allocated counters. */
339 rte_spinlock_t sl; /* The pool lock. */
340 struct mlx5_counter_stats_raw *raw;
341 struct mlx5_counter_stats_raw *raw_hw; /* The raw on HW working. */
342 struct mlx5_flow_counter counters_raw[]; /* The pool counters memory. */
345 struct mlx5_counter_stats_raw;
347 /* Memory management structure for group of counter statistics raws. */
348 struct mlx5_counter_stats_mem_mng {
349 LIST_ENTRY(mlx5_counter_stats_mem_mng) next;
350 struct mlx5_counter_stats_raw *raws;
351 struct mlx5_devx_obj *dm;
352 struct mlx5dv_devx_umem *umem;
355 /* Raw memory structure for the counter statistics values of a pool. */
356 struct mlx5_counter_stats_raw {
357 LIST_ENTRY(mlx5_counter_stats_raw) next;
359 struct mlx5_counter_stats_mem_mng *mem_mng;
360 volatile struct flow_counter_stats *data;
363 TAILQ_HEAD(mlx5_counter_pools, mlx5_flow_counter_pool);
365 /* Container structure for counter pools. */
366 struct mlx5_pools_container {
367 rte_atomic16_t n_valid; /* Number of valid pools. */
368 uint16_t n; /* Number of pools. */
369 struct mlx5_counter_pools pool_list; /* Counter pool list. */
370 struct mlx5_flow_counter_pool **pools; /* Counter pool array. */
371 struct mlx5_counter_stats_mem_mng *init_mem_mng;
372 /* Hold the memory management for the next allocated pools raws. */
375 /* Counter global management structure. */
376 struct mlx5_flow_counter_mng {
377 uint8_t mhi[2]; /* master \ host container index. */
378 struct mlx5_pools_container ccont[2 * 2];
379 /* 2 containers for single and for batch for double-buffer. */
380 struct mlx5_counters flow_counters; /* Legacy flow counter list. */
381 uint8_t pending_queries;
384 uint8_t query_thread_on;
385 LIST_HEAD(mem_mngs, mlx5_counter_stats_mem_mng) mem_mngs;
386 LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws;
389 /* Per port data of shared IB device. */
390 struct mlx5_ibv_shared_port {
392 uint32_t devx_ih_port_id;
394 * Interrupt handler port_id. Used by shared interrupt
395 * handler to find the corresponding rte_eth device
396 * by IB port index. If value is equal or greater
397 * RTE_MAX_ETHPORTS it means there is no subhandler
398 * installed for specified IB port index.
402 /* Table key of the hash organization. */
403 union mlx5_flow_tbl_key {
405 /* Table ID should be at the lowest address. */
406 uint32_t table_id; /**< ID of the table. */
407 uint16_t reserved; /**< must be zero for comparison. */
408 uint8_t domain; /**< 1 - FDB, 0 - NIC TX/RX. */
409 uint8_t direction; /**< 1 - egress, 0 - ingress. */
411 uint64_t v64; /**< full 64bits value of key */
414 /* Table structure. */
415 struct mlx5_flow_tbl_resource {
416 void *obj; /**< Pointer to DR table object. */
417 rte_atomic32_t refcnt; /**< Reference counter. */
420 #define MLX5_MAX_TABLES UINT16_MAX
421 #define MLX5_FLOW_TABLE_LEVEL_METER (UINT16_MAX - 3)
422 #define MLX5_FLOW_TABLE_LEVEL_SUFFIX (UINT16_MAX - 2)
423 #define MLX5_HAIRPIN_TX_TABLE (UINT16_MAX - 1)
424 /* Reserve the last two tables for metadata register copy. */
425 #define MLX5_FLOW_MREG_ACT_TABLE_GROUP (MLX5_MAX_TABLES - 1)
426 #define MLX5_FLOW_MREG_CP_TABLE_GROUP (MLX5_MAX_TABLES - 2)
427 /* Tables for metering splits should be added here. */
428 #define MLX5_MAX_TABLES_EXTERNAL (MLX5_MAX_TABLES - 3)
429 #define MLX5_MAX_TABLES_FDB UINT16_MAX
431 #define MLX5_DBR_PAGE_SIZE 4096 /* Must be >= 512. */
432 #define MLX5_DBR_SIZE 8
433 #define MLX5_DBR_PER_PAGE (MLX5_DBR_PAGE_SIZE / MLX5_DBR_SIZE)
434 #define MLX5_DBR_BITMAP_SIZE (MLX5_DBR_PER_PAGE / 64)
436 struct mlx5_devx_dbr_page {
437 /* Door-bell records, must be first member in structure. */
438 uint8_t dbrs[MLX5_DBR_PAGE_SIZE];
439 LIST_ENTRY(mlx5_devx_dbr_page) next; /* Pointer to the next element. */
440 struct mlx5dv_devx_umem *umem;
441 uint32_t dbr_count; /* Number of door-bell records in use. */
442 /* 1 bit marks matching door-bell is in use. */
443 uint64_t dbr_bitmap[MLX5_DBR_BITMAP_SIZE];
446 /* ID generation structure. */
447 struct mlx5_flow_id_pool {
448 uint32_t *free_arr; /**< Pointer to the a array of free values. */
450 /**< The next index that can be used without any free elements. */
451 uint32_t *curr; /**< Pointer to the index to pop. */
452 uint32_t *last; /**< Pointer to the last element in the empty arrray. */
453 uint32_t max_id; /**< Maximum id can be allocated from the pool. */
457 * Shared Infiniband device context for Master/Representors
458 * which belong to same IB device with multiple IB ports.
460 struct mlx5_ibv_shared {
461 LIST_ENTRY(mlx5_ibv_shared) next;
463 uint32_t devx:1; /* Opened with DV. */
464 uint32_t max_port; /* Maximal IB device port index. */
465 struct ibv_context *ctx; /* Verbs/DV context. */
466 struct ibv_pd *pd; /* Protection Domain. */
467 uint32_t pdn; /* Protection Domain number. */
468 uint32_t tdn; /* Transport Domain number. */
469 char ibdev_name[IBV_SYSFS_NAME_MAX]; /* IB device name. */
470 char ibdev_path[IBV_SYSFS_PATH_MAX]; /* IB device path for secondary */
471 struct ibv_device_attr_ex device_attr; /* Device properties. */
472 LIST_ENTRY(mlx5_ibv_shared) mem_event_cb;
473 /**< Called by memory event callback. */
475 uint32_t dev_gen; /* Generation number to flush local caches. */
476 rte_rwlock_t rwlock; /* MR Lock. */
477 struct mlx5_mr_btree cache; /* Global MR cache table. */
478 struct mlx5_mr_list mr_list; /* Registered MR list. */
479 struct mlx5_mr_list mr_free_list; /* Freed MR list. */
481 /* Shared DV/DR flow data section. */
482 pthread_mutex_t dv_mutex; /* DV context mutex. */
483 uint32_t dv_meta_mask; /* flow META metadata supported mask. */
484 uint32_t dv_mark_mask; /* flow MARK metadata supported mask. */
485 uint32_t dv_regc0_mask; /* available bits of metatada reg_c[0]. */
486 uint32_t dv_refcnt; /* DV/DR data reference counter. */
487 void *fdb_domain; /* FDB Direct Rules name space handle. */
488 struct mlx5_flow_tbl_resource *fdb_mtr_sfx_tbl;
489 /* FDB meter suffix rules table. */
490 void *rx_domain; /* RX Direct Rules name space handle. */
491 struct mlx5_flow_tbl_resource *rx_mtr_sfx_tbl;
492 /* RX meter suffix rules table. */
493 void *tx_domain; /* TX Direct Rules name space handle. */
494 struct mlx5_flow_tbl_resource *tx_mtr_sfx_tbl;
495 /* TX meter suffix rules table. */
496 struct mlx5_hlist *flow_tbls;
497 /* Direct Rules tables for FDB, NIC TX+RX */
498 void *esw_drop_action; /* Pointer to DR E-Switch drop action. */
499 void *pop_vlan_action; /* Pointer to DR pop VLAN action. */
500 LIST_HEAD(encap_decap, mlx5_flow_dv_encap_decap_resource) encaps_decaps;
501 LIST_HEAD(modify_cmd, mlx5_flow_dv_modify_hdr_resource) modify_cmds;
502 struct mlx5_hlist *tag_table;
503 LIST_HEAD(port_id_action_list, mlx5_flow_dv_port_id_action_resource)
504 port_id_action_list; /* List of port ID actions. */
505 LIST_HEAD(push_vlan_action_list, mlx5_flow_dv_push_vlan_action_resource)
506 push_vlan_action_list; /* List of push VLAN actions. */
507 struct mlx5_flow_counter_mng cmng; /* Counters management structure. */
508 /* Shared interrupt handler section. */
509 pthread_mutex_t intr_mutex; /* Interrupt config mutex. */
510 uint32_t intr_cnt; /* Interrupt handler reference counter. */
511 struct rte_intr_handle intr_handle; /* Interrupt handler for device. */
512 uint32_t devx_intr_cnt; /* Devx interrupt handler reference counter. */
513 struct rte_intr_handle intr_handle_devx; /* DEVX interrupt handler. */
514 struct mlx5dv_devx_cmd_comp *devx_comp; /* DEVX async comp obj. */
515 struct mlx5_devx_obj *tis; /* TIS object. */
516 struct mlx5_devx_obj *td; /* Transport domain. */
517 struct mlx5_flow_id_pool *flow_id_pool; /* Flow ID pool. */
518 struct mlx5_ibv_shared_port port[]; /* per device port data array. */
521 /* Per-process private structure. */
522 struct mlx5_proc_priv {
524 /* Size of UAR register table. */
526 /* Table of UAR registers for each process. */
529 /* MTR profile list. */
530 TAILQ_HEAD(mlx5_mtr_profiles, mlx5_flow_meter_profile);
532 TAILQ_HEAD(mlx5_flow_meters, mlx5_flow_meter);
534 #define MLX5_PROC_PRIV(port_id) \
535 ((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private)
538 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */
539 struct mlx5_ibv_shared *sh; /* Shared IB device context. */
540 uint32_t ibv_port; /* IB device port number. */
541 struct rte_pci_device *pci_dev; /* Backend PCI device. */
542 struct rte_ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */
543 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES);
544 /* Bit-field of MAC addresses owned by the PMD. */
545 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */
546 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */
547 /* Device properties. */
548 uint16_t mtu; /* Configured MTU. */
549 unsigned int isolated:1; /* Whether isolated mode is enabled. */
550 unsigned int representor:1; /* Device is a port representor. */
551 unsigned int master:1; /* Device is a E-Switch master. */
552 unsigned int dr_shared:1; /* DV/DR data is shared. */
553 unsigned int counter_fallback:1; /* Use counter fallback management. */
554 unsigned int mtr_en:1; /* Whether support meter. */
555 unsigned int mtr_reg_share:1; /* Whether support meter REG_C share. */
556 uint16_t domain_id; /* Switch domain identifier. */
557 uint16_t vport_id; /* Associated VF vport index (if any). */
558 uint32_t vport_meta_tag; /* Used for vport index match ove VF LAG. */
559 uint32_t vport_meta_mask; /* Used for vport index field match mask. */
560 int32_t representor_id; /* Port representor identifier. */
561 int32_t pf_bond; /* >=0 means PF index in bonding configuration. */
562 unsigned int if_index; /* Associated kernel network device index. */
564 unsigned int rxqs_n; /* RX queues array size. */
565 unsigned int txqs_n; /* TX queues array size. */
566 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */
567 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */
568 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
569 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */
570 unsigned int (*reta_idx)[]; /* RETA index table. */
571 unsigned int reta_idx_n; /* RETA index size. */
572 struct mlx5_drop drop_queue; /* Flow drop queues. */
573 struct mlx5_flows flows; /* RTE Flow rules. */
574 struct mlx5_flows ctrl_flows; /* Control flow rules. */
575 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */
576 LIST_HEAD(rxqobj, mlx5_rxq_obj) rxqsobj; /* Verbs/DevX Rx queues. */
577 LIST_HEAD(hrxq, mlx5_hrxq) hrxqs; /* Verbs Hash Rx queues. */
578 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */
579 LIST_HEAD(txqobj, mlx5_txq_obj) txqsobj; /* Verbs/DevX Tx queues. */
580 /* Indirection tables. */
581 LIST_HEAD(ind_tables, mlx5_ind_table_obj) ind_tbls;
582 /* Pointer to next element. */
583 rte_atomic32_t refcnt; /**< Reference counter. */
584 struct ibv_flow_action *verbs_action;
585 /**< Verbs modify header action object. */
586 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
587 uint8_t max_lro_msg_size;
588 /* Tags resources cache. */
589 uint32_t link_speed_capa; /* Link speed capabilities. */
590 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */
591 struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */
592 struct mlx5_dev_config config; /* Device configuration. */
593 struct mlx5_verbs_alloc_ctx verbs_alloc_ctx;
594 /* Context for Verbs allocator. */
595 int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */
596 int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */
597 uint32_t nl_sn; /* Netlink message sequence number. */
598 LIST_HEAD(dbrpage, mlx5_devx_dbr_page) dbrpgs; /* Door-bell pages. */
599 struct mlx5_vlan_vmwa_context *vmwa_context; /* VLAN WA context. */
600 struct mlx5_flow_id_pool *qrss_id_pool;
601 struct mlx5_hlist *mreg_cp_tbl;
602 /* Hash table of Rx metadata register copy table. */
603 uint8_t mtr_sfx_reg; /* Meter prefix-suffix flow match REG_C. */
604 uint8_t mtr_color_reg; /* Meter color match REG_C. */
605 struct mlx5_mtr_profiles flow_meter_profiles; /* MTR profile list. */
606 struct mlx5_flow_meters flow_meters; /* MTR list. */
608 rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */
609 rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX];
610 /* UAR same-page access control required in 32bit implementations. */
612 uint8_t skip_default_rss_reta; /* Skip configuration of default reta. */
615 #define PORT_ID(priv) ((priv)->dev_data->port_id)
616 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)])
620 int mlx5_getenv_int(const char *);
621 int mlx5_proc_priv_init(struct rte_eth_dev *dev);
622 int64_t mlx5_get_dbr(struct rte_eth_dev *dev,
623 struct mlx5_devx_dbr_page **dbr_page);
624 int32_t mlx5_release_dbr(struct rte_eth_dev *dev, uint32_t umem_id,
626 int mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev,
627 struct rte_eth_udp_tunnel *udp_tunnel);
628 uint16_t mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev);
630 /* Macro to iterate over all valid ports for mlx5 driver. */
631 #define MLX5_ETH_FOREACH_DEV(port_id, pci_dev) \
632 for (port_id = mlx5_eth_find_next(0, pci_dev); \
633 port_id < RTE_MAX_ETHPORTS; \
634 port_id = mlx5_eth_find_next(port_id + 1, pci_dev))
638 int mlx5_get_ifname(const struct rte_eth_dev *dev, char (*ifname)[IF_NAMESIZE]);
639 int mlx5_get_master_ifname(const char *ibdev_path, char (*ifname)[IF_NAMESIZE]);
640 unsigned int mlx5_ifindex(const struct rte_eth_dev *dev);
641 int mlx5_ifreq(const struct rte_eth_dev *dev, int req, struct ifreq *ifr);
642 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu);
643 int mlx5_set_flags(struct rte_eth_dev *dev, unsigned int keep,
645 int mlx5_dev_configure(struct rte_eth_dev *dev);
646 int mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info);
647 int mlx5_read_clock(struct rte_eth_dev *dev, uint64_t *clock);
648 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size);
649 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev);
650 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete);
651 int mlx5_force_link_status_change(struct rte_eth_dev *dev, int status);
652 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
653 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev,
654 struct rte_eth_fc_conf *fc_conf);
655 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev,
656 struct rte_eth_fc_conf *fc_conf);
657 int mlx5_dev_to_pci_addr(const char *dev_path,
658 struct rte_pci_addr *pci_addr);
659 void mlx5_dev_link_status_handler(void *arg);
660 void mlx5_dev_interrupt_handler(void *arg);
661 void mlx5_dev_interrupt_handler_devx(void *arg);
662 void mlx5_dev_interrupt_handler_uninstall(struct rte_eth_dev *dev);
663 void mlx5_dev_interrupt_handler_install(struct rte_eth_dev *dev);
664 void mlx5_dev_interrupt_handler_devx_uninstall(struct rte_eth_dev *dev);
665 void mlx5_dev_interrupt_handler_devx_install(struct rte_eth_dev *dev);
666 int mlx5_set_link_down(struct rte_eth_dev *dev);
667 int mlx5_set_link_up(struct rte_eth_dev *dev);
668 int mlx5_is_removed(struct rte_eth_dev *dev);
669 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev);
670 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev);
671 struct mlx5_priv *mlx5_port_to_eswitch_info(uint16_t port, bool valid);
672 struct mlx5_priv *mlx5_dev_to_eswitch_info(struct rte_eth_dev *dev);
673 int mlx5_sysfs_switch_info(unsigned int ifindex,
674 struct mlx5_switch_info *info);
675 void mlx5_sysfs_check_switch_info(bool device_dir,
676 struct mlx5_switch_info *switch_info);
677 void mlx5_nl_check_switch_info(bool nun_vf_set,
678 struct mlx5_switch_info *switch_info);
679 void mlx5_translate_port_name(const char *port_name_in,
680 struct mlx5_switch_info *port_info_out);
681 void mlx5_intr_callback_unregister(const struct rte_intr_handle *handle,
682 rte_intr_callback_fn cb_fn, void *cb_arg);
683 int mlx5_get_module_info(struct rte_eth_dev *dev,
684 struct rte_eth_dev_module_info *modinfo);
685 int mlx5_get_module_eeprom(struct rte_eth_dev *dev,
686 struct rte_dev_eeprom_info *info);
687 int mlx5_hairpin_cap_get(struct rte_eth_dev *dev,
688 struct rte_eth_hairpin_cap *cap);
689 int mlx5_dev_configure_rss_reta(struct rte_eth_dev *dev);
693 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]);
694 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
695 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
696 uint32_t index, uint32_t vmdq);
697 int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr);
698 int mlx5_set_mc_addr_list(struct rte_eth_dev *dev,
699 struct rte_ether_addr *mc_addr_set,
700 uint32_t nb_mc_addr);
704 int mlx5_rss_hash_update(struct rte_eth_dev *dev,
705 struct rte_eth_rss_conf *rss_conf);
706 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev,
707 struct rte_eth_rss_conf *rss_conf);
708 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size);
709 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev,
710 struct rte_eth_rss_reta_entry64 *reta_conf,
712 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev,
713 struct rte_eth_rss_reta_entry64 *reta_conf,
718 int mlx5_promiscuous_enable(struct rte_eth_dev *dev);
719 int mlx5_promiscuous_disable(struct rte_eth_dev *dev);
720 int mlx5_allmulticast_enable(struct rte_eth_dev *dev);
721 int mlx5_allmulticast_disable(struct rte_eth_dev *dev);
725 void mlx5_stats_init(struct rte_eth_dev *dev);
726 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
727 int mlx5_stats_reset(struct rte_eth_dev *dev);
728 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats,
730 int mlx5_xstats_reset(struct rte_eth_dev *dev);
731 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
732 struct rte_eth_xstat_name *xstats_names,
737 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
738 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on);
739 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask);
743 int mlx5_dev_start(struct rte_eth_dev *dev);
744 void mlx5_dev_stop(struct rte_eth_dev *dev);
745 int mlx5_traffic_enable(struct rte_eth_dev *dev);
746 void mlx5_traffic_disable(struct rte_eth_dev *dev);
747 int mlx5_traffic_restart(struct rte_eth_dev *dev);
751 int mlx5_flow_discover_mreg_c(struct rte_eth_dev *eth_dev);
752 bool mlx5_flow_ext_mreg_supported(struct rte_eth_dev *dev);
753 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
754 void mlx5_flow_print(struct rte_flow *flow);
755 int mlx5_flow_validate(struct rte_eth_dev *dev,
756 const struct rte_flow_attr *attr,
757 const struct rte_flow_item items[],
758 const struct rte_flow_action actions[],
759 struct rte_flow_error *error);
760 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev,
761 const struct rte_flow_attr *attr,
762 const struct rte_flow_item items[],
763 const struct rte_flow_action actions[],
764 struct rte_flow_error *error);
765 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow,
766 struct rte_flow_error *error);
767 void mlx5_flow_list_flush(struct rte_eth_dev *dev, struct mlx5_flows *list);
768 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error);
769 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow,
770 const struct rte_flow_action *action, void *data,
771 struct rte_flow_error *error);
772 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable,
773 struct rte_flow_error *error);
774 int mlx5_dev_filter_ctrl(struct rte_eth_dev *dev,
775 enum rte_filter_type filter_type,
776 enum rte_filter_op filter_op,
778 int mlx5_flow_start(struct rte_eth_dev *dev, struct mlx5_flows *list);
779 void mlx5_flow_stop(struct rte_eth_dev *dev, struct mlx5_flows *list);
780 int mlx5_flow_verify(struct rte_eth_dev *dev);
781 int mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, uint32_t queue);
782 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev,
783 struct rte_flow_item_eth *eth_spec,
784 struct rte_flow_item_eth *eth_mask,
785 struct rte_flow_item_vlan *vlan_spec,
786 struct rte_flow_item_vlan *vlan_mask);
787 int mlx5_ctrl_flow(struct rte_eth_dev *dev,
788 struct rte_flow_item_eth *eth_spec,
789 struct rte_flow_item_eth *eth_mask);
790 struct rte_flow *mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev);
791 int mlx5_flow_create_drop_queue(struct rte_eth_dev *dev);
792 void mlx5_flow_delete_drop_queue(struct rte_eth_dev *dev);
793 void mlx5_flow_async_pool_query_handle(struct mlx5_ibv_shared *sh,
794 uint64_t async_id, int status);
795 void mlx5_set_query_alarm(struct mlx5_ibv_shared *sh);
796 void mlx5_flow_query_alarm(void *arg);
797 struct mlx5_flow_counter *mlx5_counter_alloc(struct rte_eth_dev *dev);
798 void mlx5_counter_free(struct rte_eth_dev *dev, struct mlx5_flow_counter *cnt);
799 int mlx5_counter_query(struct rte_eth_dev *dev, struct mlx5_flow_counter *cnt,
800 bool clear, uint64_t *pkts, uint64_t *bytes);
801 int mlx5_flow_dev_dump(struct rte_eth_dev *dev, FILE *file,
802 struct rte_flow_error *error);
805 void mlx5_mp_req_start_rxtx(struct rte_eth_dev *dev);
806 void mlx5_mp_req_stop_rxtx(struct rte_eth_dev *dev);
807 int mlx5_mp_req_mr_create(struct rte_eth_dev *dev, uintptr_t addr);
808 int mlx5_mp_req_verbs_cmd_fd(struct rte_eth_dev *dev);
809 int mlx5_mp_req_queue_state_modify(struct rte_eth_dev *dev,
810 struct mlx5_mp_arg_queue_state_modify *sm);
811 int mlx5_mp_init_primary(void);
812 void mlx5_mp_uninit_primary(void);
813 int mlx5_mp_init_secondary(void);
814 void mlx5_mp_uninit_secondary(void);
818 int mlx5_pmd_socket_init(void);
819 void mlx5_pmd_socket_uninit(void);
823 int mlx5_nl_init(int protocol);
824 int mlx5_nl_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
826 int mlx5_nl_mac_addr_remove(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
828 void mlx5_nl_mac_addr_sync(struct rte_eth_dev *dev);
829 void mlx5_nl_mac_addr_flush(struct rte_eth_dev *dev);
830 int mlx5_nl_promisc(struct rte_eth_dev *dev, int enable);
831 int mlx5_nl_allmulti(struct rte_eth_dev *dev, int enable);
832 unsigned int mlx5_nl_portnum(int nl, const char *name);
833 unsigned int mlx5_nl_ifindex(int nl, const char *name, uint32_t pindex);
834 int mlx5_nl_vf_mac_addr_modify(struct rte_eth_dev *dev,
835 struct rte_ether_addr *mac, int vf_index);
836 int mlx5_nl_switch_info(int nl, unsigned int ifindex,
837 struct mlx5_switch_info *info);
839 struct mlx5_vlan_vmwa_context *mlx5_vlan_vmwa_init(struct rte_eth_dev *dev,
841 void mlx5_vlan_vmwa_exit(struct mlx5_vlan_vmwa_context *ctx);
842 void mlx5_vlan_vmwa_release(struct rte_eth_dev *dev,
843 struct mlx5_vf_vlan *vf_vlan);
844 void mlx5_vlan_vmwa_acquire(struct rte_eth_dev *dev,
845 struct mlx5_vf_vlan *vf_vlan);
847 /* mlx5_flow_meter.c */
849 int mlx5_flow_meter_ops_get(struct rte_eth_dev *dev, void *arg);
850 struct mlx5_flow_meter *mlx5_flow_meter_find(struct mlx5_priv *priv,
852 struct mlx5_flow_meter *mlx5_flow_meter_attach
853 (struct mlx5_priv *priv,
855 const struct rte_flow_attr *attr,
856 struct rte_flow_error *error);
857 void mlx5_flow_meter_detach(struct mlx5_flow_meter *fm);
859 #endif /* RTE_PMD_MLX5_H_ */