1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_H_
7 #define RTE_PMD_MLX5_H_
14 #include <netinet/in.h>
15 #include <sys/queue.h>
18 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
20 #pragma GCC diagnostic ignored "-Wpedantic"
22 #include <infiniband/verbs.h>
24 #pragma GCC diagnostic error "-Wpedantic"
28 #include <rte_ether.h>
29 #include <rte_ethdev_driver.h>
30 #include <rte_rwlock.h>
31 #include <rte_interrupts.h>
32 #include <rte_errno.h>
35 #include <mlx5_glue.h>
36 #include <mlx5_devx_cmds.h>
39 #include <mlx5_common_mp.h>
40 #include <mlx5_common_mr.h>
42 #include "mlx5_defs.h"
43 #include "mlx5_utils.h"
44 #include "mlx5_autoconf.h"
47 enum mlx5_ipool_index {
48 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
49 MLX5_IPOOL_DECAP_ENCAP = 0, /* Pool for encap/decap resource. */
50 MLX5_IPOOL_PUSH_VLAN, /* Pool for push vlan resource. */
51 MLX5_IPOOL_TAG, /* Pool for tag resource. */
52 MLX5_IPOOL_PORT_ID, /* Pool for port id resource. */
53 MLX5_IPOOL_JUMP, /* Pool for jump resource. */
55 MLX5_IPOOL_MTR, /* Pool for meter resource. */
56 MLX5_IPOOL_MCP, /* Pool for metadata resource. */
57 MLX5_IPOOL_HRXQ, /* Pool for hrxq resource. */
58 MLX5_IPOOL_MLX5_FLOW, /* Pool for mlx5 flow handle. */
59 MLX5_IPOOL_RTE_FLOW, /* Pool for rte_flow. */
63 /** Key string for IPC. */
64 #define MLX5_MP_NAME "net_mlx5_mp"
67 LIST_HEAD(mlx5_dev_list, mlx5_ibv_shared);
69 /* Shared data between primary and secondary processes. */
70 struct mlx5_shared_data {
72 /* Global spinlock for primary and secondary processes. */
73 int init_done; /* Whether primary has done initialization. */
74 unsigned int secondary_cnt; /* Number of secondary processes init'd. */
75 struct mlx5_dev_list mem_event_cb_list;
76 rte_rwlock_t mem_event_rwlock;
79 /* Per-process data structure, not visible to other processes. */
80 struct mlx5_local_data {
81 int init_done; /* Whether a secondary has done initialization. */
84 extern struct mlx5_shared_data *mlx5_shared_data;
86 struct mlx5_counter_ctrl {
87 /* Name of the counter. */
88 char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE];
89 /* Name of the counter on the device table. */
90 char ctr_name[RTE_ETH_XSTATS_NAME_SIZE];
91 uint32_t ib:1; /**< Nonzero for IB counters. */
94 struct mlx5_xstats_ctrl {
95 /* Number of device stats. */
97 /* Number of device stats identified by PMD. */
98 uint16_t mlx5_stats_n;
99 /* Index in the device counters table. */
100 uint16_t dev_table_idx[MLX5_MAX_XSTATS];
101 uint64_t base[MLX5_MAX_XSTATS];
102 uint64_t xstats[MLX5_MAX_XSTATS];
103 uint64_t hw_stats[MLX5_MAX_XSTATS];
104 struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS];
107 struct mlx5_stats_ctrl {
108 /* Base for imissed counter. */
109 uint64_t imissed_base;
113 /* Default PMD specific parameter value. */
114 #define MLX5_ARG_UNSET (-1)
116 #define MLX5_LRO_SUPPORTED(dev) \
117 (((struct mlx5_priv *)((dev)->data->dev_private))->config.lro.supported)
119 /* Maximal size of coalesced segment for LRO is set in chunks of 256 Bytes. */
120 #define MLX5_LRO_SEG_CHUNK_SIZE 256u
122 /* Maximal size of aggregated LRO packet. */
123 #define MLX5_MAX_LRO_SIZE (UINT8_MAX * MLX5_LRO_SEG_CHUNK_SIZE)
125 /* LRO configurations structure. */
126 struct mlx5_lro_config {
127 uint32_t supported:1; /* Whether LRO is supported. */
128 uint32_t timeout; /* User configuration. */
132 * Device configuration structure.
134 * Merged configuration from:
136 * - Device capabilities,
137 * - User device parameters disabled features.
139 struct mlx5_dev_config {
140 unsigned int hw_csum:1; /* Checksum offload is supported. */
141 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */
142 unsigned int hw_vlan_insert:1; /* VLAN insertion in WQE is supported. */
143 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */
144 unsigned int hw_padding:1; /* End alignment padding is supported. */
145 unsigned int vf:1; /* This is a VF. */
146 unsigned int tunnel_en:1;
147 /* Whether tunnel stateless offloads are supported. */
148 unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */
149 unsigned int cqe_comp:1; /* CQE compression is enabled. */
150 unsigned int cqe_pad:1; /* CQE padding is enabled. */
151 unsigned int tso:1; /* Whether TSO is supported. */
152 unsigned int rx_vec_en:1; /* Rx vector is enabled. */
153 unsigned int mr_ext_memseg_en:1;
154 /* Whether memseg should be extended for MR creation. */
155 unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */
156 unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */
157 unsigned int dv_esw_en:1; /* Enable E-Switch DV flow. */
158 unsigned int dv_flow_en:1; /* Enable DV flow. */
159 unsigned int dv_xmeta_en:2; /* Enable extensive flow metadata. */
160 unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */
161 unsigned int devx:1; /* Whether devx interface is available or not. */
162 unsigned int dest_tir:1; /* Whether advanced DR API is available. */
164 unsigned int enabled:1; /* Whether MPRQ is enabled. */
165 unsigned int stride_num_n; /* Number of strides. */
166 unsigned int stride_size_n; /* Size of a stride. */
167 unsigned int min_stride_size_n; /* Min size of a stride. */
168 unsigned int max_stride_size_n; /* Max size of a stride. */
169 unsigned int max_memcpy_len;
170 /* Maximum packet size to memcpy Rx packets. */
171 unsigned int min_rxqs_num;
172 /* Rx queue count threshold to enable MPRQ. */
173 } mprq; /* Configurations for Multi-Packet RQ. */
174 int mps; /* Multi-packet send supported mode. */
175 int dbnc; /* Skip doorbell register write barrier. */
176 unsigned int flow_prio; /* Number of flow priorities. */
177 enum modify_reg flow_mreg_c[MLX5_MREG_C_NUM];
178 /* Availibility of mreg_c's. */
179 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */
180 unsigned int ind_table_max_size; /* Maximum indirection table size. */
181 unsigned int max_dump_files_num; /* Maximum dump files per queue. */
182 unsigned int log_hp_size; /* Single hairpin queue data size in total. */
183 int txqs_inline; /* Queue number threshold for inlining. */
184 int txq_inline_min; /* Minimal amount of data bytes to inline. */
185 int txq_inline_max; /* Max packet size for inlining with SEND. */
186 int txq_inline_mpw; /* Max packet size for inlining with eMPW. */
187 struct mlx5_hca_attr hca_attr; /* HCA attributes. */
188 struct mlx5_lro_config lro; /* LRO configuration. */
193 * Type of object being allocated.
195 enum mlx5_verbs_alloc_type {
196 MLX5_VERBS_ALLOC_TYPE_NONE,
197 MLX5_VERBS_ALLOC_TYPE_TX_QUEUE,
198 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE,
201 /* Structure for VF VLAN workaround. */
202 struct mlx5_vf_vlan {
208 * Verbs allocator needs a context to know in the callback which kind of
209 * resources it is allocating.
211 struct mlx5_verbs_alloc_ctx {
212 enum mlx5_verbs_alloc_type type; /* Kind of object being allocated. */
213 const void *obj; /* Pointer to the DPDK object. */
216 /* Flow drop context necessary due to Verbs API. */
218 struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */
219 struct mlx5_rxq_obj *rxq; /* Rx queue object. */
222 #define MLX5_COUNTERS_PER_POOL 512
223 #define MLX5_MAX_PENDING_QUERIES 4
224 #define MLX5_CNT_CONTAINER_RESIZE 64
225 #define CNT_SIZE (sizeof(struct mlx5_flow_counter))
226 #define CNTEXT_SIZE (sizeof(struct mlx5_flow_counter_ext))
228 #define CNT_POOL_TYPE_EXT (1 << 0)
229 #define IS_EXT_POOL(pool) (((pool)->type) & CNT_POOL_TYPE_EXT)
230 #define MLX5_CNT_LEN(pool) \
231 (CNT_SIZE + (IS_EXT_POOL(pool) ? CNTEXT_SIZE : 0))
232 #define MLX5_POOL_GET_CNT(pool, index) \
233 ((struct mlx5_flow_counter *) \
234 ((uint8_t *)((pool) + 1) + (index) * (MLX5_CNT_LEN(pool))))
235 #define MLX5_CNT_ARRAY_IDX(pool, cnt) \
236 ((int)(((uint8_t *)(cnt) - (uint8_t *)((pool) + 1)) / \
239 * The pool index and offset of counter in the pool array makes up the
240 * counter index. In case the counter is from pool 0 and offset 0, it
241 * should plus 1 to avoid index 0, since 0 means invalid counter index
244 #define MLX5_MAKE_CNT_IDX(pi, offset) \
245 ((pi) * MLX5_COUNTERS_PER_POOL + (offset) + 1)
246 #define MLX5_CNT_TO_CNT_EXT(cnt) \
247 ((struct mlx5_flow_counter_ext *)((cnt) + 1))
248 #define MLX5_GET_POOL_CNT_EXT(pool, offset) \
249 MLX5_CNT_TO_CNT_EXT(MLX5_POOL_GET_CNT((pool), (offset)))
251 struct mlx5_flow_counter_pool;
253 struct flow_counter_stats {
258 /* Generic counters information. */
259 struct mlx5_flow_counter {
260 TAILQ_ENTRY(mlx5_flow_counter) next;
261 /**< Pointer to the next flow counter structure. */
263 uint64_t hits; /**< Reset value of hits packets. */
264 int64_t query_gen; /**< Generation of the last release. */
266 uint64_t bytes; /**< Reset value of bytes. */
267 void *action; /**< Pointer to the dv action. */
270 /* Extend counters information for none batch counters. */
271 struct mlx5_flow_counter_ext {
272 uint32_t shared:1; /**< Share counter ID with other flow rules. */
274 /**< Whether the counter was allocated by batch command. */
275 uint32_t ref_cnt:30; /**< Reference counter. */
276 uint32_t id; /**< User counter ID. */
277 union { /**< Holds the counters for the rule. */
278 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42)
279 struct ibv_counter_set *cs;
280 #elif defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
281 struct ibv_counters *cs;
283 struct mlx5_devx_obj *dcs; /**< Counter Devx object. */
288 TAILQ_HEAD(mlx5_counters, mlx5_flow_counter);
290 /* Generic counter pool structure - query is in pool resolution. */
291 struct mlx5_flow_counter_pool {
292 TAILQ_ENTRY(mlx5_flow_counter_pool) next;
293 struct mlx5_counters counters; /* Free counter list. */
295 struct mlx5_devx_obj *min_dcs;
296 rte_atomic64_t a64_dcs;
298 /* The devx object of the minimum counter ID. */
299 rte_atomic64_t start_query_gen; /* Query start round. */
300 rte_atomic64_t end_query_gen; /* Query end round. */
301 uint32_t index; /* Pool index in container. */
302 uint32_t type: 2; /* Memory type behind the counter array. */
303 rte_spinlock_t sl; /* The pool lock. */
304 struct mlx5_counter_stats_raw *raw;
305 struct mlx5_counter_stats_raw *raw_hw; /* The raw on HW working. */
308 struct mlx5_counter_stats_raw;
310 /* Memory management structure for group of counter statistics raws. */
311 struct mlx5_counter_stats_mem_mng {
312 LIST_ENTRY(mlx5_counter_stats_mem_mng) next;
313 struct mlx5_counter_stats_raw *raws;
314 struct mlx5_devx_obj *dm;
315 struct mlx5dv_devx_umem *umem;
318 /* Raw memory structure for the counter statistics values of a pool. */
319 struct mlx5_counter_stats_raw {
320 LIST_ENTRY(mlx5_counter_stats_raw) next;
322 struct mlx5_counter_stats_mem_mng *mem_mng;
323 volatile struct flow_counter_stats *data;
326 TAILQ_HEAD(mlx5_counter_pools, mlx5_flow_counter_pool);
328 /* Container structure for counter pools. */
329 struct mlx5_pools_container {
330 rte_atomic16_t n_valid; /* Number of valid pools. */
331 uint16_t n; /* Number of pools. */
332 struct mlx5_counter_pools pool_list; /* Counter pool list. */
333 struct mlx5_flow_counter_pool **pools; /* Counter pool array. */
334 struct mlx5_counter_stats_mem_mng *init_mem_mng;
335 /* Hold the memory management for the next allocated pools raws. */
338 /* Counter global management structure. */
339 struct mlx5_flow_counter_mng {
340 uint8_t mhi[2]; /* master \ host container index. */
341 struct mlx5_pools_container ccont[2 * 2];
342 /* 2 containers for single and for batch for double-buffer. */
343 struct mlx5_counters flow_counters; /* Legacy flow counter list. */
344 uint8_t pending_queries;
347 uint8_t query_thread_on;
348 LIST_HEAD(mem_mngs, mlx5_counter_stats_mem_mng) mem_mngs;
349 LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws;
352 /* Per port data of shared IB device. */
353 struct mlx5_ibv_shared_port {
355 uint32_t devx_ih_port_id;
357 * Interrupt handler port_id. Used by shared interrupt
358 * handler to find the corresponding rte_eth device
359 * by IB port index. If value is equal or greater
360 * RTE_MAX_ETHPORTS it means there is no subhandler
361 * installed for specified IB port index.
365 /* Table key of the hash organization. */
366 union mlx5_flow_tbl_key {
368 /* Table ID should be at the lowest address. */
369 uint32_t table_id; /**< ID of the table. */
370 uint16_t reserved; /**< must be zero for comparison. */
371 uint8_t domain; /**< 1 - FDB, 0 - NIC TX/RX. */
372 uint8_t direction; /**< 1 - egress, 0 - ingress. */
374 uint64_t v64; /**< full 64bits value of key */
377 /* Table structure. */
378 struct mlx5_flow_tbl_resource {
379 void *obj; /**< Pointer to DR table object. */
380 rte_atomic32_t refcnt; /**< Reference counter. */
383 #define MLX5_MAX_TABLES UINT16_MAX
384 #define MLX5_FLOW_TABLE_LEVEL_METER (UINT16_MAX - 3)
385 #define MLX5_FLOW_TABLE_LEVEL_SUFFIX (UINT16_MAX - 2)
386 #define MLX5_HAIRPIN_TX_TABLE (UINT16_MAX - 1)
387 /* Reserve the last two tables for metadata register copy. */
388 #define MLX5_FLOW_MREG_ACT_TABLE_GROUP (MLX5_MAX_TABLES - 1)
389 #define MLX5_FLOW_MREG_CP_TABLE_GROUP (MLX5_MAX_TABLES - 2)
390 /* Tables for metering splits should be added here. */
391 #define MLX5_MAX_TABLES_EXTERNAL (MLX5_MAX_TABLES - 3)
392 #define MLX5_MAX_TABLES_FDB UINT16_MAX
394 #define MLX5_DBR_PAGE_SIZE 4096 /* Must be >= 512. */
395 #define MLX5_DBR_SIZE 8
396 #define MLX5_DBR_PER_PAGE (MLX5_DBR_PAGE_SIZE / MLX5_DBR_SIZE)
397 #define MLX5_DBR_BITMAP_SIZE (MLX5_DBR_PER_PAGE / 64)
399 struct mlx5_devx_dbr_page {
400 /* Door-bell records, must be first member in structure. */
401 uint8_t dbrs[MLX5_DBR_PAGE_SIZE];
402 LIST_ENTRY(mlx5_devx_dbr_page) next; /* Pointer to the next element. */
403 struct mlx5dv_devx_umem *umem;
404 uint32_t dbr_count; /* Number of door-bell records in use. */
405 /* 1 bit marks matching door-bell is in use. */
406 uint64_t dbr_bitmap[MLX5_DBR_BITMAP_SIZE];
409 /* ID generation structure. */
410 struct mlx5_flow_id_pool {
411 uint32_t *free_arr; /**< Pointer to the a array of free values. */
413 /**< The next index that can be used without any free elements. */
414 uint32_t *curr; /**< Pointer to the index to pop. */
415 uint32_t *last; /**< Pointer to the last element in the empty arrray. */
416 uint32_t max_id; /**< Maximum id can be allocated from the pool. */
420 * Shared Infiniband device context for Master/Representors
421 * which belong to same IB device with multiple IB ports.
423 struct mlx5_ibv_shared {
424 LIST_ENTRY(mlx5_ibv_shared) next;
426 uint32_t devx:1; /* Opened with DV. */
427 uint32_t max_port; /* Maximal IB device port index. */
428 struct ibv_context *ctx; /* Verbs/DV context. */
429 struct ibv_pd *pd; /* Protection Domain. */
430 uint32_t pdn; /* Protection Domain number. */
431 uint32_t tdn; /* Transport Domain number. */
432 char ibdev_name[IBV_SYSFS_NAME_MAX]; /* IB device name. */
433 char ibdev_path[IBV_SYSFS_PATH_MAX]; /* IB device path for secondary */
434 struct ibv_device_attr_ex device_attr; /* Device properties. */
435 LIST_ENTRY(mlx5_ibv_shared) mem_event_cb;
436 /**< Called by memory event callback. */
437 struct mlx5_mr_share_cache share_cache;
438 /* Shared DV/DR flow data section. */
439 pthread_mutex_t dv_mutex; /* DV context mutex. */
440 uint32_t dv_meta_mask; /* flow META metadata supported mask. */
441 uint32_t dv_mark_mask; /* flow MARK metadata supported mask. */
442 uint32_t dv_regc0_mask; /* available bits of metatada reg_c[0]. */
443 uint32_t dv_refcnt; /* DV/DR data reference counter. */
444 void *fdb_domain; /* FDB Direct Rules name space handle. */
445 void *rx_domain; /* RX Direct Rules name space handle. */
446 void *tx_domain; /* TX Direct Rules name space handle. */
447 struct mlx5_hlist *flow_tbls;
448 /* Direct Rules tables for FDB, NIC TX+RX */
449 void *esw_drop_action; /* Pointer to DR E-Switch drop action. */
450 void *pop_vlan_action; /* Pointer to DR pop VLAN action. */
451 uint32_t encaps_decaps; /* Encap/decap action indexed memory list. */
452 LIST_HEAD(modify_cmd, mlx5_flow_dv_modify_hdr_resource) modify_cmds;
453 struct mlx5_hlist *tag_table;
454 uint32_t port_id_action_list; /* List of port ID actions. */
455 uint32_t push_vlan_action_list; /* List of push VLAN actions. */
456 struct mlx5_flow_counter_mng cmng; /* Counters management structure. */
457 struct mlx5_indexed_pool *ipool[MLX5_IPOOL_MAX];
458 /* Memory Pool for mlx5 flow resources. */
459 /* Shared interrupt handler section. */
460 pthread_mutex_t intr_mutex; /* Interrupt config mutex. */
461 uint32_t intr_cnt; /* Interrupt handler reference counter. */
462 struct rte_intr_handle intr_handle; /* Interrupt handler for device. */
463 uint32_t devx_intr_cnt; /* Devx interrupt handler reference counter. */
464 struct rte_intr_handle intr_handle_devx; /* DEVX interrupt handler. */
465 struct mlx5dv_devx_cmd_comp *devx_comp; /* DEVX async comp obj. */
466 struct mlx5_devx_obj *tis; /* TIS object. */
467 struct mlx5_devx_obj *td; /* Transport domain. */
468 struct mlx5_flow_id_pool *flow_id_pool; /* Flow ID pool. */
469 struct mlx5_ibv_shared_port port[]; /* per device port data array. */
472 /* Per-process private structure. */
473 struct mlx5_proc_priv {
475 /* Size of UAR register table. */
477 /* Table of UAR registers for each process. */
480 /* MTR profile list. */
481 TAILQ_HEAD(mlx5_mtr_profiles, mlx5_flow_meter_profile);
483 TAILQ_HEAD(mlx5_flow_meters, mlx5_flow_meter);
485 #define MLX5_PROC_PRIV(port_id) \
486 ((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private)
489 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */
490 struct mlx5_ibv_shared *sh; /* Shared IB device context. */
491 uint32_t ibv_port; /* IB device port number. */
492 struct rte_pci_device *pci_dev; /* Backend PCI device. */
493 struct rte_ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */
494 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES);
495 /* Bit-field of MAC addresses owned by the PMD. */
496 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */
497 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */
498 /* Device properties. */
499 uint16_t mtu; /* Configured MTU. */
500 unsigned int isolated:1; /* Whether isolated mode is enabled. */
501 unsigned int representor:1; /* Device is a port representor. */
502 unsigned int master:1; /* Device is a E-Switch master. */
503 unsigned int dr_shared:1; /* DV/DR data is shared. */
504 unsigned int counter_fallback:1; /* Use counter fallback management. */
505 unsigned int mtr_en:1; /* Whether support meter. */
506 unsigned int mtr_reg_share:1; /* Whether support meter REG_C share. */
507 uint16_t domain_id; /* Switch domain identifier. */
508 uint16_t vport_id; /* Associated VF vport index (if any). */
509 uint32_t vport_meta_tag; /* Used for vport index match ove VF LAG. */
510 uint32_t vport_meta_mask; /* Used for vport index field match mask. */
511 int32_t representor_id; /* Port representor identifier. */
512 int32_t pf_bond; /* >=0 means PF index in bonding configuration. */
513 unsigned int if_index; /* Associated kernel network device index. */
515 unsigned int rxqs_n; /* RX queues array size. */
516 unsigned int txqs_n; /* TX queues array size. */
517 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */
518 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */
519 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
520 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */
521 unsigned int (*reta_idx)[]; /* RETA index table. */
522 unsigned int reta_idx_n; /* RETA index size. */
523 struct mlx5_drop drop_queue; /* Flow drop queues. */
524 uint32_t flows; /* RTE Flow rules. */
525 uint32_t ctrl_flows; /* Control flow rules. */
526 void *inter_flows; /* Intermediate resources for flow creation. */
527 void *rss_desc; /* Intermediate rss description resources. */
528 int flow_idx; /* Intermediate device flow index. */
529 int flow_nested_idx; /* Intermediate device flow index, nested. */
530 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */
531 LIST_HEAD(rxqobj, mlx5_rxq_obj) rxqsobj; /* Verbs/DevX Rx queues. */
532 uint32_t hrxqs; /* Verbs Hash Rx queues. */
533 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */
534 LIST_HEAD(txqobj, mlx5_txq_obj) txqsobj; /* Verbs/DevX Tx queues. */
535 /* Indirection tables. */
536 LIST_HEAD(ind_tables, mlx5_ind_table_obj) ind_tbls;
537 /* Pointer to next element. */
538 rte_atomic32_t refcnt; /**< Reference counter. */
539 struct ibv_flow_action *verbs_action;
540 /**< Verbs modify header action object. */
541 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
542 uint8_t max_lro_msg_size;
543 /* Tags resources cache. */
544 uint32_t link_speed_capa; /* Link speed capabilities. */
545 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */
546 struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */
547 struct mlx5_dev_config config; /* Device configuration. */
548 struct mlx5_verbs_alloc_ctx verbs_alloc_ctx;
549 /* Context for Verbs allocator. */
550 int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */
551 int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */
552 LIST_HEAD(dbrpage, mlx5_devx_dbr_page) dbrpgs; /* Door-bell pages. */
553 struct mlx5_nl_vlan_vmwa_context *vmwa_context; /* VLAN WA context. */
554 struct mlx5_flow_id_pool *qrss_id_pool;
555 struct mlx5_hlist *mreg_cp_tbl;
556 /* Hash table of Rx metadata register copy table. */
557 uint8_t mtr_sfx_reg; /* Meter prefix-suffix flow match REG_C. */
558 uint8_t mtr_color_reg; /* Meter color match REG_C. */
559 struct mlx5_mtr_profiles flow_meter_profiles; /* MTR profile list. */
560 struct mlx5_flow_meters flow_meters; /* MTR list. */
562 rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */
563 rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX];
564 /* UAR same-page access control required in 32bit implementations. */
566 uint8_t skip_default_rss_reta; /* Skip configuration of default reta. */
567 uint8_t fdb_def_rule; /* Whether fdb jump to table 1 is configured. */
568 struct mlx5_mp_id mp_id; /* ID of a multi-process process */
569 LIST_HEAD(fdir, mlx5_fdir_flow) fdir_flows; /* fdir flows. */
572 #define PORT_ID(priv) ((priv)->dev_data->port_id)
573 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)])
577 int mlx5_getenv_int(const char *);
578 int mlx5_proc_priv_init(struct rte_eth_dev *dev);
579 int64_t mlx5_get_dbr(struct rte_eth_dev *dev,
580 struct mlx5_devx_dbr_page **dbr_page);
581 int32_t mlx5_release_dbr(struct rte_eth_dev *dev, uint32_t umem_id,
583 int mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev,
584 struct rte_eth_udp_tunnel *udp_tunnel);
585 uint16_t mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev);
587 /* Macro to iterate over all valid ports for mlx5 driver. */
588 #define MLX5_ETH_FOREACH_DEV(port_id, pci_dev) \
589 for (port_id = mlx5_eth_find_next(0, pci_dev); \
590 port_id < RTE_MAX_ETHPORTS; \
591 port_id = mlx5_eth_find_next(port_id + 1, pci_dev))
595 int mlx5_get_ifname(const struct rte_eth_dev *dev, char (*ifname)[IF_NAMESIZE]);
596 int mlx5_get_master_ifname(const char *ibdev_path, char (*ifname)[IF_NAMESIZE]);
597 unsigned int mlx5_ifindex(const struct rte_eth_dev *dev);
598 int mlx5_ifreq(const struct rte_eth_dev *dev, int req, struct ifreq *ifr);
599 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu);
600 int mlx5_set_flags(struct rte_eth_dev *dev, unsigned int keep,
602 int mlx5_dev_configure(struct rte_eth_dev *dev);
603 int mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info);
604 int mlx5_read_clock(struct rte_eth_dev *dev, uint64_t *clock);
605 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size);
606 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev);
607 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete);
608 int mlx5_force_link_status_change(struct rte_eth_dev *dev, int status);
609 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
610 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev,
611 struct rte_eth_fc_conf *fc_conf);
612 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev,
613 struct rte_eth_fc_conf *fc_conf);
614 void mlx5_dev_link_status_handler(void *arg);
615 void mlx5_dev_interrupt_handler(void *arg);
616 void mlx5_dev_interrupt_handler_devx(void *arg);
617 void mlx5_dev_interrupt_handler_uninstall(struct rte_eth_dev *dev);
618 void mlx5_dev_interrupt_handler_install(struct rte_eth_dev *dev);
619 void mlx5_dev_interrupt_handler_devx_uninstall(struct rte_eth_dev *dev);
620 void mlx5_dev_interrupt_handler_devx_install(struct rte_eth_dev *dev);
621 int mlx5_set_link_down(struct rte_eth_dev *dev);
622 int mlx5_set_link_up(struct rte_eth_dev *dev);
623 int mlx5_is_removed(struct rte_eth_dev *dev);
624 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev);
625 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev);
626 struct mlx5_priv *mlx5_port_to_eswitch_info(uint16_t port, bool valid);
627 struct mlx5_priv *mlx5_dev_to_eswitch_info(struct rte_eth_dev *dev);
628 int mlx5_sysfs_switch_info(unsigned int ifindex,
629 struct mlx5_switch_info *info);
630 void mlx5_sysfs_check_switch_info(bool device_dir,
631 struct mlx5_switch_info *switch_info);
632 void mlx5_translate_port_name(const char *port_name_in,
633 struct mlx5_switch_info *port_info_out);
634 void mlx5_intr_callback_unregister(const struct rte_intr_handle *handle,
635 rte_intr_callback_fn cb_fn, void *cb_arg);
636 int mlx5_get_module_info(struct rte_eth_dev *dev,
637 struct rte_eth_dev_module_info *modinfo);
638 int mlx5_get_module_eeprom(struct rte_eth_dev *dev,
639 struct rte_dev_eeprom_info *info);
640 int mlx5_hairpin_cap_get(struct rte_eth_dev *dev,
641 struct rte_eth_hairpin_cap *cap);
642 int mlx5_dev_configure_rss_reta(struct rte_eth_dev *dev);
646 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]);
647 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
648 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
649 uint32_t index, uint32_t vmdq);
650 struct mlx5_nl_vlan_vmwa_context *mlx5_vlan_vmwa_init
651 (struct rte_eth_dev *dev, uint32_t ifindex);
652 int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr);
653 int mlx5_set_mc_addr_list(struct rte_eth_dev *dev,
654 struct rte_ether_addr *mc_addr_set,
655 uint32_t nb_mc_addr);
659 int mlx5_rss_hash_update(struct rte_eth_dev *dev,
660 struct rte_eth_rss_conf *rss_conf);
661 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev,
662 struct rte_eth_rss_conf *rss_conf);
663 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size);
664 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev,
665 struct rte_eth_rss_reta_entry64 *reta_conf,
667 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev,
668 struct rte_eth_rss_reta_entry64 *reta_conf,
673 int mlx5_promiscuous_enable(struct rte_eth_dev *dev);
674 int mlx5_promiscuous_disable(struct rte_eth_dev *dev);
675 int mlx5_allmulticast_enable(struct rte_eth_dev *dev);
676 int mlx5_allmulticast_disable(struct rte_eth_dev *dev);
680 void mlx5_stats_init(struct rte_eth_dev *dev);
681 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
682 int mlx5_stats_reset(struct rte_eth_dev *dev);
683 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats,
685 int mlx5_xstats_reset(struct rte_eth_dev *dev);
686 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
687 struct rte_eth_xstat_name *xstats_names,
692 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
693 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on);
694 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask);
695 void mlx5_vlan_vmwa_exit(struct mlx5_nl_vlan_vmwa_context *ctx);
696 void mlx5_vlan_vmwa_release(struct rte_eth_dev *dev,
697 struct mlx5_vf_vlan *vf_vlan);
698 void mlx5_vlan_vmwa_acquire(struct rte_eth_dev *dev,
699 struct mlx5_vf_vlan *vf_vlan);
703 int mlx5_dev_start(struct rte_eth_dev *dev);
704 void mlx5_dev_stop(struct rte_eth_dev *dev);
705 int mlx5_traffic_enable(struct rte_eth_dev *dev);
706 void mlx5_traffic_disable(struct rte_eth_dev *dev);
707 int mlx5_traffic_restart(struct rte_eth_dev *dev);
711 int mlx5_flow_discover_mreg_c(struct rte_eth_dev *eth_dev);
712 bool mlx5_flow_ext_mreg_supported(struct rte_eth_dev *dev);
713 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
714 void mlx5_flow_print(struct rte_flow *flow);
715 int mlx5_flow_validate(struct rte_eth_dev *dev,
716 const struct rte_flow_attr *attr,
717 const struct rte_flow_item items[],
718 const struct rte_flow_action actions[],
719 struct rte_flow_error *error);
720 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev,
721 const struct rte_flow_attr *attr,
722 const struct rte_flow_item items[],
723 const struct rte_flow_action actions[],
724 struct rte_flow_error *error);
725 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow,
726 struct rte_flow_error *error);
727 void mlx5_flow_list_flush(struct rte_eth_dev *dev, uint32_t *list, bool active);
728 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error);
729 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow,
730 const struct rte_flow_action *action, void *data,
731 struct rte_flow_error *error);
732 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable,
733 struct rte_flow_error *error);
734 int mlx5_dev_filter_ctrl(struct rte_eth_dev *dev,
735 enum rte_filter_type filter_type,
736 enum rte_filter_op filter_op,
738 int mlx5_flow_start(struct rte_eth_dev *dev, uint32_t *list);
739 void mlx5_flow_stop(struct rte_eth_dev *dev, uint32_t *list);
740 int mlx5_flow_start_default(struct rte_eth_dev *dev);
741 void mlx5_flow_stop_default(struct rte_eth_dev *dev);
742 void mlx5_flow_alloc_intermediate(struct rte_eth_dev *dev);
743 void mlx5_flow_free_intermediate(struct rte_eth_dev *dev);
744 int mlx5_flow_verify(struct rte_eth_dev *dev);
745 int mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, uint32_t queue);
746 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev,
747 struct rte_flow_item_eth *eth_spec,
748 struct rte_flow_item_eth *eth_mask,
749 struct rte_flow_item_vlan *vlan_spec,
750 struct rte_flow_item_vlan *vlan_mask);
751 int mlx5_ctrl_flow(struct rte_eth_dev *dev,
752 struct rte_flow_item_eth *eth_spec,
753 struct rte_flow_item_eth *eth_mask);
754 struct rte_flow *mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev);
755 int mlx5_flow_create_drop_queue(struct rte_eth_dev *dev);
756 void mlx5_flow_delete_drop_queue(struct rte_eth_dev *dev);
757 void mlx5_flow_async_pool_query_handle(struct mlx5_ibv_shared *sh,
758 uint64_t async_id, int status);
759 void mlx5_set_query_alarm(struct mlx5_ibv_shared *sh);
760 void mlx5_flow_query_alarm(void *arg);
761 uint32_t mlx5_counter_alloc(struct rte_eth_dev *dev);
762 void mlx5_counter_free(struct rte_eth_dev *dev, uint32_t cnt);
763 int mlx5_counter_query(struct rte_eth_dev *dev, uint32_t cnt,
764 bool clear, uint64_t *pkts, uint64_t *bytes);
765 int mlx5_flow_dev_dump(struct rte_eth_dev *dev, FILE *file,
766 struct rte_flow_error *error);
767 void mlx5_flow_rxq_dynf_metadata_set(struct rte_eth_dev *dev);
770 int mlx5_mp_primary_handle(const struct rte_mp_msg *mp_msg, const void *peer);
771 int mlx5_mp_secondary_handle(const struct rte_mp_msg *mp_msg, const void *peer);
772 void mlx5_mp_req_start_rxtx(struct rte_eth_dev *dev);
773 void mlx5_mp_req_stop_rxtx(struct rte_eth_dev *dev);
777 int mlx5_pmd_socket_init(void);
779 /* mlx5_flow_meter.c */
781 int mlx5_flow_meter_ops_get(struct rte_eth_dev *dev, void *arg);
782 struct mlx5_flow_meter *mlx5_flow_meter_find(struct mlx5_priv *priv,
784 struct mlx5_flow_meter *mlx5_flow_meter_attach
785 (struct mlx5_priv *priv,
787 const struct rte_flow_attr *attr,
788 struct rte_flow_error *error);
789 void mlx5_flow_meter_detach(struct mlx5_flow_meter *fm);
791 #endif /* RTE_PMD_MLX5_H_ */