1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_H_
7 #define RTE_PMD_MLX5_H_
13 #include <netinet/in.h>
14 #include <sys/queue.h>
17 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
19 #pragma GCC diagnostic ignored "-Wpedantic"
21 #include <infiniband/verbs.h>
23 #pragma GCC diagnostic error "-Wpedantic"
27 #include <rte_ether.h>
28 #include <rte_ethdev_driver.h>
29 #include <rte_rwlock.h>
30 #include <rte_interrupts.h>
31 #include <rte_errno.h>
34 #include "mlx5_utils.h"
36 #include "mlx5_rxtx.h"
37 #include "mlx5_autoconf.h"
38 #include "mlx5_defs.h"
41 PCI_VENDOR_ID_MELLANOX = 0x15b3,
45 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013,
46 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014,
47 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015,
48 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016,
49 PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017,
50 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018,
51 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019,
52 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a,
53 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF = 0xa2d2,
54 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF = 0xa2d3,
55 PCI_DEVICE_ID_MELLANOX_CONNECTX6 = 0x101b,
56 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF = 0x101c,
59 /** Switch information returned by mlx5_nl_switch_info(). */
60 struct mlx5_switch_info {
61 uint32_t master:1; /**< Master device. */
62 uint32_t representor:1; /**< Representor device. */
63 int32_t port_name; /**< Representor port name. */
64 uint64_t switch_id; /**< Switch identifier. */
67 LIST_HEAD(mlx5_dev_list, mlx5_priv);
69 /* Shared memory between primary and secondary processes. */
70 struct mlx5_shared_data {
71 struct mlx5_dev_list mem_event_cb_list;
72 rte_rwlock_t mem_event_rwlock;
75 extern struct mlx5_shared_data *mlx5_shared_data;
77 struct mlx5_counter_ctrl {
78 /* Name of the counter. */
79 char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE];
80 /* Name of the counter on the device table. */
81 char ctr_name[RTE_ETH_XSTATS_NAME_SIZE];
82 uint32_t ib:1; /**< Nonzero for IB counters. */
85 struct mlx5_xstats_ctrl {
86 /* Number of device stats. */
88 /* Number of device stats identified by PMD. */
89 uint16_t mlx5_stats_n;
90 /* Index in the device counters table. */
91 uint16_t dev_table_idx[MLX5_MAX_XSTATS];
92 uint64_t base[MLX5_MAX_XSTATS];
93 struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS];
96 struct mlx5_stats_ctrl {
97 /* Base for imissed counter. */
98 uint64_t imissed_base;
101 /* devx counter object */
102 struct mlx5_devx_counter_set {
103 struct mlx5dv_devx_obj *obj;
104 int id; /* Flow counter ID */
108 TAILQ_HEAD(mlx5_flows, rte_flow);
110 /* Default PMD specific parameter value. */
111 #define MLX5_ARG_UNSET (-1)
114 * Device configuration structure.
116 * Merged configuration from:
118 * - Device capabilities,
119 * - User device parameters disabled features.
121 struct mlx5_dev_config {
122 unsigned int hw_csum:1; /* Checksum offload is supported. */
123 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */
124 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */
125 unsigned int hw_padding:1; /* End alignment padding is supported. */
126 unsigned int vf:1; /* This is a VF. */
127 unsigned int tunnel_en:1;
128 /* Whether tunnel stateless offloads are supported. */
129 unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */
130 unsigned int cqe_comp:1; /* CQE compression is enabled. */
131 unsigned int cqe_pad:1; /* CQE padding is enabled. */
132 unsigned int tso:1; /* Whether TSO is supported. */
133 unsigned int tx_vec_en:1; /* Tx vector is enabled. */
134 unsigned int rx_vec_en:1; /* Rx vector is enabled. */
135 unsigned int mpw_hdr_dseg:1; /* Enable DSEGs in the title WQEBB. */
136 unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */
137 unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */
138 unsigned int dv_flow_en:1; /* Enable DV flow. */
139 unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */
140 unsigned int devx:1; /* Whether devx interface is available or not. */
142 unsigned int enabled:1; /* Whether MPRQ is enabled. */
143 unsigned int stride_num_n; /* Number of strides. */
144 unsigned int min_stride_size_n; /* Min size of a stride. */
145 unsigned int max_stride_size_n; /* Max size of a stride. */
146 unsigned int max_memcpy_len;
147 /* Maximum packet size to memcpy Rx packets. */
148 unsigned int min_rxqs_num;
149 /* Rx queue count threshold to enable MPRQ. */
150 } mprq; /* Configurations for Multi-Packet RQ. */
151 int mps; /* Multi-packet send supported mode. */
152 unsigned int flow_prio; /* Number of flow priorities. */
153 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */
154 unsigned int ind_table_max_size; /* Maximum indirection table size. */
155 int txq_inline; /* Maximum packet size for inlining. */
156 int txqs_inline; /* Queue number threshold for inlining. */
157 int txqs_vec; /* Queue number threshold for vectorized Tx. */
158 int inline_max_packet_sz; /* Max packet size for inlining. */
162 * Type of objet being allocated.
164 enum mlx5_verbs_alloc_type {
165 MLX5_VERBS_ALLOC_TYPE_NONE,
166 MLX5_VERBS_ALLOC_TYPE_TX_QUEUE,
167 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE,
171 * Verbs allocator needs a context to know in the callback which kind of
172 * resources it is allocating.
174 struct mlx5_verbs_alloc_ctx {
175 enum mlx5_verbs_alloc_type type; /* Kind of object being allocated. */
176 const void *obj; /* Pointer to the DPDK object. */
179 LIST_HEAD(mlx5_mr_list, mlx5_mr);
181 /* Flow drop context necessary due to Verbs API. */
183 struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */
184 struct mlx5_rxq_ibv *rxq; /* Verbs Rx queue. */
187 struct mlx5_flow_tcf_context;
190 LIST_ENTRY(mlx5_priv) mem_event_cb;
191 /**< Called by memory event callback. */
192 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */
193 struct ibv_context *ctx; /* Verbs context. */
194 struct ibv_device_attr_ex device_attr; /* Device properties. */
195 struct ibv_pd *pd; /* Protection Domain. */
196 char ibdev_name[IBV_SYSFS_NAME_MAX]; /* IB device name. */
197 char ibdev_path[IBV_SYSFS_PATH_MAX]; /* IB device path for secondary */
198 struct ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */
199 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES);
200 /* Bit-field of MAC addresses owned by the PMD. */
201 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */
202 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */
203 /* Device properties. */
204 uint16_t mtu; /* Configured MTU. */
205 unsigned int isolated:1; /* Whether isolated mode is enabled. */
206 unsigned int representor:1; /* Device is a port representor. */
207 uint16_t domain_id; /* Switch domain identifier. */
208 int32_t representor_id; /* Port representor identifier. */
210 unsigned int rxqs_n; /* RX queues array size. */
211 unsigned int txqs_n; /* TX queues array size. */
212 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */
213 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */
214 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
215 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */
216 struct rte_intr_handle intr_handle; /* Interrupt handler. */
217 unsigned int (*reta_idx)[]; /* RETA index table. */
218 unsigned int reta_idx_n; /* RETA index size. */
219 struct mlx5_drop drop_queue; /* Flow drop queues. */
220 struct mlx5_flows flows; /* RTE Flow rules. */
221 struct mlx5_flows ctrl_flows; /* Control flow rules. */
222 LIST_HEAD(counters, mlx5_flow_counter) flow_counters;
225 uint32_t dev_gen; /* Generation number to flush local caches. */
226 rte_rwlock_t rwlock; /* MR Lock. */
227 struct mlx5_mr_btree cache; /* Global MR cache table. */
228 struct mlx5_mr_list mr_list; /* Registered MR list. */
229 struct mlx5_mr_list mr_free_list; /* Freed MR list. */
231 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */
232 LIST_HEAD(rxqibv, mlx5_rxq_ibv) rxqsibv; /* Verbs Rx queues. */
233 LIST_HEAD(hrxq, mlx5_hrxq) hrxqs; /* Verbs Hash Rx queues. */
234 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */
235 LIST_HEAD(txqibv, mlx5_txq_ibv) txqsibv; /* Verbs Tx queues. */
236 /* Verbs Indirection tables. */
237 LIST_HEAD(ind_tables, mlx5_ind_table_ibv) ind_tbls;
238 LIST_HEAD(matchers, mlx5_flow_dv_matcher) matchers;
239 LIST_HEAD(encap_decap, mlx5_flow_dv_encap_decap_resource) encaps_decaps;
240 LIST_HEAD(modify_cmd, mlx5_flow_dv_modify_hdr_resource) modify_cmds;
241 uint32_t link_speed_capa; /* Link speed capabilities. */
242 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */
243 struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */
244 int primary_socket; /* Unix socket for primary process. */
245 void *uar_base; /* Reserved address space for UAR mapping */
246 struct rte_intr_handle intr_handle_socket; /* Interrupt handler. */
247 struct mlx5_dev_config config; /* Device configuration. */
248 struct mlx5_verbs_alloc_ctx verbs_alloc_ctx;
249 /* Context for Verbs allocator. */
250 int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */
251 int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */
252 uint32_t nl_sn; /* Netlink message sequence number. */
254 rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */
255 rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX];
256 /* UAR same-page access control required in 32bit implementations. */
258 struct mlx5_flow_tcf_context *tcf_context; /* TC flower context. */
261 #define PORT_ID(priv) ((priv)->dev_data->port_id)
262 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)])
266 int mlx5_getenv_int(const char *);
270 int mlx5_get_ifname(const struct rte_eth_dev *dev, char (*ifname)[IF_NAMESIZE]);
271 unsigned int mlx5_ifindex(const struct rte_eth_dev *dev);
272 int mlx5_ifreq(const struct rte_eth_dev *dev, int req, struct ifreq *ifr);
273 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu);
274 int mlx5_set_flags(struct rte_eth_dev *dev, unsigned int keep,
276 int mlx5_dev_configure(struct rte_eth_dev *dev);
277 void mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info);
278 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size);
279 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev);
280 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete);
281 int mlx5_force_link_status_change(struct rte_eth_dev *dev, int status);
282 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
283 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev,
284 struct rte_eth_fc_conf *fc_conf);
285 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev,
286 struct rte_eth_fc_conf *fc_conf);
287 int mlx5_ibv_device_to_pci_addr(const struct ibv_device *device,
288 struct rte_pci_addr *pci_addr);
289 void mlx5_dev_link_status_handler(void *arg);
290 void mlx5_dev_interrupt_handler(void *arg);
291 void mlx5_dev_interrupt_handler_uninstall(struct rte_eth_dev *dev);
292 void mlx5_dev_interrupt_handler_install(struct rte_eth_dev *dev);
293 int mlx5_set_link_down(struct rte_eth_dev *dev);
294 int mlx5_set_link_up(struct rte_eth_dev *dev);
295 int mlx5_is_removed(struct rte_eth_dev *dev);
296 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev);
297 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev);
298 unsigned int mlx5_dev_to_port_id(const struct rte_device *dev,
300 unsigned int port_list_n);
301 int mlx5_sysfs_switch_info(unsigned int ifindex,
302 struct mlx5_switch_info *info);
306 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[ETHER_ADDR_LEN]);
307 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
308 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac,
309 uint32_t index, uint32_t vmdq);
310 int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr);
311 int mlx5_set_mc_addr_list(struct rte_eth_dev *dev,
312 struct ether_addr *mc_addr_set, uint32_t nb_mc_addr);
316 int mlx5_rss_hash_update(struct rte_eth_dev *dev,
317 struct rte_eth_rss_conf *rss_conf);
318 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev,
319 struct rte_eth_rss_conf *rss_conf);
320 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size);
321 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev,
322 struct rte_eth_rss_reta_entry64 *reta_conf,
324 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev,
325 struct rte_eth_rss_reta_entry64 *reta_conf,
330 void mlx5_promiscuous_enable(struct rte_eth_dev *dev);
331 void mlx5_promiscuous_disable(struct rte_eth_dev *dev);
332 void mlx5_allmulticast_enable(struct rte_eth_dev *dev);
333 void mlx5_allmulticast_disable(struct rte_eth_dev *dev);
337 void mlx5_stats_init(struct rte_eth_dev *dev);
338 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
339 void mlx5_stats_reset(struct rte_eth_dev *dev);
340 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats,
342 void mlx5_xstats_reset(struct rte_eth_dev *dev);
343 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
344 struct rte_eth_xstat_name *xstats_names,
349 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
350 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on);
351 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask);
355 int mlx5_dev_start(struct rte_eth_dev *dev);
356 void mlx5_dev_stop(struct rte_eth_dev *dev);
357 int mlx5_traffic_enable(struct rte_eth_dev *dev);
358 void mlx5_traffic_disable(struct rte_eth_dev *dev);
359 int mlx5_traffic_restart(struct rte_eth_dev *dev);
363 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
364 void mlx5_flow_print(struct rte_flow *flow);
365 int mlx5_flow_validate(struct rte_eth_dev *dev,
366 const struct rte_flow_attr *attr,
367 const struct rte_flow_item items[],
368 const struct rte_flow_action actions[],
369 struct rte_flow_error *error);
370 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev,
371 const struct rte_flow_attr *attr,
372 const struct rte_flow_item items[],
373 const struct rte_flow_action actions[],
374 struct rte_flow_error *error);
375 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow,
376 struct rte_flow_error *error);
377 void mlx5_flow_list_flush(struct rte_eth_dev *dev, struct mlx5_flows *list);
378 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error);
379 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow,
380 const struct rte_flow_action *action, void *data,
381 struct rte_flow_error *error);
382 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable,
383 struct rte_flow_error *error);
384 int mlx5_dev_filter_ctrl(struct rte_eth_dev *dev,
385 enum rte_filter_type filter_type,
386 enum rte_filter_op filter_op,
388 int mlx5_flow_start(struct rte_eth_dev *dev, struct mlx5_flows *list);
389 void mlx5_flow_stop(struct rte_eth_dev *dev, struct mlx5_flows *list);
390 int mlx5_flow_verify(struct rte_eth_dev *dev);
391 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev,
392 struct rte_flow_item_eth *eth_spec,
393 struct rte_flow_item_eth *eth_mask,
394 struct rte_flow_item_vlan *vlan_spec,
395 struct rte_flow_item_vlan *vlan_mask);
396 int mlx5_ctrl_flow(struct rte_eth_dev *dev,
397 struct rte_flow_item_eth *eth_spec,
398 struct rte_flow_item_eth *eth_mask);
399 int mlx5_flow_create_drop_queue(struct rte_eth_dev *dev);
400 void mlx5_flow_delete_drop_queue(struct rte_eth_dev *dev);
404 int mlx5_socket_init(struct rte_eth_dev *priv);
405 void mlx5_socket_uninit(struct rte_eth_dev *priv);
406 void mlx5_socket_handle(struct rte_eth_dev *priv);
407 int mlx5_socket_connect(struct rte_eth_dev *priv);
411 int mlx5_nl_init(int protocol);
412 int mlx5_nl_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac,
414 int mlx5_nl_mac_addr_remove(struct rte_eth_dev *dev, struct ether_addr *mac,
416 void mlx5_nl_mac_addr_sync(struct rte_eth_dev *dev);
417 void mlx5_nl_mac_addr_flush(struct rte_eth_dev *dev);
418 int mlx5_nl_promisc(struct rte_eth_dev *dev, int enable);
419 int mlx5_nl_allmulti(struct rte_eth_dev *dev, int enable);
420 unsigned int mlx5_nl_ifindex(int nl, const char *name);
421 int mlx5_nl_switch_info(int nl, unsigned int ifindex,
422 struct mlx5_switch_info *info);
424 /* mlx5_devx_cmds.c */
426 int mlx5_devx_cmd_flow_counter_alloc(struct ibv_context *ctx,
427 struct mlx5_devx_counter_set *dcx);
428 int mlx5_devx_cmd_flow_counter_free(struct mlx5dv_devx_obj *obj);
429 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_counter_set *dcx,
431 uint64_t *pkts, uint64_t *bytes);
432 #endif /* RTE_PMD_MLX5_H_ */