1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_H_
7 #define RTE_PMD_MLX5_H_
14 #include <netinet/in.h>
15 #include <sys/queue.h>
18 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
20 #pragma GCC diagnostic ignored "-Wpedantic"
22 #include <infiniband/verbs.h>
24 #pragma GCC diagnostic error "-Wpedantic"
28 #include <rte_ether.h>
29 #include <rte_ethdev_driver.h>
30 #include <rte_rwlock.h>
31 #include <rte_interrupts.h>
32 #include <rte_errno.h>
35 #include "mlx5_utils.h"
37 #include "mlx5_autoconf.h"
38 #include "mlx5_defs.h"
39 #include "mlx5_glue.h"
43 PCI_VENDOR_ID_MELLANOX = 0x15b3,
47 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013,
48 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014,
49 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015,
50 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016,
51 PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017,
52 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018,
53 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019,
54 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a,
55 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF = 0xa2d2,
56 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF = 0xa2d3,
57 PCI_DEVICE_ID_MELLANOX_CONNECTX6 = 0x101b,
58 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF = 0x101c,
59 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX = 0x101d,
60 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF = 0x101e,
63 /* Request types for IPC. */
64 enum mlx5_mp_req_type {
65 MLX5_MP_REQ_VERBS_CMD_FD = 1,
66 MLX5_MP_REQ_CREATE_MR,
67 MLX5_MP_REQ_START_RXTX,
68 MLX5_MP_REQ_STOP_RXTX,
69 MLX5_MP_REQ_QUEUE_STATE_MODIFY,
72 struct mlx5_mp_arg_queue_state_modify {
73 uint8_t is_wq; /* Set if WQ. */
74 uint16_t queue_id; /* DPDK queue ID. */
75 enum ibv_wq_state state; /* WQ requested state. */
78 /* Pameters for IPC. */
79 struct mlx5_mp_param {
80 enum mlx5_mp_req_type type;
85 uintptr_t addr; /* MLX5_MP_REQ_CREATE_MR */
86 struct mlx5_mp_arg_queue_state_modify state_modify;
87 /* MLX5_MP_REQ_QUEUE_STATE_MODIFY */
91 /** Request timeout for IPC. */
92 #define MLX5_MP_REQ_TIMEOUT_SEC 5
94 /** Key string for IPC. */
95 #define MLX5_MP_NAME "net_mlx5_mp"
97 /* Recognized Infiniband device physical port name types. */
98 enum mlx5_phys_port_name_type {
99 MLX5_PHYS_PORT_NAME_TYPE_NOTSET = 0, /* Not set. */
100 MLX5_PHYS_PORT_NAME_TYPE_LEGACY, /* before kernel ver < 5.0 */
101 MLX5_PHYS_PORT_NAME_TYPE_UPLINK, /* p0, kernel ver >= 5.0 */
102 MLX5_PHYS_PORT_NAME_TYPE_PFVF, /* pf0vf0, kernel ver >= 5.0 */
103 MLX5_PHYS_PORT_NAME_TYPE_UNKNOWN, /* Unrecognized. */
106 /** Switch information returned by mlx5_nl_switch_info(). */
107 struct mlx5_switch_info {
108 uint32_t master:1; /**< Master device. */
109 uint32_t representor:1; /**< Representor device. */
110 enum mlx5_phys_port_name_type name_type; /** < Port name type. */
111 int32_t pf_num; /**< PF number (valid for pfxvfx format only). */
112 int32_t port_name; /**< Representor port name. */
113 uint64_t switch_id; /**< Switch identifier. */
116 LIST_HEAD(mlx5_dev_list, mlx5_ibv_shared);
118 /* Shared data between primary and secondary processes. */
119 struct mlx5_shared_data {
121 /* Global spinlock for primary and secondary processes. */
122 int init_done; /* Whether primary has done initialization. */
123 unsigned int secondary_cnt; /* Number of secondary processes init'd. */
124 struct mlx5_dev_list mem_event_cb_list;
125 rte_rwlock_t mem_event_rwlock;
128 /* Per-process data structure, not visible to other processes. */
129 struct mlx5_local_data {
130 int init_done; /* Whether a secondary has done initialization. */
133 extern struct mlx5_shared_data *mlx5_shared_data;
135 struct mlx5_counter_ctrl {
136 /* Name of the counter. */
137 char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE];
138 /* Name of the counter on the device table. */
139 char ctr_name[RTE_ETH_XSTATS_NAME_SIZE];
140 uint32_t ib:1; /**< Nonzero for IB counters. */
143 struct mlx5_xstats_ctrl {
144 /* Number of device stats. */
146 /* Number of device stats identified by PMD. */
147 uint16_t mlx5_stats_n;
148 /* Index in the device counters table. */
149 uint16_t dev_table_idx[MLX5_MAX_XSTATS];
150 uint64_t base[MLX5_MAX_XSTATS];
151 struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS];
154 struct mlx5_stats_ctrl {
155 /* Base for imissed counter. */
156 uint64_t imissed_base;
159 /* devX creation object */
160 struct mlx5_devx_obj {
161 struct mlx5dv_devx_obj *obj; /* The DV object. */
162 int id; /* The object ID. */
165 struct mlx5_devx_mkey_attr {
172 /* HCA qos attributes. */
173 struct mlx5_hca_qos_attr {
174 uint32_t sup:1; /* Whether QOS is supported. */
175 uint32_t srtcm_sup:1; /* Whether srTCM mode is supported. */
176 uint32_t flow_meter_reg_share:1;
177 /* Whether reg_c share is supported. */
178 uint8_t log_max_flow_meter;
179 /* Power of the maximum supported meters. */
180 uint8_t flow_meter_reg_c_ids;
181 /* Bitmap of the reg_Cs available for flow meter to use. */
185 /* HCA supports this number of time periods for LRO. */
186 #define MLX5_LRO_NUM_SUPP_PERIODS 4
188 /* HCA attributes. */
189 struct mlx5_hca_attr {
190 uint32_t eswitch_manager:1;
191 uint32_t flow_counters_dump:1;
192 uint8_t flow_counter_bulk_alloc_bitmap;
193 uint32_t eth_net_offloads:1;
195 uint32_t wqe_vlan_insert:1;
196 uint32_t wqe_inline_mode:2;
197 uint32_t vport_inline_mode:3;
198 uint32_t tunnel_stateless_geneve_rx:1;
199 uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */
200 uint32_t tunnel_stateless_gtp:1;
202 uint32_t tunnel_lro_gre:1;
203 uint32_t tunnel_lro_vxlan:1;
204 uint32_t lro_max_msg_sz_mode:2;
205 uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS];
206 uint32_t flex_parser_protocols;
208 uint32_t log_max_hairpin_queues:5;
209 uint32_t log_max_hairpin_wq_data_sz:5;
210 uint32_t log_max_hairpin_num_packets:5;
212 struct mlx5_hca_qos_attr qos;
216 TAILQ_HEAD(mlx5_flows, rte_flow);
218 /* Default PMD specific parameter value. */
219 #define MLX5_ARG_UNSET (-1)
221 #define MLX5_LRO_SUPPORTED(dev) \
222 (((struct mlx5_priv *)((dev)->data->dev_private))->config.lro.supported)
224 /* Maximal size of coalesced segment for LRO is set in chunks of 256 Bytes. */
225 #define MLX5_LRO_SEG_CHUNK_SIZE 256u
227 /* Maximal size of aggregated LRO packet. */
228 #define MLX5_MAX_LRO_SIZE (UINT8_MAX * MLX5_LRO_SEG_CHUNK_SIZE)
230 /* LRO configurations structure. */
231 struct mlx5_lro_config {
232 uint32_t supported:1; /* Whether LRO is supported. */
233 uint32_t timeout; /* User configuration. */
237 * Device configuration structure.
239 * Merged configuration from:
241 * - Device capabilities,
242 * - User device parameters disabled features.
244 struct mlx5_dev_config {
245 unsigned int hw_csum:1; /* Checksum offload is supported. */
246 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */
247 unsigned int hw_vlan_insert:1; /* VLAN insertion in WQE is supported. */
248 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */
249 unsigned int hw_padding:1; /* End alignment padding is supported. */
250 unsigned int vf:1; /* This is a VF. */
251 unsigned int tunnel_en:1;
252 /* Whether tunnel stateless offloads are supported. */
253 unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */
254 unsigned int cqe_comp:1; /* CQE compression is enabled. */
255 unsigned int cqe_pad:1; /* CQE padding is enabled. */
256 unsigned int tso:1; /* Whether TSO is supported. */
257 unsigned int rx_vec_en:1; /* Rx vector is enabled. */
258 unsigned int mr_ext_memseg_en:1;
259 /* Whether memseg should be extended for MR creation. */
260 unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */
261 unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */
262 unsigned int dv_esw_en:1; /* Enable E-Switch DV flow. */
263 unsigned int dv_flow_en:1; /* Enable DV flow. */
264 unsigned int dv_xmeta_en:2; /* Enable extensive flow metadata. */
265 unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */
266 unsigned int devx:1; /* Whether devx interface is available or not. */
267 unsigned int dest_tir:1; /* Whether advanced DR API is available. */
269 unsigned int enabled:1; /* Whether MPRQ is enabled. */
270 unsigned int stride_num_n; /* Number of strides. */
271 unsigned int min_stride_size_n; /* Min size of a stride. */
272 unsigned int max_stride_size_n; /* Max size of a stride. */
273 unsigned int max_memcpy_len;
274 /* Maximum packet size to memcpy Rx packets. */
275 unsigned int min_rxqs_num;
276 /* Rx queue count threshold to enable MPRQ. */
277 } mprq; /* Configurations for Multi-Packet RQ. */
278 int mps; /* Multi-packet send supported mode. */
279 int dbnc; /* Skip doorbell register write barrier. */
280 unsigned int flow_prio; /* Number of flow priorities. */
281 enum modify_reg flow_mreg_c[MLX5_MREG_C_NUM];
282 /* Availibility of mreg_c's. */
283 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */
284 unsigned int ind_table_max_size; /* Maximum indirection table size. */
285 unsigned int max_dump_files_num; /* Maximum dump files per queue. */
286 int txqs_inline; /* Queue number threshold for inlining. */
287 int txq_inline_min; /* Minimal amount of data bytes to inline. */
288 int txq_inline_max; /* Max packet size for inlining with SEND. */
289 int txq_inline_mpw; /* Max packet size for inlining with eMPW. */
290 struct mlx5_hca_attr hca_attr; /* HCA attributes. */
291 struct mlx5_lro_config lro; /* LRO configuration. */
294 struct mlx5_devx_wq_attr {
296 uint32_t wq_signature:1;
297 uint32_t end_padding_mode:2;
299 uint32_t hds_skip_first_sge:1;
300 uint32_t log2_hds_buf_size:3;
301 uint32_t page_offset:5;
304 uint32_t uar_page:24;
308 uint32_t log_wq_stride:4;
309 uint32_t log_wq_pg_sz:5;
310 uint32_t log_wq_sz:5;
311 uint32_t dbr_umem_valid:1;
312 uint32_t wq_umem_valid:1;
313 uint32_t log_hairpin_num_packets:5;
314 uint32_t log_hairpin_data_sz:5;
315 uint32_t single_wqe_log_num_of_strides:4;
316 uint32_t two_byte_shift_en:1;
317 uint32_t single_stride_log_num_of_bytes:3;
318 uint32_t dbr_umem_id;
320 uint64_t wq_umem_offset;
323 /* Create RQ attributes structure, used by create RQ operation. */
324 struct mlx5_devx_create_rq_attr {
326 uint32_t delay_drop_en:1;
327 uint32_t scatter_fcs:1;
329 uint32_t mem_rq_type:4;
331 uint32_t flush_in_error_en:1;
333 uint32_t user_index:24;
335 uint32_t counter_set_id:8;
337 struct mlx5_devx_wq_attr wq_attr;
340 /* Modify RQ attributes structure, used by modify RQ operation. */
341 struct mlx5_devx_modify_rq_attr {
343 uint32_t rq_state:4; /* Current RQ state. */
344 uint32_t state:4; /* Required RQ state. */
345 uint32_t scatter_fcs:1;
347 uint32_t counter_set_id:8;
348 uint32_t hairpin_peer_sq:24;
349 uint32_t hairpin_peer_vhca:16;
350 uint64_t modify_bitmask;
351 uint32_t lwm:16; /* Contained WQ lwm. */
354 struct mlx5_rx_hash_field_select {
355 uint32_t l3_prot_type:1;
356 uint32_t l4_prot_type:1;
357 uint32_t selected_fields:30;
360 /* TIR attributes structure, used by TIR operations. */
361 struct mlx5_devx_tir_attr {
362 uint32_t disp_type:4;
363 uint32_t lro_timeout_period_usecs:16;
364 uint32_t lro_enable_mask:4;
365 uint32_t lro_max_msg_sz:8;
366 uint32_t inline_rqn:24;
367 uint32_t rx_hash_symmetric:1;
368 uint32_t tunneled_offload_en:1;
369 uint32_t indirect_table:24;
370 uint32_t rx_hash_fn:4;
371 uint32_t self_lb_block:2;
372 uint32_t transport_domain:24;
373 uint32_t rx_hash_toeplitz_key[10];
374 struct mlx5_rx_hash_field_select rx_hash_field_selector_outer;
375 struct mlx5_rx_hash_field_select rx_hash_field_selector_inner;
378 /* RQT attributes structure, used by RQT operations. */
379 struct mlx5_devx_rqt_attr {
380 uint32_t rqt_max_size:16;
381 uint32_t rqt_actual_size:16;
385 /* TIS attributes structure. */
386 struct mlx5_devx_tis_attr {
387 uint32_t strict_lag_tx_port_affinity:1;
389 uint32_t lag_tx_port_affinity:4;
391 uint32_t transport_domain:24;
394 /* SQ attributes structure, used by SQ create operation. */
395 struct mlx5_devx_create_sq_attr {
397 uint32_t cd_master:1;
399 uint32_t flush_in_error_en:1;
400 uint32_t allow_multi_pkt_send_wqe:1;
401 uint32_t min_wqe_inline_mode:3;
404 uint32_t allow_swp:1;
406 uint32_t user_index:24;
408 uint32_t packet_pacing_rate_limit_index:16;
409 uint32_t tis_lst_sz:16;
411 struct mlx5_devx_wq_attr wq_attr;
414 /* SQ attributes structure, used by SQ modify operation. */
415 struct mlx5_devx_modify_sq_attr {
418 uint32_t hairpin_peer_rq:24;
419 uint32_t hairpin_peer_vhca:16;
423 * Type of object being allocated.
425 enum mlx5_verbs_alloc_type {
426 MLX5_VERBS_ALLOC_TYPE_NONE,
427 MLX5_VERBS_ALLOC_TYPE_TX_QUEUE,
428 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE,
431 /* VLAN netdev for VLAN workaround. */
432 struct mlx5_vlan_dev {
434 uint32_t ifindex; /**< Own interface index. */
437 /* Structure for VF VLAN workaround. */
438 struct mlx5_vf_vlan {
444 * Array of VLAN devices created on the base of VF
445 * used for workaround in virtual environments.
447 struct mlx5_vlan_vmwa_context {
451 struct rte_eth_dev *dev;
452 struct mlx5_vlan_dev vlan_dev[4096];
456 * Verbs allocator needs a context to know in the callback which kind of
457 * resources it is allocating.
459 struct mlx5_verbs_alloc_ctx {
460 enum mlx5_verbs_alloc_type type; /* Kind of object being allocated. */
461 const void *obj; /* Pointer to the DPDK object. */
464 LIST_HEAD(mlx5_mr_list, mlx5_mr);
466 /* Flow drop context necessary due to Verbs API. */
468 struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */
469 struct mlx5_rxq_obj *rxq; /* Rx queue object. */
472 #define MLX5_COUNTERS_PER_POOL 512
473 #define MLX5_MAX_PENDING_QUERIES 4
475 struct mlx5_flow_counter_pool;
477 struct flow_counter_stats {
482 /* Counters information. */
483 struct mlx5_flow_counter {
484 TAILQ_ENTRY(mlx5_flow_counter) next;
485 /**< Pointer to the next flow counter structure. */
486 uint32_t shared:1; /**< Share counter ID with other flow rules. */
488 /**< Whether the counter was allocated by batch command. */
489 uint32_t ref_cnt:30; /**< Reference counter. */
490 uint32_t id; /**< Counter ID. */
491 union { /**< Holds the counters for the rule. */
492 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42)
493 struct ibv_counter_set *cs;
494 #elif defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
495 struct ibv_counters *cs;
497 struct mlx5_devx_obj *dcs; /**< Counter Devx object. */
498 struct mlx5_flow_counter_pool *pool; /**< The counter pool. */
501 uint64_t hits; /**< Reset value of hits packets. */
502 int64_t query_gen; /**< Generation of the last release. */
504 uint64_t bytes; /**< Reset value of bytes. */
505 void *action; /**< Pointer to the dv action. */
508 TAILQ_HEAD(mlx5_counters, mlx5_flow_counter);
510 /* Counter pool structure - query is in pool resolution. */
511 struct mlx5_flow_counter_pool {
512 TAILQ_ENTRY(mlx5_flow_counter_pool) next;
513 struct mlx5_counters counters; /* Free counter list. */
515 struct mlx5_devx_obj *min_dcs;
516 rte_atomic64_t a64_dcs;
518 /* The devx object of the minimum counter ID. */
519 rte_atomic64_t query_gen;
520 uint32_t n_counters: 16; /* Number of devx allocated counters. */
521 rte_spinlock_t sl; /* The pool lock. */
522 struct mlx5_counter_stats_raw *raw;
523 struct mlx5_counter_stats_raw *raw_hw; /* The raw on HW working. */
524 struct mlx5_flow_counter counters_raw[]; /* The pool counters memory. */
527 struct mlx5_counter_stats_raw;
529 /* Memory management structure for group of counter statistics raws. */
530 struct mlx5_counter_stats_mem_mng {
531 LIST_ENTRY(mlx5_counter_stats_mem_mng) next;
532 struct mlx5_counter_stats_raw *raws;
533 struct mlx5_devx_obj *dm;
534 struct mlx5dv_devx_umem *umem;
537 /* Raw memory structure for the counter statistics values of a pool. */
538 struct mlx5_counter_stats_raw {
539 LIST_ENTRY(mlx5_counter_stats_raw) next;
541 struct mlx5_counter_stats_mem_mng *mem_mng;
542 volatile struct flow_counter_stats *data;
545 TAILQ_HEAD(mlx5_counter_pools, mlx5_flow_counter_pool);
547 /* Container structure for counter pools. */
548 struct mlx5_pools_container {
549 rte_atomic16_t n_valid; /* Number of valid pools. */
550 uint16_t n; /* Number of pools. */
551 struct mlx5_counter_pools pool_list; /* Counter pool list. */
552 struct mlx5_flow_counter_pool **pools; /* Counter pool array. */
553 struct mlx5_counter_stats_mem_mng *init_mem_mng;
554 /* Hold the memory management for the next allocated pools raws. */
557 /* Counter global management structure. */
558 struct mlx5_flow_counter_mng {
559 uint8_t mhi[2]; /* master \ host container index. */
560 struct mlx5_pools_container ccont[2 * 2];
561 /* 2 containers for single and for batch for double-buffer. */
562 struct mlx5_counters flow_counters; /* Legacy flow counter list. */
563 uint8_t pending_queries;
566 uint8_t query_thread_on;
567 LIST_HEAD(mem_mngs, mlx5_counter_stats_mem_mng) mem_mngs;
568 LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws;
571 /* Per port data of shared IB device. */
572 struct mlx5_ibv_shared_port {
574 uint32_t devx_ih_port_id;
576 * Interrupt handler port_id. Used by shared interrupt
577 * handler to find the corresponding rte_eth device
578 * by IB port index. If value is equal or greater
579 * RTE_MAX_ETHPORTS it means there is no subhandler
580 * installed for specified IB port index.
584 /* Table key of the hash organization. */
585 union mlx5_flow_tbl_key {
587 /* Table ID should be at the lowest address. */
588 uint32_t table_id; /**< ID of the table. */
589 uint16_t reserved; /**< must be zero for comparison. */
590 uint8_t domain; /**< 1 - FDB, 0 - NIC TX/RX. */
591 uint8_t direction; /**< 1 - egress, 0 - ingress. */
593 uint64_t v64; /**< full 64bits value of key */
596 /* Table structure. */
597 struct mlx5_flow_tbl_resource {
598 void *obj; /**< Pointer to DR table object. */
599 rte_atomic32_t refcnt; /**< Reference counter. */
602 #define MLX5_MAX_TABLES UINT16_MAX
603 #define MLX5_FLOW_TABLE_LEVEL_METER (UINT16_MAX - 3)
604 #define MLX5_FLOW_TABLE_LEVEL_SUFFIX (UINT16_MAX - 2)
605 #define MLX5_HAIRPIN_TX_TABLE (UINT16_MAX - 1)
606 /* Reserve the last two tables for metadata register copy. */
607 #define MLX5_FLOW_MREG_ACT_TABLE_GROUP (MLX5_MAX_TABLES - 1)
608 #define MLX5_FLOW_MREG_CP_TABLE_GROUP (MLX5_MAX_TABLES - 2)
609 /* Tables for metering splits should be added here. */
610 #define MLX5_MAX_TABLES_EXTERNAL (MLX5_MAX_TABLES - 3)
611 #define MLX5_MAX_TABLES_FDB UINT16_MAX
613 #define MLX5_DBR_PAGE_SIZE 4096 /* Must be >= 512. */
614 #define MLX5_DBR_SIZE 8
615 #define MLX5_DBR_PER_PAGE (MLX5_DBR_PAGE_SIZE / MLX5_DBR_SIZE)
616 #define MLX5_DBR_BITMAP_SIZE (MLX5_DBR_PER_PAGE / 64)
618 struct mlx5_devx_dbr_page {
619 /* Door-bell records, must be first member in structure. */
620 uint8_t dbrs[MLX5_DBR_PAGE_SIZE];
621 LIST_ENTRY(mlx5_devx_dbr_page) next; /* Pointer to the next element. */
622 struct mlx5dv_devx_umem *umem;
623 uint32_t dbr_count; /* Number of door-bell records in use. */
624 /* 1 bit marks matching door-bell is in use. */
625 uint64_t dbr_bitmap[MLX5_DBR_BITMAP_SIZE];
628 /* ID generation structure. */
629 struct mlx5_flow_id_pool {
630 uint32_t *free_arr; /**< Pointer to the a array of free values. */
632 /**< The next index that can be used without any free elements. */
633 uint32_t *curr; /**< Pointer to the index to pop. */
634 uint32_t *last; /**< Pointer to the last element in the empty arrray. */
635 uint32_t max_id; /**< Maximum id can be allocated from the pool. */
639 * Shared Infiniband device context for Master/Representors
640 * which belong to same IB device with multiple IB ports.
642 struct mlx5_ibv_shared {
643 LIST_ENTRY(mlx5_ibv_shared) next;
645 uint32_t devx:1; /* Opened with DV. */
646 uint32_t max_port; /* Maximal IB device port index. */
647 struct ibv_context *ctx; /* Verbs/DV context. */
648 struct ibv_pd *pd; /* Protection Domain. */
649 uint32_t pdn; /* Protection Domain number. */
650 uint32_t tdn; /* Transport Domain number. */
651 char ibdev_name[IBV_SYSFS_NAME_MAX]; /* IB device name. */
652 char ibdev_path[IBV_SYSFS_PATH_MAX]; /* IB device path for secondary */
653 struct ibv_device_attr_ex device_attr; /* Device properties. */
654 LIST_ENTRY(mlx5_ibv_shared) mem_event_cb;
655 /**< Called by memory event callback. */
657 uint32_t dev_gen; /* Generation number to flush local caches. */
658 rte_rwlock_t rwlock; /* MR Lock. */
659 struct mlx5_mr_btree cache; /* Global MR cache table. */
660 struct mlx5_mr_list mr_list; /* Registered MR list. */
661 struct mlx5_mr_list mr_free_list; /* Freed MR list. */
663 /* Shared DV/DR flow data section. */
664 pthread_mutex_t dv_mutex; /* DV context mutex. */
665 uint32_t dv_meta_mask; /* flow META metadata supported mask. */
666 uint32_t dv_mark_mask; /* flow MARK metadata supported mask. */
667 uint32_t dv_regc0_mask; /* available bits of metatada reg_c[0]. */
668 uint32_t dv_refcnt; /* DV/DR data reference counter. */
669 void *fdb_domain; /* FDB Direct Rules name space handle. */
670 struct mlx5_flow_tbl_resource *fdb_mtr_sfx_tbl;
671 /* FDB meter suffix rules table. */
672 void *rx_domain; /* RX Direct Rules name space handle. */
673 struct mlx5_flow_tbl_resource *rx_mtr_sfx_tbl;
674 /* RX meter suffix rules table. */
675 void *tx_domain; /* TX Direct Rules name space handle. */
676 struct mlx5_flow_tbl_resource *tx_mtr_sfx_tbl;
677 /* TX meter suffix rules table. */
678 struct mlx5_hlist *flow_tbls;
679 /* Direct Rules tables for FDB, NIC TX+RX */
680 void *esw_drop_action; /* Pointer to DR E-Switch drop action. */
681 void *pop_vlan_action; /* Pointer to DR pop VLAN action. */
682 LIST_HEAD(encap_decap, mlx5_flow_dv_encap_decap_resource) encaps_decaps;
683 LIST_HEAD(modify_cmd, mlx5_flow_dv_modify_hdr_resource) modify_cmds;
684 struct mlx5_hlist *tag_table;
685 LIST_HEAD(port_id_action_list, mlx5_flow_dv_port_id_action_resource)
686 port_id_action_list; /* List of port ID actions. */
687 LIST_HEAD(push_vlan_action_list, mlx5_flow_dv_push_vlan_action_resource)
688 push_vlan_action_list; /* List of push VLAN actions. */
689 struct mlx5_flow_counter_mng cmng; /* Counters management structure. */
690 /* Shared interrupt handler section. */
691 pthread_mutex_t intr_mutex; /* Interrupt config mutex. */
692 uint32_t intr_cnt; /* Interrupt handler reference counter. */
693 struct rte_intr_handle intr_handle; /* Interrupt handler for device. */
694 uint32_t devx_intr_cnt; /* Devx interrupt handler reference counter. */
695 struct rte_intr_handle intr_handle_devx; /* DEVX interrupt handler. */
696 struct mlx5dv_devx_cmd_comp *devx_comp; /* DEVX async comp obj. */
697 struct mlx5_devx_obj *tis; /* TIS object. */
698 struct mlx5_devx_obj *td; /* Transport domain. */
699 struct mlx5_flow_id_pool *flow_id_pool; /* Flow ID pool. */
700 struct mlx5_ibv_shared_port port[]; /* per device port data array. */
703 /* Per-process private structure. */
704 struct mlx5_proc_priv {
706 /* Size of UAR register table. */
708 /* Table of UAR registers for each process. */
711 /* MTR profile list. */
712 TAILQ_HEAD(mlx5_mtr_profiles, mlx5_flow_meter_profile);
714 TAILQ_HEAD(mlx5_flow_meters, mlx5_flow_meter);
716 #define MLX5_PROC_PRIV(port_id) \
717 ((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private)
720 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */
721 struct mlx5_ibv_shared *sh; /* Shared IB device context. */
722 uint32_t ibv_port; /* IB device port number. */
723 struct rte_pci_device *pci_dev; /* Backend PCI device. */
724 struct rte_ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */
725 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES);
726 /* Bit-field of MAC addresses owned by the PMD. */
727 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */
728 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */
729 /* Device properties. */
730 uint16_t mtu; /* Configured MTU. */
731 unsigned int isolated:1; /* Whether isolated mode is enabled. */
732 unsigned int representor:1; /* Device is a port representor. */
733 unsigned int master:1; /* Device is a E-Switch master. */
734 unsigned int dr_shared:1; /* DV/DR data is shared. */
735 unsigned int counter_fallback:1; /* Use counter fallback management. */
736 unsigned int mtr_en:1; /* Whether support meter. */
737 unsigned int mtr_reg_share:1; /* Whether support meter REG_C share. */
738 uint16_t domain_id; /* Switch domain identifier. */
739 uint16_t vport_id; /* Associated VF vport index (if any). */
740 uint32_t vport_meta_tag; /* Used for vport index match ove VF LAG. */
741 uint32_t vport_meta_mask; /* Used for vport index field match mask. */
742 int32_t representor_id; /* Port representor identifier. */
743 int32_t pf_bond; /* >=0 means PF index in bonding configuration. */
744 unsigned int if_index; /* Associated kernel network device index. */
746 unsigned int rxqs_n; /* RX queues array size. */
747 unsigned int txqs_n; /* TX queues array size. */
748 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */
749 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */
750 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
751 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */
752 unsigned int (*reta_idx)[]; /* RETA index table. */
753 unsigned int reta_idx_n; /* RETA index size. */
754 struct mlx5_drop drop_queue; /* Flow drop queues. */
755 struct mlx5_flows flows; /* RTE Flow rules. */
756 struct mlx5_flows ctrl_flows; /* Control flow rules. */
757 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */
758 LIST_HEAD(rxqobj, mlx5_rxq_obj) rxqsobj; /* Verbs/DevX Rx queues. */
759 LIST_HEAD(hrxq, mlx5_hrxq) hrxqs; /* Verbs Hash Rx queues. */
760 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */
761 LIST_HEAD(txqobj, mlx5_txq_obj) txqsobj; /* Verbs/DevX Tx queues. */
762 /* Indirection tables. */
763 LIST_HEAD(ind_tables, mlx5_ind_table_obj) ind_tbls;
764 /* Pointer to next element. */
765 rte_atomic32_t refcnt; /**< Reference counter. */
766 struct ibv_flow_action *verbs_action;
767 /**< Verbs modify header action object. */
768 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
769 uint8_t max_lro_msg_size;
770 /* Tags resources cache. */
771 uint32_t link_speed_capa; /* Link speed capabilities. */
772 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */
773 struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */
774 struct mlx5_dev_config config; /* Device configuration. */
775 struct mlx5_verbs_alloc_ctx verbs_alloc_ctx;
776 /* Context for Verbs allocator. */
777 int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */
778 int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */
779 uint32_t nl_sn; /* Netlink message sequence number. */
780 LIST_HEAD(dbrpage, mlx5_devx_dbr_page) dbrpgs; /* Door-bell pages. */
781 struct mlx5_vlan_vmwa_context *vmwa_context; /* VLAN WA context. */
782 struct mlx5_flow_id_pool *qrss_id_pool;
783 struct mlx5_hlist *mreg_cp_tbl;
784 /* Hash table of Rx metadata register copy table. */
785 uint8_t mtr_sfx_reg; /* Meter prefix-suffix flow match REG_C. */
786 uint8_t mtr_color_reg; /* Meter color match REG_C. */
787 struct mlx5_mtr_profiles flow_meter_profiles; /* MTR profile list. */
788 struct mlx5_flow_meters flow_meters; /* MTR list. */
790 rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */
791 rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX];
792 /* UAR same-page access control required in 32bit implementations. */
794 uint8_t skip_default_rss_reta; /* Skip configuration of default reta. */
797 #define PORT_ID(priv) ((priv)->dev_data->port_id)
798 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)])
802 int mlx5_getenv_int(const char *);
803 int mlx5_proc_priv_init(struct rte_eth_dev *dev);
804 int64_t mlx5_get_dbr(struct rte_eth_dev *dev,
805 struct mlx5_devx_dbr_page **dbr_page);
806 int32_t mlx5_release_dbr(struct rte_eth_dev *dev, uint32_t umem_id,
808 int mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev,
809 struct rte_eth_udp_tunnel *udp_tunnel);
810 uint16_t mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev);
812 /* Macro to iterate over all valid ports for mlx5 driver. */
813 #define MLX5_ETH_FOREACH_DEV(port_id, pci_dev) \
814 for (port_id = mlx5_eth_find_next(0, pci_dev); \
815 port_id < RTE_MAX_ETHPORTS; \
816 port_id = mlx5_eth_find_next(port_id + 1, pci_dev))
820 int mlx5_get_ifname(const struct rte_eth_dev *dev, char (*ifname)[IF_NAMESIZE]);
821 int mlx5_get_master_ifname(const char *ibdev_path, char (*ifname)[IF_NAMESIZE]);
822 unsigned int mlx5_ifindex(const struct rte_eth_dev *dev);
823 int mlx5_ifreq(const struct rte_eth_dev *dev, int req, struct ifreq *ifr);
824 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu);
825 int mlx5_set_flags(struct rte_eth_dev *dev, unsigned int keep,
827 int mlx5_dev_configure(struct rte_eth_dev *dev);
828 int mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info);
829 int mlx5_read_clock(struct rte_eth_dev *dev, uint64_t *clock);
830 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size);
831 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev);
832 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete);
833 int mlx5_force_link_status_change(struct rte_eth_dev *dev, int status);
834 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
835 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev,
836 struct rte_eth_fc_conf *fc_conf);
837 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev,
838 struct rte_eth_fc_conf *fc_conf);
839 int mlx5_dev_to_pci_addr(const char *dev_path,
840 struct rte_pci_addr *pci_addr);
841 void mlx5_dev_link_status_handler(void *arg);
842 void mlx5_dev_interrupt_handler(void *arg);
843 void mlx5_dev_interrupt_handler_devx(void *arg);
844 void mlx5_dev_interrupt_handler_uninstall(struct rte_eth_dev *dev);
845 void mlx5_dev_interrupt_handler_install(struct rte_eth_dev *dev);
846 void mlx5_dev_interrupt_handler_devx_uninstall(struct rte_eth_dev *dev);
847 void mlx5_dev_interrupt_handler_devx_install(struct rte_eth_dev *dev);
848 int mlx5_set_link_down(struct rte_eth_dev *dev);
849 int mlx5_set_link_up(struct rte_eth_dev *dev);
850 int mlx5_is_removed(struct rte_eth_dev *dev);
851 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev);
852 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev);
853 struct mlx5_priv *mlx5_port_to_eswitch_info(uint16_t port, bool valid);
854 struct mlx5_priv *mlx5_dev_to_eswitch_info(struct rte_eth_dev *dev);
855 int mlx5_sysfs_switch_info(unsigned int ifindex,
856 struct mlx5_switch_info *info);
857 void mlx5_sysfs_check_switch_info(bool device_dir,
858 struct mlx5_switch_info *switch_info);
859 void mlx5_nl_check_switch_info(bool nun_vf_set,
860 struct mlx5_switch_info *switch_info);
861 void mlx5_translate_port_name(const char *port_name_in,
862 struct mlx5_switch_info *port_info_out);
863 void mlx5_intr_callback_unregister(const struct rte_intr_handle *handle,
864 rte_intr_callback_fn cb_fn, void *cb_arg);
865 int mlx5_get_module_info(struct rte_eth_dev *dev,
866 struct rte_eth_dev_module_info *modinfo);
867 int mlx5_get_module_eeprom(struct rte_eth_dev *dev,
868 struct rte_dev_eeprom_info *info);
869 int mlx5_hairpin_cap_get(struct rte_eth_dev *dev,
870 struct rte_eth_hairpin_cap *cap);
871 int mlx5_dev_configure_rss_reta(struct rte_eth_dev *dev);
875 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]);
876 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
877 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
878 uint32_t index, uint32_t vmdq);
879 int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr);
880 int mlx5_set_mc_addr_list(struct rte_eth_dev *dev,
881 struct rte_ether_addr *mc_addr_set,
882 uint32_t nb_mc_addr);
886 int mlx5_rss_hash_update(struct rte_eth_dev *dev,
887 struct rte_eth_rss_conf *rss_conf);
888 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev,
889 struct rte_eth_rss_conf *rss_conf);
890 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size);
891 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev,
892 struct rte_eth_rss_reta_entry64 *reta_conf,
894 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev,
895 struct rte_eth_rss_reta_entry64 *reta_conf,
900 int mlx5_promiscuous_enable(struct rte_eth_dev *dev);
901 int mlx5_promiscuous_disable(struct rte_eth_dev *dev);
902 int mlx5_allmulticast_enable(struct rte_eth_dev *dev);
903 int mlx5_allmulticast_disable(struct rte_eth_dev *dev);
907 void mlx5_stats_init(struct rte_eth_dev *dev);
908 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
909 int mlx5_stats_reset(struct rte_eth_dev *dev);
910 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats,
912 int mlx5_xstats_reset(struct rte_eth_dev *dev);
913 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
914 struct rte_eth_xstat_name *xstats_names,
919 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
920 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on);
921 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask);
925 int mlx5_dev_start(struct rte_eth_dev *dev);
926 void mlx5_dev_stop(struct rte_eth_dev *dev);
927 int mlx5_traffic_enable(struct rte_eth_dev *dev);
928 void mlx5_traffic_disable(struct rte_eth_dev *dev);
929 int mlx5_traffic_restart(struct rte_eth_dev *dev);
933 int mlx5_flow_discover_mreg_c(struct rte_eth_dev *eth_dev);
934 bool mlx5_flow_ext_mreg_supported(struct rte_eth_dev *dev);
935 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
936 void mlx5_flow_print(struct rte_flow *flow);
937 int mlx5_flow_validate(struct rte_eth_dev *dev,
938 const struct rte_flow_attr *attr,
939 const struct rte_flow_item items[],
940 const struct rte_flow_action actions[],
941 struct rte_flow_error *error);
942 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev,
943 const struct rte_flow_attr *attr,
944 const struct rte_flow_item items[],
945 const struct rte_flow_action actions[],
946 struct rte_flow_error *error);
947 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow,
948 struct rte_flow_error *error);
949 void mlx5_flow_list_flush(struct rte_eth_dev *dev, struct mlx5_flows *list);
950 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error);
951 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow,
952 const struct rte_flow_action *action, void *data,
953 struct rte_flow_error *error);
954 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable,
955 struct rte_flow_error *error);
956 int mlx5_dev_filter_ctrl(struct rte_eth_dev *dev,
957 enum rte_filter_type filter_type,
958 enum rte_filter_op filter_op,
960 int mlx5_flow_start(struct rte_eth_dev *dev, struct mlx5_flows *list);
961 void mlx5_flow_stop(struct rte_eth_dev *dev, struct mlx5_flows *list);
962 int mlx5_flow_verify(struct rte_eth_dev *dev);
963 int mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, uint32_t queue);
964 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev,
965 struct rte_flow_item_eth *eth_spec,
966 struct rte_flow_item_eth *eth_mask,
967 struct rte_flow_item_vlan *vlan_spec,
968 struct rte_flow_item_vlan *vlan_mask);
969 int mlx5_ctrl_flow(struct rte_eth_dev *dev,
970 struct rte_flow_item_eth *eth_spec,
971 struct rte_flow_item_eth *eth_mask);
972 struct rte_flow *mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev);
973 int mlx5_flow_create_drop_queue(struct rte_eth_dev *dev);
974 void mlx5_flow_delete_drop_queue(struct rte_eth_dev *dev);
975 void mlx5_flow_async_pool_query_handle(struct mlx5_ibv_shared *sh,
976 uint64_t async_id, int status);
977 void mlx5_set_query_alarm(struct mlx5_ibv_shared *sh);
978 void mlx5_flow_query_alarm(void *arg);
979 struct mlx5_flow_counter *mlx5_counter_alloc(struct rte_eth_dev *dev);
980 void mlx5_counter_free(struct rte_eth_dev *dev, struct mlx5_flow_counter *cnt);
981 int mlx5_counter_query(struct rte_eth_dev *dev, struct mlx5_flow_counter *cnt,
982 bool clear, uint64_t *pkts, uint64_t *bytes);
983 int mlx5_flow_dev_dump(struct rte_eth_dev *dev, FILE *file,
984 struct rte_flow_error *error);
987 void mlx5_mp_req_start_rxtx(struct rte_eth_dev *dev);
988 void mlx5_mp_req_stop_rxtx(struct rte_eth_dev *dev);
989 int mlx5_mp_req_mr_create(struct rte_eth_dev *dev, uintptr_t addr);
990 int mlx5_mp_req_verbs_cmd_fd(struct rte_eth_dev *dev);
991 int mlx5_mp_req_queue_state_modify(struct rte_eth_dev *dev,
992 struct mlx5_mp_arg_queue_state_modify *sm);
993 int mlx5_mp_init_primary(void);
994 void mlx5_mp_uninit_primary(void);
995 int mlx5_mp_init_secondary(void);
996 void mlx5_mp_uninit_secondary(void);
1000 int mlx5_pmd_socket_init(void);
1001 void mlx5_pmd_socket_uninit(void);
1005 int mlx5_nl_init(int protocol);
1006 int mlx5_nl_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
1008 int mlx5_nl_mac_addr_remove(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
1010 void mlx5_nl_mac_addr_sync(struct rte_eth_dev *dev);
1011 void mlx5_nl_mac_addr_flush(struct rte_eth_dev *dev);
1012 int mlx5_nl_promisc(struct rte_eth_dev *dev, int enable);
1013 int mlx5_nl_allmulti(struct rte_eth_dev *dev, int enable);
1014 unsigned int mlx5_nl_portnum(int nl, const char *name);
1015 unsigned int mlx5_nl_ifindex(int nl, const char *name, uint32_t pindex);
1016 int mlx5_nl_vf_mac_addr_modify(struct rte_eth_dev *dev,
1017 struct rte_ether_addr *mac, int vf_index);
1018 int mlx5_nl_switch_info(int nl, unsigned int ifindex,
1019 struct mlx5_switch_info *info);
1021 struct mlx5_vlan_vmwa_context *mlx5_vlan_vmwa_init(struct rte_eth_dev *dev,
1023 void mlx5_vlan_vmwa_exit(struct mlx5_vlan_vmwa_context *ctx);
1024 void mlx5_vlan_vmwa_release(struct rte_eth_dev *dev,
1025 struct mlx5_vf_vlan *vf_vlan);
1026 void mlx5_vlan_vmwa_acquire(struct rte_eth_dev *dev,
1027 struct mlx5_vf_vlan *vf_vlan);
1029 /* mlx5_devx_cmds.c */
1031 struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(struct ibv_context *ctx,
1033 int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj);
1034 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
1035 int clear, uint32_t n_counters,
1036 uint64_t *pkts, uint64_t *bytes,
1037 uint32_t mkey, void *addr,
1038 struct mlx5dv_devx_cmd_comp *cmd_comp,
1040 int mlx5_devx_cmd_query_hca_attr(struct ibv_context *ctx,
1041 struct mlx5_hca_attr *attr);
1042 struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(struct ibv_context *ctx,
1043 struct mlx5_devx_mkey_attr *attr);
1044 int mlx5_devx_get_out_command_status(void *out);
1045 int mlx5_devx_cmd_qp_query_tis_td(struct ibv_qp *qp, uint32_t tis_num,
1047 struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(struct ibv_context *ctx,
1048 struct mlx5_devx_create_rq_attr *rq_attr,
1050 int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
1051 struct mlx5_devx_modify_rq_attr *rq_attr);
1052 struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(struct ibv_context *ctx,
1053 struct mlx5_devx_tir_attr *tir_attr);
1054 struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(struct ibv_context *ctx,
1055 struct mlx5_devx_rqt_attr *rqt_attr);
1056 struct mlx5_devx_obj *mlx5_devx_cmd_create_sq
1057 (struct ibv_context *ctx, struct mlx5_devx_create_sq_attr *sq_attr);
1058 int mlx5_devx_cmd_modify_sq
1059 (struct mlx5_devx_obj *sq, struct mlx5_devx_modify_sq_attr *sq_attr);
1060 struct mlx5_devx_obj *mlx5_devx_cmd_create_tis
1061 (struct ibv_context *ctx, struct mlx5_devx_tis_attr *tis_attr);
1062 struct mlx5_devx_obj *mlx5_devx_cmd_create_td(struct ibv_context *ctx);
1064 int mlx5_devx_cmd_flow_dump(struct mlx5_ibv_shared *sh, FILE *file);
1066 /* mlx5_flow_meter.c */
1068 int mlx5_flow_meter_ops_get(struct rte_eth_dev *dev, void *arg);
1069 struct mlx5_flow_meter *mlx5_flow_meter_find(struct mlx5_priv *priv,
1071 struct mlx5_flow_meter *mlx5_flow_meter_attach
1072 (struct mlx5_priv *priv,
1074 const struct rte_flow_attr *attr,
1075 struct rte_flow_error *error);
1076 void mlx5_flow_meter_detach(struct mlx5_flow_meter *fm);
1078 #endif /* RTE_PMD_MLX5_H_ */