1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_H_
7 #define RTE_PMD_MLX5_H_
14 #include <netinet/in.h>
15 #include <sys/queue.h>
18 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
20 #pragma GCC diagnostic ignored "-Wpedantic"
22 #include <infiniband/verbs.h>
24 #pragma GCC diagnostic error "-Wpedantic"
28 #include <rte_ether.h>
29 #include <rte_ethdev_driver.h>
30 #include <rte_rwlock.h>
31 #include <rte_interrupts.h>
32 #include <rte_errno.h>
35 #include "mlx5_utils.h"
37 #include "mlx5_autoconf.h"
38 #include "mlx5_defs.h"
41 PCI_VENDOR_ID_MELLANOX = 0x15b3,
45 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013,
46 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014,
47 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015,
48 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016,
49 PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017,
50 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018,
51 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019,
52 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a,
53 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF = 0xa2d2,
54 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF = 0xa2d3,
55 PCI_DEVICE_ID_MELLANOX_CONNECTX6 = 0x101b,
56 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF = 0x101c,
59 /* Request types for IPC. */
60 enum mlx5_mp_req_type {
61 MLX5_MP_REQ_VERBS_CMD_FD = 1,
62 MLX5_MP_REQ_CREATE_MR,
63 MLX5_MP_REQ_START_RXTX,
64 MLX5_MP_REQ_STOP_RXTX,
65 MLX5_MP_REQ_QUEUE_STATE_MODIFY,
68 struct mlx5_mp_arg_queue_state_modify {
69 uint8_t is_wq; /* Set if WQ. */
70 uint16_t queue_id; /* DPDK queue ID. */
71 enum ibv_wq_state state; /* WQ requested state. */
74 /* Pameters for IPC. */
75 struct mlx5_mp_param {
76 enum mlx5_mp_req_type type;
81 uintptr_t addr; /* MLX5_MP_REQ_CREATE_MR */
82 struct mlx5_mp_arg_queue_state_modify state_modify;
83 /* MLX5_MP_REQ_QUEUE_STATE_MODIFY */
87 /** Request timeout for IPC. */
88 #define MLX5_MP_REQ_TIMEOUT_SEC 5
90 /** Key string for IPC. */
91 #define MLX5_MP_NAME "net_mlx5_mp"
93 /* Recognized Infiniband device physical port name types. */
94 enum mlx5_phys_port_name_type {
95 MLX5_PHYS_PORT_NAME_TYPE_NOTSET = 0, /* Not set. */
96 MLX5_PHYS_PORT_NAME_TYPE_LEGACY, /* before kernel ver < 5.0 */
97 MLX5_PHYS_PORT_NAME_TYPE_UPLINK, /* p0, kernel ver >= 5.0 */
98 MLX5_PHYS_PORT_NAME_TYPE_PFVF, /* pf0vf0, kernel ver >= 5.0 */
99 MLX5_PHYS_PORT_NAME_TYPE_UNKNOWN, /* Unrecognized. */
102 /** Switch information returned by mlx5_nl_switch_info(). */
103 struct mlx5_switch_info {
104 uint32_t master:1; /**< Master device. */
105 uint32_t representor:1; /**< Representor device. */
106 enum mlx5_phys_port_name_type name_type; /** < Port name type. */
107 int32_t pf_num; /**< PF number (valid for pfxvfx format only). */
108 int32_t port_name; /**< Representor port name. */
109 uint64_t switch_id; /**< Switch identifier. */
112 LIST_HEAD(mlx5_dev_list, mlx5_ibv_shared);
114 /* Shared data between primary and secondary processes. */
115 struct mlx5_shared_data {
117 /* Global spinlock for primary and secondary processes. */
118 int init_done; /* Whether primary has done initialization. */
119 unsigned int secondary_cnt; /* Number of secondary processes init'd. */
120 struct mlx5_dev_list mem_event_cb_list;
121 rte_rwlock_t mem_event_rwlock;
124 /* Per-process data structure, not visible to other processes. */
125 struct mlx5_local_data {
126 int init_done; /* Whether a secondary has done initialization. */
129 extern struct mlx5_shared_data *mlx5_shared_data;
131 struct mlx5_counter_ctrl {
132 /* Name of the counter. */
133 char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE];
134 /* Name of the counter on the device table. */
135 char ctr_name[RTE_ETH_XSTATS_NAME_SIZE];
136 uint32_t ib:1; /**< Nonzero for IB counters. */
139 struct mlx5_xstats_ctrl {
140 /* Number of device stats. */
142 /* Number of device stats identified by PMD. */
143 uint16_t mlx5_stats_n;
144 /* Index in the device counters table. */
145 uint16_t dev_table_idx[MLX5_MAX_XSTATS];
146 uint64_t base[MLX5_MAX_XSTATS];
147 struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS];
150 struct mlx5_stats_ctrl {
151 /* Base for imissed counter. */
152 uint64_t imissed_base;
155 /* devx counter object */
156 struct mlx5_devx_counter_set {
157 struct mlx5dv_devx_obj *obj;
158 int id; /* Flow counter ID */
161 /* HCA attributes. */
162 struct mlx5_hca_attr {
163 uint32_t eswitch_manager:1;
167 TAILQ_HEAD(mlx5_flows, rte_flow);
169 /* Default PMD specific parameter value. */
170 #define MLX5_ARG_UNSET (-1)
173 * Device configuration structure.
175 * Merged configuration from:
177 * - Device capabilities,
178 * - User device parameters disabled features.
180 struct mlx5_dev_config {
181 unsigned int hw_csum:1; /* Checksum offload is supported. */
182 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */
183 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */
184 unsigned int hw_padding:1; /* End alignment padding is supported. */
185 unsigned int vf:1; /* This is a VF. */
186 unsigned int tunnel_en:1;
187 /* Whether tunnel stateless offloads are supported. */
188 unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */
189 unsigned int cqe_comp:1; /* CQE compression is enabled. */
190 unsigned int cqe_pad:1; /* CQE padding is enabled. */
191 unsigned int tso:1; /* Whether TSO is supported. */
192 unsigned int tx_vec_en:1; /* Tx vector is enabled. */
193 unsigned int rx_vec_en:1; /* Rx vector is enabled. */
194 unsigned int mpw_hdr_dseg:1; /* Enable DSEGs in the title WQEBB. */
195 unsigned int mr_ext_memseg_en:1;
196 /* Whether memseg should be extended for MR creation. */
197 unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */
198 unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */
199 unsigned int dv_esw_en:1; /* Enable E-Switch DV flow. */
200 unsigned int dv_flow_en:1; /* Enable DV flow. */
201 unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */
202 unsigned int devx:1; /* Whether devx interface is available or not. */
204 unsigned int enabled:1; /* Whether MPRQ is enabled. */
205 unsigned int stride_num_n; /* Number of strides. */
206 unsigned int min_stride_size_n; /* Min size of a stride. */
207 unsigned int max_stride_size_n; /* Max size of a stride. */
208 unsigned int max_memcpy_len;
209 /* Maximum packet size to memcpy Rx packets. */
210 unsigned int min_rxqs_num;
211 /* Rx queue count threshold to enable MPRQ. */
212 } mprq; /* Configurations for Multi-Packet RQ. */
213 int mps; /* Multi-packet send supported mode. */
214 unsigned int flow_prio; /* Number of flow priorities. */
215 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */
216 unsigned int ind_table_max_size; /* Maximum indirection table size. */
217 unsigned int max_dump_files_num; /* Maximum dump files per queue. */
218 int txq_inline; /* Maximum packet size for inlining. */
219 int txqs_inline; /* Queue number threshold for inlining. */
220 int txqs_vec; /* Queue number threshold for vectorized Tx. */
221 int inline_max_packet_sz; /* Max packet size for inlining. */
222 struct mlx5_hca_attr hca_attr; /* HCA attributes. */
226 * Type of objet being allocated.
228 enum mlx5_verbs_alloc_type {
229 MLX5_VERBS_ALLOC_TYPE_NONE,
230 MLX5_VERBS_ALLOC_TYPE_TX_QUEUE,
231 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE,
235 * Verbs allocator needs a context to know in the callback which kind of
236 * resources it is allocating.
238 struct mlx5_verbs_alloc_ctx {
239 enum mlx5_verbs_alloc_type type; /* Kind of object being allocated. */
240 const void *obj; /* Pointer to the DPDK object. */
243 LIST_HEAD(mlx5_mr_list, mlx5_mr);
245 /* Flow drop context necessary due to Verbs API. */
247 struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */
248 struct mlx5_rxq_ibv *rxq; /* Verbs Rx queue. */
251 /* Per port data of shared IB device. */
252 struct mlx5_ibv_shared_port {
255 * Interrupt handler port_id. Used by shared interrupt
256 * handler to find the corresponding rte_eth device
257 * by IB port index. If value is equal or greater
258 * RTE_MAX_ETHPORTS it means there is no subhandler
259 * installed for specified IB port index.
263 /* Table structure. */
264 struct mlx5_flow_tbl_resource {
265 void *obj; /**< Pointer to DR table object. */
266 rte_atomic32_t refcnt; /**< Reference counter. */
269 #define MLX5_MAX_TABLES 1024
270 #define MLX5_MAX_TABLES_FDB 32
271 #define MLX5_GROUP_FACTOR 1
274 * Shared Infiniband device context for Master/Representors
275 * which belong to same IB device with multiple IB ports.
277 struct mlx5_ibv_shared {
278 LIST_ENTRY(mlx5_ibv_shared) next;
280 uint32_t devx:1; /* Opened with DV. */
281 uint32_t max_port; /* Maximal IB device port index. */
282 struct ibv_context *ctx; /* Verbs/DV context. */
283 struct ibv_pd *pd; /* Protection Domain. */
284 char ibdev_name[IBV_SYSFS_NAME_MAX]; /* IB device name. */
285 char ibdev_path[IBV_SYSFS_PATH_MAX]; /* IB device path for secondary */
286 struct ibv_device_attr_ex device_attr; /* Device properties. */
287 struct rte_pci_device *pci_dev; /* Backend PCI device. */
288 LIST_ENTRY(mlx5_ibv_shared) mem_event_cb;
289 /**< Called by memory event callback. */
291 uint32_t dev_gen; /* Generation number to flush local caches. */
292 rte_rwlock_t rwlock; /* MR Lock. */
293 struct mlx5_mr_btree cache; /* Global MR cache table. */
294 struct mlx5_mr_list mr_list; /* Registered MR list. */
295 struct mlx5_mr_list mr_free_list; /* Freed MR list. */
297 /* Shared DV/DR flow data section. */
298 pthread_mutex_t dv_mutex; /* DV context mutex. */
299 uint32_t dv_refcnt; /* DV/DR data reference counter. */
300 void *fdb_domain; /* FDB Direct Rules name space handle. */
301 struct mlx5_flow_tbl_resource fdb_tbl[MLX5_MAX_TABLES_FDB];
302 /* FDB Direct Rules tables. */
303 void *rx_domain; /* RX Direct Rules name space handle. */
304 struct mlx5_flow_tbl_resource rx_tbl[MLX5_MAX_TABLES];
305 /* RX Direct Rules tables. */
306 void *tx_domain; /* TX Direct Rules name space handle. */
307 struct mlx5_flow_tbl_resource tx_tbl[MLX5_MAX_TABLES];
308 void *esw_drop_action; /* Pointer to DR E-Switch drop action. */
309 /* TX Direct Rules tables/ */
310 LIST_HEAD(matchers, mlx5_flow_dv_matcher) matchers;
311 LIST_HEAD(encap_decap, mlx5_flow_dv_encap_decap_resource) encaps_decaps;
312 LIST_HEAD(modify_cmd, mlx5_flow_dv_modify_hdr_resource) modify_cmds;
313 LIST_HEAD(tag, mlx5_flow_dv_tag_resource) tags;
314 LIST_HEAD(jump, mlx5_flow_dv_jump_tbl_resource) jump_tbl;
315 LIST_HEAD(port_id_action_list, mlx5_flow_dv_port_id_action_resource)
316 port_id_action_list; /* List of port ID actions. */
317 /* Shared interrupt handler section. */
318 pthread_mutex_t intr_mutex; /* Interrupt config mutex. */
319 uint32_t intr_cnt; /* Interrupt handler reference counter. */
320 struct rte_intr_handle intr_handle; /* Interrupt handler for device. */
321 struct mlx5_ibv_shared_port port[]; /* per device port data array. */
324 /* Per-process private structure. */
325 struct mlx5_proc_priv {
327 /* Size of UAR register table. */
329 /* Table of UAR registers for each process. */
332 #define MLX5_PROC_PRIV(port_id) \
333 ((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private)
336 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */
337 struct mlx5_ibv_shared *sh; /* Shared IB device context. */
338 uint32_t ibv_port; /* IB device port number. */
339 struct rte_ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */
340 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES);
341 /* Bit-field of MAC addresses owned by the PMD. */
342 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */
343 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */
344 /* Device properties. */
345 uint16_t mtu; /* Configured MTU. */
346 unsigned int isolated:1; /* Whether isolated mode is enabled. */
347 unsigned int representor:1; /* Device is a port representor. */
348 unsigned int master:1; /* Device is a E-Switch master. */
349 unsigned int dr_shared:1; /* DV/DR data is shared. */
350 uint16_t domain_id; /* Switch domain identifier. */
351 uint16_t vport_id; /* Associated VF vport index (if any). */
352 int32_t representor_id; /* Port representor identifier. */
354 unsigned int rxqs_n; /* RX queues array size. */
355 unsigned int txqs_n; /* TX queues array size. */
356 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */
357 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */
358 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
359 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */
360 unsigned int (*reta_idx)[]; /* RETA index table. */
361 unsigned int reta_idx_n; /* RETA index size. */
362 struct mlx5_drop drop_queue; /* Flow drop queues. */
363 struct mlx5_flows flows; /* RTE Flow rules. */
364 struct mlx5_flows ctrl_flows; /* Control flow rules. */
365 LIST_HEAD(counters, mlx5_flow_counter) flow_counters;
367 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */
368 LIST_HEAD(rxqibv, mlx5_rxq_ibv) rxqsibv; /* Verbs Rx queues. */
369 LIST_HEAD(hrxq, mlx5_hrxq) hrxqs; /* Verbs Hash Rx queues. */
370 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */
371 LIST_HEAD(txqibv, mlx5_txq_ibv) txqsibv; /* Verbs Tx queues. */
372 /* Verbs Indirection tables. */
373 LIST_HEAD(ind_tables, mlx5_ind_table_ibv) ind_tbls;
374 /* Pointer to next element. */
375 rte_atomic32_t refcnt; /**< Reference counter. */
376 struct ibv_flow_action *verbs_action;
377 /**< Verbs modify header action object. */
378 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
379 /* Tags resources cache. */
380 uint32_t link_speed_capa; /* Link speed capabilities. */
381 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */
382 struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */
383 struct mlx5_dev_config config; /* Device configuration. */
384 struct mlx5_verbs_alloc_ctx verbs_alloc_ctx;
385 /* Context for Verbs allocator. */
386 int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */
387 int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */
388 uint32_t nl_sn; /* Netlink message sequence number. */
390 rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */
391 rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX];
392 /* UAR same-page access control required in 32bit implementations. */
396 #define PORT_ID(priv) ((priv)->dev_data->port_id)
397 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)])
401 int mlx5_getenv_int(const char *);
402 int mlx5_proc_priv_init(struct rte_eth_dev *dev);
406 int mlx5_get_ifname(const struct rte_eth_dev *dev, char (*ifname)[IF_NAMESIZE]);
407 int mlx5_get_ifname_base(const struct rte_eth_dev *base,
408 const struct rte_eth_dev *dev,
409 char (*ifname)[IF_NAMESIZE]);
410 int mlx5_get_master_ifname(const char *ibdev_path, char (*ifname)[IF_NAMESIZE]);
411 unsigned int mlx5_ifindex(const struct rte_eth_dev *dev);
412 int mlx5_ifreq(const struct rte_eth_dev *dev, int req, struct ifreq *ifr);
413 int mlx5_ifreq_base(const struct rte_eth_dev *base,
414 const struct rte_eth_dev *dev,
415 int req, struct ifreq *ifr);
416 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu);
417 int mlx5_set_flags(struct rte_eth_dev *dev, unsigned int keep,
419 int mlx5_dev_configure(struct rte_eth_dev *dev);
420 void mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info);
421 int mlx5_read_clock(struct rte_eth_dev *dev, uint64_t *clock);
422 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size);
423 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev);
424 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete);
425 int mlx5_force_link_status_change(struct rte_eth_dev *dev, int status);
426 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
427 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev,
428 struct rte_eth_fc_conf *fc_conf);
429 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev,
430 struct rte_eth_fc_conf *fc_conf);
431 int mlx5_ibv_device_to_pci_addr(const struct ibv_device *device,
432 struct rte_pci_addr *pci_addr);
433 void mlx5_dev_link_status_handler(void *arg);
434 void mlx5_dev_interrupt_handler(void *arg);
435 void mlx5_dev_interrupt_handler_uninstall(struct rte_eth_dev *dev);
436 void mlx5_dev_interrupt_handler_install(struct rte_eth_dev *dev);
437 int mlx5_set_link_down(struct rte_eth_dev *dev);
438 int mlx5_set_link_up(struct rte_eth_dev *dev);
439 int mlx5_is_removed(struct rte_eth_dev *dev);
440 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev);
441 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev);
442 unsigned int mlx5_dev_to_port_id(const struct rte_device *dev,
444 unsigned int port_list_n);
445 int mlx5_port_to_eswitch_info(uint16_t port, uint16_t *es_domain_id,
446 uint16_t *es_port_id);
447 int mlx5_sysfs_switch_info(unsigned int ifindex,
448 struct mlx5_switch_info *info);
449 void mlx5_sysfs_check_switch_info(bool device_dir,
450 struct mlx5_switch_info *switch_info);
451 void mlx5_nl_check_switch_info(bool nun_vf_set,
452 struct mlx5_switch_info *switch_info);
453 void mlx5_translate_port_name(const char *port_name_in,
454 struct mlx5_switch_info *port_info_out);
455 void mlx5_intr_callback_unregister(const struct rte_intr_handle *handle,
456 rte_intr_callback_fn cb_fn, void *cb_arg);
460 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]);
461 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
462 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
463 uint32_t index, uint32_t vmdq);
464 int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr);
465 int mlx5_set_mc_addr_list(struct rte_eth_dev *dev,
466 struct rte_ether_addr *mc_addr_set,
467 uint32_t nb_mc_addr);
471 int mlx5_rss_hash_update(struct rte_eth_dev *dev,
472 struct rte_eth_rss_conf *rss_conf);
473 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev,
474 struct rte_eth_rss_conf *rss_conf);
475 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size);
476 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev,
477 struct rte_eth_rss_reta_entry64 *reta_conf,
479 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev,
480 struct rte_eth_rss_reta_entry64 *reta_conf,
485 void mlx5_promiscuous_enable(struct rte_eth_dev *dev);
486 void mlx5_promiscuous_disable(struct rte_eth_dev *dev);
487 void mlx5_allmulticast_enable(struct rte_eth_dev *dev);
488 void mlx5_allmulticast_disable(struct rte_eth_dev *dev);
492 void mlx5_stats_init(struct rte_eth_dev *dev);
493 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
494 void mlx5_stats_reset(struct rte_eth_dev *dev);
495 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats,
497 void mlx5_xstats_reset(struct rte_eth_dev *dev);
498 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
499 struct rte_eth_xstat_name *xstats_names,
504 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
505 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on);
506 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask);
510 int mlx5_dev_start(struct rte_eth_dev *dev);
511 void mlx5_dev_stop(struct rte_eth_dev *dev);
512 int mlx5_traffic_enable(struct rte_eth_dev *dev);
513 void mlx5_traffic_disable(struct rte_eth_dev *dev);
514 int mlx5_traffic_restart(struct rte_eth_dev *dev);
518 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
519 void mlx5_flow_print(struct rte_flow *flow);
520 int mlx5_flow_validate(struct rte_eth_dev *dev,
521 const struct rte_flow_attr *attr,
522 const struct rte_flow_item items[],
523 const struct rte_flow_action actions[],
524 struct rte_flow_error *error);
525 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev,
526 const struct rte_flow_attr *attr,
527 const struct rte_flow_item items[],
528 const struct rte_flow_action actions[],
529 struct rte_flow_error *error);
530 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow,
531 struct rte_flow_error *error);
532 void mlx5_flow_list_flush(struct rte_eth_dev *dev, struct mlx5_flows *list);
533 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error);
534 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow,
535 const struct rte_flow_action *action, void *data,
536 struct rte_flow_error *error);
537 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable,
538 struct rte_flow_error *error);
539 int mlx5_dev_filter_ctrl(struct rte_eth_dev *dev,
540 enum rte_filter_type filter_type,
541 enum rte_filter_op filter_op,
543 int mlx5_flow_start(struct rte_eth_dev *dev, struct mlx5_flows *list);
544 void mlx5_flow_stop(struct rte_eth_dev *dev, struct mlx5_flows *list);
545 int mlx5_flow_verify(struct rte_eth_dev *dev);
546 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev,
547 struct rte_flow_item_eth *eth_spec,
548 struct rte_flow_item_eth *eth_mask,
549 struct rte_flow_item_vlan *vlan_spec,
550 struct rte_flow_item_vlan *vlan_mask);
551 int mlx5_ctrl_flow(struct rte_eth_dev *dev,
552 struct rte_flow_item_eth *eth_spec,
553 struct rte_flow_item_eth *eth_mask);
554 int mlx5_flow_create_drop_queue(struct rte_eth_dev *dev);
555 void mlx5_flow_delete_drop_queue(struct rte_eth_dev *dev);
558 void mlx5_mp_req_start_rxtx(struct rte_eth_dev *dev);
559 void mlx5_mp_req_stop_rxtx(struct rte_eth_dev *dev);
560 int mlx5_mp_req_mr_create(struct rte_eth_dev *dev, uintptr_t addr);
561 int mlx5_mp_req_verbs_cmd_fd(struct rte_eth_dev *dev);
562 int mlx5_mp_req_queue_state_modify(struct rte_eth_dev *dev,
563 struct mlx5_mp_arg_queue_state_modify *sm);
564 int mlx5_mp_init_primary(void);
565 void mlx5_mp_uninit_primary(void);
566 int mlx5_mp_init_secondary(void);
567 void mlx5_mp_uninit_secondary(void);
571 int mlx5_nl_init(int protocol);
572 int mlx5_nl_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
574 int mlx5_nl_mac_addr_remove(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
576 void mlx5_nl_mac_addr_sync(struct rte_eth_dev *dev);
577 void mlx5_nl_mac_addr_flush(struct rte_eth_dev *dev);
578 int mlx5_nl_promisc(struct rte_eth_dev *dev, int enable);
579 int mlx5_nl_allmulti(struct rte_eth_dev *dev, int enable);
580 unsigned int mlx5_nl_portnum(int nl, const char *name);
581 unsigned int mlx5_nl_ifindex(int nl, const char *name, uint32_t pindex);
582 int mlx5_nl_switch_info(int nl, unsigned int ifindex,
583 struct mlx5_switch_info *info);
585 /* mlx5_devx_cmds.c */
587 int mlx5_devx_cmd_flow_counter_alloc(struct ibv_context *ctx,
588 struct mlx5_devx_counter_set *dcx);
589 int mlx5_devx_cmd_flow_counter_free(struct mlx5dv_devx_obj *obj);
590 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_counter_set *dcx,
592 uint64_t *pkts, uint64_t *bytes);
593 int mlx5_devx_cmd_query_hca_attr(struct ibv_context *ctx,
594 struct mlx5_hca_attr *attr);
595 #endif /* RTE_PMD_MLX5_H_ */