1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_H_
7 #define RTE_PMD_MLX5_H_
14 #include <netinet/in.h>
15 #include <sys/queue.h>
18 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
20 #pragma GCC diagnostic ignored "-Wpedantic"
22 #include <infiniband/verbs.h>
24 #pragma GCC diagnostic error "-Wpedantic"
28 #include <rte_ether.h>
29 #include <rte_ethdev_driver.h>
30 #include <rte_rwlock.h>
31 #include <rte_interrupts.h>
32 #include <rte_errno.h>
35 #include "mlx5_utils.h"
37 #include "mlx5_autoconf.h"
38 #include "mlx5_defs.h"
39 #include "mlx5_glue.h"
42 PCI_VENDOR_ID_MELLANOX = 0x15b3,
46 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013,
47 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014,
48 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015,
49 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016,
50 PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017,
51 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018,
52 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019,
53 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a,
54 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF = 0xa2d2,
55 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF = 0xa2d3,
56 PCI_DEVICE_ID_MELLANOX_CONNECTX6 = 0x101b,
57 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF = 0x101c,
60 /* Request types for IPC. */
61 enum mlx5_mp_req_type {
62 MLX5_MP_REQ_VERBS_CMD_FD = 1,
63 MLX5_MP_REQ_CREATE_MR,
64 MLX5_MP_REQ_START_RXTX,
65 MLX5_MP_REQ_STOP_RXTX,
66 MLX5_MP_REQ_QUEUE_STATE_MODIFY,
69 struct mlx5_mp_arg_queue_state_modify {
70 uint8_t is_wq; /* Set if WQ. */
71 uint16_t queue_id; /* DPDK queue ID. */
72 enum ibv_wq_state state; /* WQ requested state. */
75 /* Pameters for IPC. */
76 struct mlx5_mp_param {
77 enum mlx5_mp_req_type type;
82 uintptr_t addr; /* MLX5_MP_REQ_CREATE_MR */
83 struct mlx5_mp_arg_queue_state_modify state_modify;
84 /* MLX5_MP_REQ_QUEUE_STATE_MODIFY */
88 /** Request timeout for IPC. */
89 #define MLX5_MP_REQ_TIMEOUT_SEC 5
91 /** Key string for IPC. */
92 #define MLX5_MP_NAME "net_mlx5_mp"
94 /* Recognized Infiniband device physical port name types. */
95 enum mlx5_phys_port_name_type {
96 MLX5_PHYS_PORT_NAME_TYPE_NOTSET = 0, /* Not set. */
97 MLX5_PHYS_PORT_NAME_TYPE_LEGACY, /* before kernel ver < 5.0 */
98 MLX5_PHYS_PORT_NAME_TYPE_UPLINK, /* p0, kernel ver >= 5.0 */
99 MLX5_PHYS_PORT_NAME_TYPE_PFVF, /* pf0vf0, kernel ver >= 5.0 */
100 MLX5_PHYS_PORT_NAME_TYPE_UNKNOWN, /* Unrecognized. */
103 /** Switch information returned by mlx5_nl_switch_info(). */
104 struct mlx5_switch_info {
105 uint32_t master:1; /**< Master device. */
106 uint32_t representor:1; /**< Representor device. */
107 enum mlx5_phys_port_name_type name_type; /** < Port name type. */
108 int32_t pf_num; /**< PF number (valid for pfxvfx format only). */
109 int32_t port_name; /**< Representor port name. */
110 uint64_t switch_id; /**< Switch identifier. */
113 LIST_HEAD(mlx5_dev_list, mlx5_ibv_shared);
115 /* Shared data between primary and secondary processes. */
116 struct mlx5_shared_data {
118 /* Global spinlock for primary and secondary processes. */
119 int init_done; /* Whether primary has done initialization. */
120 unsigned int secondary_cnt; /* Number of secondary processes init'd. */
121 struct mlx5_dev_list mem_event_cb_list;
122 rte_rwlock_t mem_event_rwlock;
125 /* Per-process data structure, not visible to other processes. */
126 struct mlx5_local_data {
127 int init_done; /* Whether a secondary has done initialization. */
130 extern struct mlx5_shared_data *mlx5_shared_data;
132 struct mlx5_counter_ctrl {
133 /* Name of the counter. */
134 char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE];
135 /* Name of the counter on the device table. */
136 char ctr_name[RTE_ETH_XSTATS_NAME_SIZE];
137 uint32_t ib:1; /**< Nonzero for IB counters. */
140 struct mlx5_xstats_ctrl {
141 /* Number of device stats. */
143 /* Number of device stats identified by PMD. */
144 uint16_t mlx5_stats_n;
145 /* Index in the device counters table. */
146 uint16_t dev_table_idx[MLX5_MAX_XSTATS];
147 uint64_t base[MLX5_MAX_XSTATS];
148 struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS];
151 struct mlx5_stats_ctrl {
152 /* Base for imissed counter. */
153 uint64_t imissed_base;
156 /* devX creation object */
157 struct mlx5_devx_obj {
158 struct mlx5dv_devx_obj *obj; /* The DV object. */
159 int id; /* The object ID. */
162 struct mlx5_devx_mkey_attr {
169 /* HCA supports this number of time periods for LRO. */
170 #define MLX5_LRO_NUM_SUPP_PERIODS 4
172 /* HCA attributes. */
173 struct mlx5_hca_attr {
174 uint32_t eswitch_manager:1;
175 uint32_t flow_counters_dump:1;
176 uint8_t flow_counter_bulk_alloc_bitmap;
177 uint32_t eth_net_offloads:1;
179 uint32_t wqe_vlan_insert:1;
180 uint32_t wqe_inline_mode:2;
181 uint32_t vport_inline_mode:3;
183 uint32_t tunnel_lro_gre:1;
184 uint32_t tunnel_lro_vxlan:1;
185 uint32_t lro_max_msg_sz_mode:2;
186 uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS];
190 TAILQ_HEAD(mlx5_flows, rte_flow);
192 /* Default PMD specific parameter value. */
193 #define MLX5_ARG_UNSET (-1)
195 #define MLX5_LRO_SUPPORTED(dev) \
196 (((struct mlx5_priv *)((dev)->data->dev_private))->config.lro.supported)
198 #define MLX5_LRO_ENABLED(dev) \
199 ((dev)->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO)
201 /* LRO configurations structure. */
202 struct mlx5_lro_config {
203 uint32_t supported:1; /* Whether LRO is supported. */
204 uint32_t timeout; /* User configuration. */
208 * Device configuration structure.
210 * Merged configuration from:
212 * - Device capabilities,
213 * - User device parameters disabled features.
215 struct mlx5_dev_config {
216 unsigned int hw_csum:1; /* Checksum offload is supported. */
217 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */
218 unsigned int hw_vlan_insert:1; /* VLAN insertion in WQE is supported. */
219 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */
220 unsigned int hw_padding:1; /* End alignment padding is supported. */
221 unsigned int vf:1; /* This is a VF. */
222 unsigned int tunnel_en:1;
223 /* Whether tunnel stateless offloads are supported. */
224 unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */
225 unsigned int cqe_comp:1; /* CQE compression is enabled. */
226 unsigned int cqe_pad:1; /* CQE padding is enabled. */
227 unsigned int tso:1; /* Whether TSO is supported. */
228 unsigned int rx_vec_en:1; /* Rx vector is enabled. */
229 unsigned int mr_ext_memseg_en:1;
230 /* Whether memseg should be extended for MR creation. */
231 unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */
232 unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */
233 unsigned int dv_esw_en:1; /* Enable E-Switch DV flow. */
234 unsigned int dv_flow_en:1; /* Enable DV flow. */
235 unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */
236 unsigned int devx:1; /* Whether devx interface is available or not. */
237 unsigned int dest_tir:1; /* Whether advanced DR API is available. */
239 unsigned int enabled:1; /* Whether MPRQ is enabled. */
240 unsigned int stride_num_n; /* Number of strides. */
241 unsigned int min_stride_size_n; /* Min size of a stride. */
242 unsigned int max_stride_size_n; /* Max size of a stride. */
243 unsigned int max_memcpy_len;
244 /* Maximum packet size to memcpy Rx packets. */
245 unsigned int min_rxqs_num;
246 /* Rx queue count threshold to enable MPRQ. */
247 } mprq; /* Configurations for Multi-Packet RQ. */
248 int mps; /* Multi-packet send supported mode. */
249 unsigned int flow_prio; /* Number of flow priorities. */
250 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */
251 unsigned int ind_table_max_size; /* Maximum indirection table size. */
252 unsigned int max_dump_files_num; /* Maximum dump files per queue. */
253 int txqs_inline; /* Queue number threshold for inlining. */
254 int txq_inline_min; /* Minimal amount of data bytes to inline. */
255 int txq_inline_max; /* Max packet size for inlining with SEND. */
256 int txq_inline_mpw; /* Max packet size for inlining with eMPW. */
257 struct mlx5_hca_attr hca_attr; /* HCA attributes. */
258 struct mlx5_lro_config lro; /* LRO configuration. */
261 struct mlx5_devx_wq_attr {
263 uint32_t wq_signature:1;
264 uint32_t end_padding_mode:2;
266 uint32_t hds_skip_first_sge:1;
267 uint32_t log2_hds_buf_size:3;
268 uint32_t page_offset:5;
271 uint32_t uar_page:24;
275 uint32_t log_wq_stride:4;
276 uint32_t log_wq_pg_sz:5;
277 uint32_t log_wq_sz:5;
278 uint32_t dbr_umem_valid:1;
279 uint32_t wq_umem_valid:1;
280 uint32_t log_hairpin_num_packets:5;
281 uint32_t log_hairpin_data_sz:5;
282 uint32_t single_wqe_log_num_of_strides:4;
283 uint32_t two_byte_shift_en:1;
284 uint32_t single_stride_log_num_of_bytes:3;
285 uint32_t dbr_umem_id;
287 uint64_t wq_umem_offset;
290 /* Create RQ attributes structure, used by create RQ operation. */
291 struct mlx5_devx_create_rq_attr {
293 uint32_t delay_drop_en:1;
294 uint32_t scatter_fcs:1;
296 uint32_t mem_rq_type:4;
298 uint32_t flush_in_error_en:1;
300 uint32_t user_index:24;
302 uint32_t counter_set_id:8;
304 struct mlx5_devx_wq_attr wq_attr;
307 /* Modify RQ attributes structure, used by modify RQ operation. */
308 struct mlx5_devx_modify_rq_attr {
310 uint32_t rq_state:4; /* Current RQ state. */
311 uint32_t state:4; /* Required RQ state. */
312 uint32_t scatter_fcs:1;
314 uint32_t counter_set_id:8;
315 uint32_t hairpin_peer_sq:24;
316 uint32_t hairpin_peer_vhca:16;
317 uint64_t modify_bitmask;
318 uint32_t lwm:16; /* Contained WQ lwm. */
321 struct mlx5_rx_hash_field_select {
322 uint32_t l3_prot_type:1;
323 uint32_t l4_prot_type:1;
324 uint32_t selected_fields:30;
327 /* TIR attributes structure, used by TIR operations. */
328 struct mlx5_devx_tir_attr {
329 uint32_t disp_type:4;
330 uint32_t lro_timeout_period_usecs:16;
331 uint32_t lro_enable_mask:4;
332 uint32_t lro_max_msg_sz:8;
333 uint32_t inline_rqn:24;
334 uint32_t rx_hash_symmetric:1;
335 uint32_t tunneled_offload_en:1;
336 uint32_t indirect_table:24;
337 uint32_t rx_hash_fn:4;
338 uint32_t self_lb_block:2;
339 uint32_t transport_domain:24;
340 uint32_t rx_hash_toeplitz_key[10];
341 struct mlx5_rx_hash_field_select rx_hash_field_selector_outer;
342 struct mlx5_rx_hash_field_select rx_hash_field_selector_inner;
345 /* RQT attributes structure, used by RQT operations. */
346 struct mlx5_devx_rqt_attr {
347 uint32_t rqt_max_size:16;
348 uint32_t rqt_actual_size:16;
353 * Type of object being allocated.
355 enum mlx5_verbs_alloc_type {
356 MLX5_VERBS_ALLOC_TYPE_NONE,
357 MLX5_VERBS_ALLOC_TYPE_TX_QUEUE,
358 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE,
362 * Verbs allocator needs a context to know in the callback which kind of
363 * resources it is allocating.
365 struct mlx5_verbs_alloc_ctx {
366 enum mlx5_verbs_alloc_type type; /* Kind of object being allocated. */
367 const void *obj; /* Pointer to the DPDK object. */
370 LIST_HEAD(mlx5_mr_list, mlx5_mr);
372 /* Flow drop context necessary due to Verbs API. */
374 struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */
375 struct mlx5_rxq_obj *rxq; /* Rx queue object. */
378 #define MLX5_COUNTERS_PER_POOL 512
379 #define MLX5_MAX_PENDING_QUERIES 4
381 struct mlx5_flow_counter_pool;
383 struct flow_counter_stats {
388 /* Counters information. */
389 struct mlx5_flow_counter {
390 TAILQ_ENTRY(mlx5_flow_counter) next;
391 /**< Pointer to the next flow counter structure. */
392 uint32_t shared:1; /**< Share counter ID with other flow rules. */
394 /**< Whether the counter was allocated by batch command. */
395 uint32_t ref_cnt:30; /**< Reference counter. */
396 uint32_t id; /**< Counter ID. */
397 union { /**< Holds the counters for the rule. */
398 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42)
399 struct ibv_counter_set *cs;
400 #elif defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
401 struct ibv_counters *cs;
403 struct mlx5_devx_obj *dcs; /**< Counter Devx object. */
404 struct mlx5_flow_counter_pool *pool; /**< The counter pool. */
407 uint64_t hits; /**< Reset value of hits packets. */
408 int64_t query_gen; /**< Generation of the last release. */
410 uint64_t bytes; /**< Reset value of bytes. */
411 void *action; /**< Pointer to the dv action. */
414 TAILQ_HEAD(mlx5_counters, mlx5_flow_counter);
416 /* Counter pool structure - query is in pool resolution. */
417 struct mlx5_flow_counter_pool {
418 TAILQ_ENTRY(mlx5_flow_counter_pool) next;
419 struct mlx5_counters counters; /* Free counter list. */
421 struct mlx5_devx_obj *min_dcs;
422 rte_atomic64_t a64_dcs;
424 /* The devx object of the minimum counter ID. */
425 rte_atomic64_t query_gen;
426 uint32_t n_counters: 16; /* Number of devx allocated counters. */
427 rte_spinlock_t sl; /* The pool lock. */
428 struct mlx5_counter_stats_raw *raw;
429 struct mlx5_counter_stats_raw *raw_hw; /* The raw on HW working. */
430 struct mlx5_flow_counter counters_raw[]; /* The pool counters memory. */
433 struct mlx5_counter_stats_raw;
435 /* Memory management structure for group of counter statistics raws. */
436 struct mlx5_counter_stats_mem_mng {
437 LIST_ENTRY(mlx5_counter_stats_mem_mng) next;
438 struct mlx5_counter_stats_raw *raws;
439 struct mlx5_devx_obj *dm;
440 struct mlx5dv_devx_umem *umem;
443 /* Raw memory structure for the counter statistics values of a pool. */
444 struct mlx5_counter_stats_raw {
445 LIST_ENTRY(mlx5_counter_stats_raw) next;
447 struct mlx5_counter_stats_mem_mng *mem_mng;
448 volatile struct flow_counter_stats *data;
451 TAILQ_HEAD(mlx5_counter_pools, mlx5_flow_counter_pool);
453 /* Container structure for counter pools. */
454 struct mlx5_pools_container {
455 rte_atomic16_t n_valid; /* Number of valid pools. */
456 uint16_t n; /* Number of pools. */
457 struct mlx5_counter_pools pool_list; /* Counter pool list. */
458 struct mlx5_flow_counter_pool **pools; /* Counter pool array. */
459 struct mlx5_counter_stats_mem_mng *init_mem_mng;
460 /* Hold the memory management for the next allocated pools raws. */
463 /* Counter global management structure. */
464 struct mlx5_flow_counter_mng {
465 uint8_t mhi[2]; /* master \ host container index. */
466 struct mlx5_pools_container ccont[2 * 2];
467 /* 2 containers for single and for batch for double-buffer. */
468 struct mlx5_counters flow_counters; /* Legacy flow counter list. */
469 uint8_t pending_queries;
472 uint8_t query_thread_on;
473 LIST_HEAD(mem_mngs, mlx5_counter_stats_mem_mng) mem_mngs;
474 LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws;
477 /* Per port data of shared IB device. */
478 struct mlx5_ibv_shared_port {
481 * Interrupt handler port_id. Used by shared interrupt
482 * handler to find the corresponding rte_eth device
483 * by IB port index. If value is equal or greater
484 * RTE_MAX_ETHPORTS it means there is no subhandler
485 * installed for specified IB port index.
489 /* Table structure. */
490 struct mlx5_flow_tbl_resource {
491 void *obj; /**< Pointer to DR table object. */
492 rte_atomic32_t refcnt; /**< Reference counter. */
495 #define MLX5_MAX_TABLES 1024
496 #define MLX5_MAX_TABLES_FDB 32
497 #define MLX5_GROUP_FACTOR 1
499 #define MLX5_DBR_PAGE_SIZE 4096 /* Must be >= 512. */
500 #define MLX5_DBR_SIZE 8
501 #define MLX5_DBR_PER_PAGE (MLX5_DBR_PAGE_SIZE / MLX5_DBR_SIZE)
502 #define MLX5_DBR_BITMAP_SIZE (MLX5_DBR_PER_PAGE / 64)
504 struct mlx5_devx_dbr_page {
505 /* Door-bell records, must be first member in structure. */
506 uint8_t dbrs[MLX5_DBR_PAGE_SIZE];
507 LIST_ENTRY(mlx5_devx_dbr_page) next; /* Pointer to the next element. */
508 struct mlx5dv_devx_umem *umem;
509 uint32_t dbr_count; /* Number of door-bell records in use. */
510 /* 1 bit marks matching door-bell is in use. */
511 uint64_t dbr_bitmap[MLX5_DBR_BITMAP_SIZE];
515 * Shared Infiniband device context for Master/Representors
516 * which belong to same IB device with multiple IB ports.
518 struct mlx5_ibv_shared {
519 LIST_ENTRY(mlx5_ibv_shared) next;
521 uint32_t devx:1; /* Opened with DV. */
522 uint32_t max_port; /* Maximal IB device port index. */
523 struct ibv_context *ctx; /* Verbs/DV context. */
524 struct ibv_pd *pd; /* Protection Domain. */
525 uint32_t pdn; /* Protection Domain number. */
526 uint32_t tdn; /* Transport Domain number. */
527 char ibdev_name[IBV_SYSFS_NAME_MAX]; /* IB device name. */
528 char ibdev_path[IBV_SYSFS_PATH_MAX]; /* IB device path for secondary */
529 struct ibv_device_attr_ex device_attr; /* Device properties. */
530 struct rte_pci_device *pci_dev; /* Backend PCI device. */
531 LIST_ENTRY(mlx5_ibv_shared) mem_event_cb;
532 /**< Called by memory event callback. */
534 uint32_t dev_gen; /* Generation number to flush local caches. */
535 rte_rwlock_t rwlock; /* MR Lock. */
536 struct mlx5_mr_btree cache; /* Global MR cache table. */
537 struct mlx5_mr_list mr_list; /* Registered MR list. */
538 struct mlx5_mr_list mr_free_list; /* Freed MR list. */
540 /* Shared DV/DR flow data section. */
541 pthread_mutex_t dv_mutex; /* DV context mutex. */
542 uint32_t dv_refcnt; /* DV/DR data reference counter. */
543 void *fdb_domain; /* FDB Direct Rules name space handle. */
544 struct mlx5_flow_tbl_resource fdb_tbl[MLX5_MAX_TABLES_FDB];
545 /* FDB Direct Rules tables. */
546 void *rx_domain; /* RX Direct Rules name space handle. */
547 struct mlx5_flow_tbl_resource rx_tbl[MLX5_MAX_TABLES];
548 /* RX Direct Rules tables. */
549 void *tx_domain; /* TX Direct Rules name space handle. */
550 struct mlx5_flow_tbl_resource tx_tbl[MLX5_MAX_TABLES];
551 void *esw_drop_action; /* Pointer to DR E-Switch drop action. */
552 /* TX Direct Rules tables/ */
553 LIST_HEAD(matchers, mlx5_flow_dv_matcher) matchers;
554 LIST_HEAD(encap_decap, mlx5_flow_dv_encap_decap_resource) encaps_decaps;
555 LIST_HEAD(modify_cmd, mlx5_flow_dv_modify_hdr_resource) modify_cmds;
556 LIST_HEAD(tag, mlx5_flow_dv_tag_resource) tags;
557 LIST_HEAD(jump, mlx5_flow_dv_jump_tbl_resource) jump_tbl;
558 LIST_HEAD(port_id_action_list, mlx5_flow_dv_port_id_action_resource)
559 port_id_action_list; /* List of port ID actions. */
560 struct mlx5_flow_counter_mng cmng; /* Counters management structure. */
561 /* Shared interrupt handler section. */
562 pthread_mutex_t intr_mutex; /* Interrupt config mutex. */
563 uint32_t intr_cnt; /* Interrupt handler reference counter. */
564 struct rte_intr_handle intr_handle; /* Interrupt handler for device. */
565 struct rte_intr_handle intr_handle_devx; /* DEVX interrupt handler. */
566 struct mlx5dv_devx_cmd_comp *devx_comp; /* DEVX async comp obj. */
567 struct mlx5_ibv_shared_port port[]; /* per device port data array. */
570 /* Per-process private structure. */
571 struct mlx5_proc_priv {
573 /* Size of UAR register table. */
575 /* Table of UAR registers for each process. */
578 #define MLX5_PROC_PRIV(port_id) \
579 ((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private)
582 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */
583 struct mlx5_ibv_shared *sh; /* Shared IB device context. */
584 uint32_t ibv_port; /* IB device port number. */
585 struct rte_ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */
586 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES);
587 /* Bit-field of MAC addresses owned by the PMD. */
588 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */
589 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */
590 /* Device properties. */
591 uint16_t mtu; /* Configured MTU. */
592 unsigned int isolated:1; /* Whether isolated mode is enabled. */
593 unsigned int representor:1; /* Device is a port representor. */
594 unsigned int master:1; /* Device is a E-Switch master. */
595 unsigned int dr_shared:1; /* DV/DR data is shared. */
596 unsigned int counter_fallback:1; /* Use counter fallback management. */
597 uint16_t domain_id; /* Switch domain identifier. */
598 uint16_t vport_id; /* Associated VF vport index (if any). */
599 int32_t representor_id; /* Port representor identifier. */
600 unsigned int if_index; /* Associated kernel network device index. */
602 unsigned int rxqs_n; /* RX queues array size. */
603 unsigned int txqs_n; /* TX queues array size. */
604 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */
605 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */
606 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
607 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */
608 unsigned int (*reta_idx)[]; /* RETA index table. */
609 unsigned int reta_idx_n; /* RETA index size. */
610 struct mlx5_drop drop_queue; /* Flow drop queues. */
611 struct mlx5_flows flows; /* RTE Flow rules. */
612 struct mlx5_flows ctrl_flows; /* Control flow rules. */
613 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */
614 LIST_HEAD(rxqobj, mlx5_rxq_obj) rxqsobj; /* Verbs/DevX Rx queues. */
615 LIST_HEAD(hrxq, mlx5_hrxq) hrxqs; /* Verbs Hash Rx queues. */
616 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */
617 LIST_HEAD(txqibv, mlx5_txq_ibv) txqsibv; /* Verbs Tx queues. */
618 /* Indirection tables. */
619 LIST_HEAD(ind_tables, mlx5_ind_table_obj) ind_tbls;
620 /* Pointer to next element. */
621 rte_atomic32_t refcnt; /**< Reference counter. */
622 struct ibv_flow_action *verbs_action;
623 /**< Verbs modify header action object. */
624 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
625 uint8_t max_lro_msg_size;
626 /* Tags resources cache. */
627 uint32_t link_speed_capa; /* Link speed capabilities. */
628 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */
629 struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */
630 struct mlx5_dev_config config; /* Device configuration. */
631 struct mlx5_verbs_alloc_ctx verbs_alloc_ctx;
632 /* Context for Verbs allocator. */
633 int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */
634 int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */
635 uint32_t nl_sn; /* Netlink message sequence number. */
636 LIST_HEAD(dbrpage, mlx5_devx_dbr_page) dbrpgs; /* Door-bell pages. */
638 rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */
639 rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX];
640 /* UAR same-page access control required in 32bit implementations. */
644 #define PORT_ID(priv) ((priv)->dev_data->port_id)
645 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)])
649 int mlx5_getenv_int(const char *);
650 int mlx5_proc_priv_init(struct rte_eth_dev *dev);
651 int64_t mlx5_get_dbr(struct rte_eth_dev *dev,
652 struct mlx5_devx_dbr_page **dbr_page);
653 int32_t mlx5_release_dbr(struct rte_eth_dev *dev, uint32_t umem_id,
658 int mlx5_get_ifname(const struct rte_eth_dev *dev, char (*ifname)[IF_NAMESIZE]);
659 int mlx5_get_master_ifname(const char *ibdev_path, char (*ifname)[IF_NAMESIZE]);
660 unsigned int mlx5_ifindex(const struct rte_eth_dev *dev);
661 int mlx5_ifreq(const struct rte_eth_dev *dev, int req, struct ifreq *ifr);
662 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu);
663 int mlx5_set_flags(struct rte_eth_dev *dev, unsigned int keep,
665 int mlx5_dev_configure(struct rte_eth_dev *dev);
666 void mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info);
667 int mlx5_read_clock(struct rte_eth_dev *dev, uint64_t *clock);
668 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size);
669 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev);
670 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete);
671 int mlx5_force_link_status_change(struct rte_eth_dev *dev, int status);
672 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
673 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev,
674 struct rte_eth_fc_conf *fc_conf);
675 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev,
676 struct rte_eth_fc_conf *fc_conf);
677 int mlx5_ibv_device_to_pci_addr(const struct ibv_device *device,
678 struct rte_pci_addr *pci_addr);
679 void mlx5_dev_link_status_handler(void *arg);
680 void mlx5_dev_interrupt_handler(void *arg);
681 void mlx5_dev_interrupt_handler_devx(void *arg);
682 void mlx5_dev_interrupt_handler_uninstall(struct rte_eth_dev *dev);
683 void mlx5_dev_interrupt_handler_install(struct rte_eth_dev *dev);
684 int mlx5_set_link_down(struct rte_eth_dev *dev);
685 int mlx5_set_link_up(struct rte_eth_dev *dev);
686 int mlx5_is_removed(struct rte_eth_dev *dev);
687 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev);
688 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev);
689 unsigned int mlx5_dev_to_port_id(const struct rte_device *dev,
691 unsigned int port_list_n);
692 int mlx5_port_to_eswitch_info(uint16_t port, uint16_t *es_domain_id,
693 uint16_t *es_port_id);
694 int mlx5_sysfs_switch_info(unsigned int ifindex,
695 struct mlx5_switch_info *info);
696 void mlx5_sysfs_check_switch_info(bool device_dir,
697 struct mlx5_switch_info *switch_info);
698 void mlx5_nl_check_switch_info(bool nun_vf_set,
699 struct mlx5_switch_info *switch_info);
700 void mlx5_translate_port_name(const char *port_name_in,
701 struct mlx5_switch_info *port_info_out);
702 void mlx5_intr_callback_unregister(const struct rte_intr_handle *handle,
703 rte_intr_callback_fn cb_fn, void *cb_arg);
707 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]);
708 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
709 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
710 uint32_t index, uint32_t vmdq);
711 int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr);
712 int mlx5_set_mc_addr_list(struct rte_eth_dev *dev,
713 struct rte_ether_addr *mc_addr_set,
714 uint32_t nb_mc_addr);
718 int mlx5_rss_hash_update(struct rte_eth_dev *dev,
719 struct rte_eth_rss_conf *rss_conf);
720 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev,
721 struct rte_eth_rss_conf *rss_conf);
722 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size);
723 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev,
724 struct rte_eth_rss_reta_entry64 *reta_conf,
726 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev,
727 struct rte_eth_rss_reta_entry64 *reta_conf,
732 void mlx5_promiscuous_enable(struct rte_eth_dev *dev);
733 void mlx5_promiscuous_disable(struct rte_eth_dev *dev);
734 void mlx5_allmulticast_enable(struct rte_eth_dev *dev);
735 void mlx5_allmulticast_disable(struct rte_eth_dev *dev);
739 void mlx5_stats_init(struct rte_eth_dev *dev);
740 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
741 void mlx5_stats_reset(struct rte_eth_dev *dev);
742 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats,
744 void mlx5_xstats_reset(struct rte_eth_dev *dev);
745 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
746 struct rte_eth_xstat_name *xstats_names,
751 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
752 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on);
753 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask);
757 int mlx5_dev_start(struct rte_eth_dev *dev);
758 void mlx5_dev_stop(struct rte_eth_dev *dev);
759 int mlx5_traffic_enable(struct rte_eth_dev *dev);
760 void mlx5_traffic_disable(struct rte_eth_dev *dev);
761 int mlx5_traffic_restart(struct rte_eth_dev *dev);
765 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
766 void mlx5_flow_print(struct rte_flow *flow);
767 int mlx5_flow_validate(struct rte_eth_dev *dev,
768 const struct rte_flow_attr *attr,
769 const struct rte_flow_item items[],
770 const struct rte_flow_action actions[],
771 struct rte_flow_error *error);
772 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev,
773 const struct rte_flow_attr *attr,
774 const struct rte_flow_item items[],
775 const struct rte_flow_action actions[],
776 struct rte_flow_error *error);
777 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow,
778 struct rte_flow_error *error);
779 void mlx5_flow_list_flush(struct rte_eth_dev *dev, struct mlx5_flows *list);
780 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error);
781 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow,
782 const struct rte_flow_action *action, void *data,
783 struct rte_flow_error *error);
784 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable,
785 struct rte_flow_error *error);
786 int mlx5_dev_filter_ctrl(struct rte_eth_dev *dev,
787 enum rte_filter_type filter_type,
788 enum rte_filter_op filter_op,
790 int mlx5_flow_start(struct rte_eth_dev *dev, struct mlx5_flows *list);
791 void mlx5_flow_stop(struct rte_eth_dev *dev, struct mlx5_flows *list);
792 int mlx5_flow_verify(struct rte_eth_dev *dev);
793 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev,
794 struct rte_flow_item_eth *eth_spec,
795 struct rte_flow_item_eth *eth_mask,
796 struct rte_flow_item_vlan *vlan_spec,
797 struct rte_flow_item_vlan *vlan_mask);
798 int mlx5_ctrl_flow(struct rte_eth_dev *dev,
799 struct rte_flow_item_eth *eth_spec,
800 struct rte_flow_item_eth *eth_mask);
801 int mlx5_flow_create_drop_queue(struct rte_eth_dev *dev);
802 void mlx5_flow_delete_drop_queue(struct rte_eth_dev *dev);
803 void mlx5_flow_async_pool_query_handle(struct mlx5_ibv_shared *sh,
804 uint64_t async_id, int status);
805 void mlx5_set_query_alarm(struct mlx5_ibv_shared *sh);
806 void mlx5_flow_query_alarm(void *arg);
809 void mlx5_mp_req_start_rxtx(struct rte_eth_dev *dev);
810 void mlx5_mp_req_stop_rxtx(struct rte_eth_dev *dev);
811 int mlx5_mp_req_mr_create(struct rte_eth_dev *dev, uintptr_t addr);
812 int mlx5_mp_req_verbs_cmd_fd(struct rte_eth_dev *dev);
813 int mlx5_mp_req_queue_state_modify(struct rte_eth_dev *dev,
814 struct mlx5_mp_arg_queue_state_modify *sm);
815 int mlx5_mp_init_primary(void);
816 void mlx5_mp_uninit_primary(void);
817 int mlx5_mp_init_secondary(void);
818 void mlx5_mp_uninit_secondary(void);
822 int mlx5_nl_init(int protocol);
823 int mlx5_nl_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
825 int mlx5_nl_mac_addr_remove(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
827 void mlx5_nl_mac_addr_sync(struct rte_eth_dev *dev);
828 void mlx5_nl_mac_addr_flush(struct rte_eth_dev *dev);
829 int mlx5_nl_promisc(struct rte_eth_dev *dev, int enable);
830 int mlx5_nl_allmulti(struct rte_eth_dev *dev, int enable);
831 unsigned int mlx5_nl_portnum(int nl, const char *name);
832 unsigned int mlx5_nl_ifindex(int nl, const char *name, uint32_t pindex);
833 int mlx5_nl_switch_info(int nl, unsigned int ifindex,
834 struct mlx5_switch_info *info);
836 /* mlx5_devx_cmds.c */
838 struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(struct ibv_context *ctx,
840 int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj);
841 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
842 int clear, uint32_t n_counters,
843 uint64_t *pkts, uint64_t *bytes,
844 uint32_t mkey, void *addr,
845 struct mlx5dv_devx_cmd_comp *cmd_comp,
847 int mlx5_devx_cmd_query_hca_attr(struct ibv_context *ctx,
848 struct mlx5_hca_attr *attr);
849 struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(struct ibv_context *ctx,
850 struct mlx5_devx_mkey_attr *attr);
851 int mlx5_devx_get_out_command_status(void *out);
852 int mlx5_devx_cmd_qp_query_tis_td(struct ibv_qp *qp, uint32_t tis_num,
854 struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(struct ibv_context *ctx,
855 struct mlx5_devx_create_rq_attr *rq_attr,
857 int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
858 struct mlx5_devx_modify_rq_attr *rq_attr);
859 struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(struct ibv_context *ctx,
860 struct mlx5_devx_tir_attr *tir_attr);
861 struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(struct ibv_context *ctx,
862 struct mlx5_devx_rqt_attr *rqt_attr);
864 #endif /* RTE_PMD_MLX5_H_ */