1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox.
6 #ifndef RTE_PMD_MLX5_H_
7 #define RTE_PMD_MLX5_H_
13 #include <netinet/in.h>
14 #include <sys/queue.h>
17 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
19 #pragma GCC diagnostic ignored "-Wpedantic"
21 #include <infiniband/verbs.h>
23 #pragma GCC diagnostic error "-Wpedantic"
27 #include <rte_ether.h>
28 #include <rte_ethdev_driver.h>
29 #include <rte_spinlock.h>
30 #include <rte_interrupts.h>
31 #include <rte_errno.h>
34 #include "mlx5_utils.h"
35 #include "mlx5_rxtx.h"
36 #include "mlx5_autoconf.h"
37 #include "mlx5_defs.h"
40 PCI_VENDOR_ID_MELLANOX = 0x15b3,
44 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013,
45 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014,
46 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015,
47 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016,
48 PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017,
49 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018,
50 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019,
51 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a,
54 struct mlx5_xstats_ctrl {
55 /* Number of device stats. */
57 /* Index in the device counters table. */
58 uint16_t dev_table_idx[MLX5_MAX_XSTATS];
59 uint64_t base[MLX5_MAX_XSTATS];
63 TAILQ_HEAD(mlx5_flows, rte_flow);
65 /* Default PMD specific parameter value. */
66 #define MLX5_ARG_UNSET (-1)
69 * Device configuration structure.
71 * Merged configuration from:
73 * - Device capabilities,
74 * - User device parameters disabled features.
76 struct mlx5_dev_config {
77 unsigned int hw_csum:1; /* Checksum offload is supported. */
78 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */
79 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */
80 unsigned int hw_padding:1; /* End alignment padding is supported. */
81 unsigned int mps:2; /* Multi-packet send supported mode. */
82 unsigned int tunnel_en:1;
83 /* Whether tunnel stateless offloads are supported. */
84 unsigned int flow_counter_en:1; /* Whether flow counter is supported. */
85 unsigned int cqe_comp:1; /* CQE compression is enabled. */
86 unsigned int tso:1; /* Whether TSO is supported. */
87 unsigned int tx_vec_en:1; /* Tx vector is enabled. */
88 unsigned int rx_vec_en:1; /* Rx vector is enabled. */
89 unsigned int mpw_hdr_dseg:1; /* Enable DSEGs in the title WQEBB. */
90 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */
91 unsigned int ind_table_max_size; /* Maximum indirection table size. */
92 int txq_inline; /* Maximum packet size for inlining. */
93 int txqs_inline; /* Queue number threshold for inlining. */
94 int inline_max_packet_sz; /* Max packet size for inlining. */
98 * Type of objet being allocated.
100 enum mlx5_verbs_alloc_type {
101 MLX5_VERBS_ALLOC_TYPE_NONE,
102 MLX5_VERBS_ALLOC_TYPE_TX_QUEUE,
103 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE,
107 * Verbs allocator needs a context to know in the callback which kind of
108 * resources it is allocating.
110 struct mlx5_verbs_alloc_ctx {
111 enum mlx5_verbs_alloc_type type; /* Kind of object being allocated. */
112 const void *obj; /* Pointer to the DPDK object. */
116 struct rte_eth_dev *dev; /* Ethernet device of master process. */
117 struct ibv_context *ctx; /* Verbs context. */
118 struct ibv_device_attr_ex device_attr; /* Device properties. */
119 struct ibv_pd *pd; /* Protection Domain. */
120 char ibdev_path[IBV_SYSFS_PATH_MAX]; /* IB device path for secondary */
121 struct ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */
122 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */
123 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */
124 /* Device properties. */
125 uint16_t mtu; /* Configured MTU. */
126 uint8_t port; /* Physical port number. */
127 unsigned int pending_alarm:1; /* An alarm is pending. */
128 unsigned int isolated:1; /* Whether isolated mode is enabled. */
130 unsigned int rxqs_n; /* RX queues array size. */
131 unsigned int txqs_n; /* TX queues array size. */
132 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */
133 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */
134 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */
135 struct rte_intr_handle intr_handle; /* Interrupt handler. */
136 unsigned int (*reta_idx)[]; /* RETA index table. */
137 unsigned int reta_idx_n; /* RETA index size. */
138 struct mlx5_hrxq_drop *flow_drop_queue; /* Flow drop queue. */
139 struct mlx5_flows flows; /* RTE Flow rules. */
140 struct mlx5_flows ctrl_flows; /* Control flow rules. */
141 LIST_HEAD(mr, mlx5_mr) mr; /* Memory region. */
142 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */
143 LIST_HEAD(rxqibv, mlx5_rxq_ibv) rxqsibv; /* Verbs Rx queues. */
144 LIST_HEAD(hrxq, mlx5_hrxq) hrxqs; /* Verbs Hash Rx queues. */
145 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */
146 LIST_HEAD(txqibv, mlx5_txq_ibv) txqsibv; /* Verbs Tx queues. */
147 /* Verbs Indirection tables. */
148 LIST_HEAD(ind_tables, mlx5_ind_table_ibv) ind_tbls;
149 uint32_t link_speed_capa; /* Link speed capabilities. */
150 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */
151 rte_spinlock_t lock; /* Lock for control functions. */
152 int primary_socket; /* Unix socket for primary process. */
153 void *uar_base; /* Reserved address space for UAR mapping */
154 struct rte_intr_handle intr_handle_socket; /* Interrupt handler. */
155 struct mlx5_dev_config config; /* Device configuration. */
156 struct mlx5_verbs_alloc_ctx verbs_alloc_ctx;
157 /* Context for Verbs allocator. */
161 * Lock private structure to protect it from concurrent access in the
165 * Pointer to private structure.
168 priv_lock(struct priv *priv)
170 rte_spinlock_lock(&priv->lock);
174 * Try to lock private structure to protect it from concurrent access in the
178 * Pointer to private structure.
181 * 1 if the lock is successfully taken; 0 otherwise.
184 priv_trylock(struct priv *priv)
186 return rte_spinlock_trylock(&priv->lock);
190 * Unlock private structure.
193 * Pointer to private structure.
196 priv_unlock(struct priv *priv)
198 rte_spinlock_unlock(&priv->lock);
203 int mlx5_getenv_int(const char *);
207 struct priv *mlx5_get_priv(struct rte_eth_dev *dev);
208 int mlx5_is_secondary(void);
209 int priv_get_ifname(const struct priv *, char (*)[IF_NAMESIZE]);
210 int priv_ifreq(const struct priv *, int req, struct ifreq *);
211 int priv_get_mtu(struct priv *, uint16_t *);
212 int priv_set_flags(struct priv *, unsigned int, unsigned int);
213 int mlx5_dev_configure(struct rte_eth_dev *);
214 void mlx5_dev_infos_get(struct rte_eth_dev *, struct rte_eth_dev_info *);
215 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev);
216 int priv_link_update(struct priv *, int);
217 int priv_force_link_status_change(struct priv *, int);
218 int mlx5_link_update(struct rte_eth_dev *, int);
219 int mlx5_dev_set_mtu(struct rte_eth_dev *, uint16_t);
220 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *, struct rte_eth_fc_conf *);
221 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *, struct rte_eth_fc_conf *);
222 int mlx5_ibv_device_to_pci_addr(const struct ibv_device *,
223 struct rte_pci_addr *);
224 void mlx5_dev_link_status_handler(void *);
225 void mlx5_dev_interrupt_handler(void *);
226 void priv_dev_interrupt_handler_uninstall(struct priv *, struct rte_eth_dev *);
227 void priv_dev_interrupt_handler_install(struct priv *, struct rte_eth_dev *);
228 int mlx5_set_link_down(struct rte_eth_dev *dev);
229 int mlx5_set_link_up(struct rte_eth_dev *dev);
230 int mlx5_is_removed(struct rte_eth_dev *dev);
231 eth_tx_burst_t priv_select_tx_function(struct priv *, struct rte_eth_dev *);
232 eth_rx_burst_t priv_select_rx_function(struct priv *, struct rte_eth_dev *);
236 int priv_get_mac(struct priv *, uint8_t (*)[ETHER_ADDR_LEN]);
237 void mlx5_mac_addr_remove(struct rte_eth_dev *, uint32_t);
238 int mlx5_mac_addr_add(struct rte_eth_dev *, struct ether_addr *, uint32_t,
240 void mlx5_mac_addr_set(struct rte_eth_dev *, struct ether_addr *);
244 int mlx5_rss_hash_update(struct rte_eth_dev *, struct rte_eth_rss_conf *);
245 int mlx5_rss_hash_conf_get(struct rte_eth_dev *, struct rte_eth_rss_conf *);
246 int priv_rss_reta_index_resize(struct priv *, unsigned int);
247 int mlx5_dev_rss_reta_query(struct rte_eth_dev *,
248 struct rte_eth_rss_reta_entry64 *, uint16_t);
249 int mlx5_dev_rss_reta_update(struct rte_eth_dev *,
250 struct rte_eth_rss_reta_entry64 *, uint16_t);
254 void mlx5_promiscuous_enable(struct rte_eth_dev *);
255 void mlx5_promiscuous_disable(struct rte_eth_dev *);
256 void mlx5_allmulticast_enable(struct rte_eth_dev *);
257 void mlx5_allmulticast_disable(struct rte_eth_dev *);
261 void priv_xstats_init(struct priv *);
262 int mlx5_stats_get(struct rte_eth_dev *, struct rte_eth_stats *);
263 void mlx5_stats_reset(struct rte_eth_dev *);
264 int mlx5_xstats_get(struct rte_eth_dev *,
265 struct rte_eth_xstat *, unsigned int);
266 void mlx5_xstats_reset(struct rte_eth_dev *);
267 int mlx5_xstats_get_names(struct rte_eth_dev *,
268 struct rte_eth_xstat_name *, unsigned int);
272 int mlx5_vlan_filter_set(struct rte_eth_dev *, uint16_t, int);
273 int mlx5_vlan_offload_set(struct rte_eth_dev *, int);
274 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *, uint16_t, int);
278 int mlx5_dev_start(struct rte_eth_dev *);
279 void mlx5_dev_stop(struct rte_eth_dev *);
280 int priv_dev_traffic_enable(struct priv *, struct rte_eth_dev *);
281 int priv_dev_traffic_disable(struct priv *, struct rte_eth_dev *);
282 int priv_dev_traffic_restart(struct priv *, struct rte_eth_dev *);
283 int mlx5_traffic_restart(struct rte_eth_dev *);
287 int mlx5_dev_filter_ctrl(struct rte_eth_dev *, enum rte_filter_type,
288 enum rte_filter_op, void *);
289 int mlx5_flow_validate(struct rte_eth_dev *, const struct rte_flow_attr *,
290 const struct rte_flow_item [],
291 const struct rte_flow_action [],
292 struct rte_flow_error *);
293 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *,
294 const struct rte_flow_attr *,
295 const struct rte_flow_item [],
296 const struct rte_flow_action [],
297 struct rte_flow_error *);
298 int mlx5_flow_destroy(struct rte_eth_dev *, struct rte_flow *,
299 struct rte_flow_error *);
300 void priv_flow_flush(struct priv *, struct mlx5_flows *);
301 int mlx5_flow_flush(struct rte_eth_dev *, struct rte_flow_error *);
302 int mlx5_flow_query(struct rte_eth_dev *, struct rte_flow *,
303 enum rte_flow_action_type, void *,
304 struct rte_flow_error *);
305 int mlx5_flow_isolate(struct rte_eth_dev *, int, struct rte_flow_error *);
306 int priv_flow_start(struct priv *, struct mlx5_flows *);
307 void priv_flow_stop(struct priv *, struct mlx5_flows *);
308 int priv_flow_verify(struct priv *);
309 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *, struct rte_flow_item_eth *,
310 struct rte_flow_item_eth *, struct rte_flow_item_vlan *,
311 struct rte_flow_item_vlan *);
312 int mlx5_ctrl_flow(struct rte_eth_dev *, struct rte_flow_item_eth *,
313 struct rte_flow_item_eth *);
314 int priv_flow_create_drop_queue(struct priv *);
315 void priv_flow_delete_drop_queue(struct priv *);
319 int priv_socket_init(struct priv *priv);
320 int priv_socket_uninit(struct priv *priv);
321 void priv_socket_handle(struct priv *priv);
322 int priv_socket_connect(struct priv *priv);
326 struct mlx5_mr *priv_mr_new(struct priv *, struct rte_mempool *);
327 struct mlx5_mr *priv_mr_get(struct priv *, struct rte_mempool *);
328 int priv_mr_release(struct priv *, struct mlx5_mr *);
329 int priv_mr_verify(struct priv *);
331 #endif /* RTE_PMD_MLX5_H_ */