1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_H_
7 #define RTE_PMD_MLX5_H_
13 #include <sys/queue.h>
16 #include <rte_ether.h>
17 #include <ethdev_driver.h>
18 #include <rte_rwlock.h>
19 #include <rte_interrupts.h>
20 #include <rte_errno.h>
24 #include <mlx5_glue.h>
25 #include <mlx5_devx_cmds.h>
27 #include <mlx5_common_mp.h>
28 #include <mlx5_common_mr.h>
29 #include <mlx5_common_devx.h>
30 #include <mlx5_common_defs.h>
32 #include "mlx5_defs.h"
33 #include "mlx5_utils.h"
35 #include "mlx5_autoconf.h"
38 #define MLX5_SH(dev) (((struct mlx5_priv *)(dev)->data->dev_private)->sh)
41 * Number of modification commands.
42 * The maximal actions amount in FW is some constant, and it is 16 in the
43 * latest releases. In some old releases, it will be limited to 8.
44 * Since there is no interface to query the capacity, the maximal value should
45 * be used to allow PMD to create the flow. The validation will be done in the
46 * lower driver layer or FW. A failure will be returned if exceeds the maximal
47 * supported actions number on the root table.
48 * On non-root tables, there is no limitation, but 32 is enough right now.
50 #define MLX5_MAX_MODIFY_NUM 32
51 #define MLX5_ROOT_TBL_MODIFY_NUM 16
53 enum mlx5_ipool_index {
54 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
55 MLX5_IPOOL_DECAP_ENCAP = 0, /* Pool for encap/decap resource. */
56 MLX5_IPOOL_PUSH_VLAN, /* Pool for push vlan resource. */
57 MLX5_IPOOL_TAG, /* Pool for tag resource. */
58 MLX5_IPOOL_PORT_ID, /* Pool for port id resource. */
59 MLX5_IPOOL_JUMP, /* Pool for jump resource. */
60 MLX5_IPOOL_SAMPLE, /* Pool for sample resource. */
61 MLX5_IPOOL_DEST_ARRAY, /* Pool for destination array resource. */
62 MLX5_IPOOL_TUNNEL_ID, /* Pool for tunnel offload context */
63 MLX5_IPOOL_TNL_TBL_ID, /* Pool for tunnel table ID. */
65 MLX5_IPOOL_MTR, /* Pool for meter resource. */
66 MLX5_IPOOL_MCP, /* Pool for metadata resource. */
67 MLX5_IPOOL_HRXQ, /* Pool for hrxq resource. */
68 MLX5_IPOOL_MLX5_FLOW, /* Pool for mlx5 flow handle. */
69 MLX5_IPOOL_RTE_FLOW, /* Pool for rte_flow. */
70 MLX5_IPOOL_RSS_EXPANTION_FLOW_ID, /* Pool for Queue/RSS flow ID. */
71 MLX5_IPOOL_RSS_SHARED_ACTIONS, /* Pool for RSS shared actions. */
72 MLX5_IPOOL_MTR_POLICY, /* Pool for meter policy resource. */
77 * There are three reclaim memory mode supported.
78 * 0(none) means no memory reclaim.
79 * 1(light) means only PMD level reclaim.
80 * 2(aggressive) means both PMD and rdma-core level reclaim.
82 enum mlx5_reclaim_mem_mode {
83 MLX5_RCM_NONE, /* Don't reclaim memory. */
84 MLX5_RCM_LIGHT, /* Reclaim PMD level. */
85 MLX5_RCM_AGGR, /* Reclaim PMD and rdma-core level. */
88 /* The type of flow. */
90 MLX5_FLOW_TYPE_CTL, /* Control flow. */
91 MLX5_FLOW_TYPE_GEN, /* General flow. */
92 MLX5_FLOW_TYPE_MCP, /* MCP flow. */
96 /* Hlist and list callback context. */
97 struct mlx5_flow_cb_ctx {
98 struct rte_eth_dev *dev;
99 struct rte_flow_error *error;
104 /* Device attributes used in mlx5 PMD */
105 struct mlx5_dev_attr {
106 uint64_t device_cap_flags_ex;
116 uint32_t raw_packet_caps;
117 uint32_t max_rwq_indirection_table_size;
119 uint32_t tso_supported_qpts;
122 uint32_t sw_parsing_offloads;
123 uint32_t min_single_stride_log_num_of_bytes;
124 uint32_t max_single_stride_log_num_of_bytes;
125 uint32_t min_single_wqe_log_num_of_strides;
126 uint32_t max_single_wqe_log_num_of_strides;
127 uint32_t stride_supported_qpts;
128 uint32_t tunnel_offloads_caps;
132 /** Data associated with devices to spawn. */
133 struct mlx5_dev_spawn_data {
134 uint32_t ifindex; /**< Network interface index. */
135 uint32_t max_port; /**< Device maximal port index. */
136 uint32_t phys_port; /**< Device physical port index. */
137 int pf_bond; /**< bonding device PF index. < 0 - no bonding */
138 struct mlx5_switch_info info; /**< Switch information. */
139 const char *phys_dev_name; /**< Name of physical device. */
140 struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */
141 struct rte_pci_device *pci_dev; /**< Backend PCI device. */
142 struct mlx5_common_device *cdev; /**< Backend common device. */
143 struct mlx5_bond_info *bond_info;
146 /** Data associated with socket messages. */
147 struct mlx5_flow_dump_req {
148 uint32_t port_id; /**< There are plans in DPDK to extend port_id. */
152 struct mlx5_flow_dump_ack {
153 int rc; /**< Return code. */
156 LIST_HEAD(mlx5_dev_list, mlx5_dev_ctx_shared);
158 /* Shared data between primary and secondary processes. */
159 struct mlx5_shared_data {
161 /* Global spinlock for primary and secondary processes. */
162 int init_done; /* Whether primary has done initialization. */
163 unsigned int secondary_cnt; /* Number of secondary processes init'd. */
166 /* Per-process data structure, not visible to other processes. */
167 struct mlx5_local_data {
168 int init_done; /* Whether a secondary has done initialization. */
171 extern struct mlx5_shared_data *mlx5_shared_data;
173 /* Dev ops structs */
174 extern const struct eth_dev_ops mlx5_dev_ops;
175 extern const struct eth_dev_ops mlx5_dev_sec_ops;
176 extern const struct eth_dev_ops mlx5_dev_ops_isolate;
178 struct mlx5_counter_ctrl {
179 /* Name of the counter. */
180 char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE];
181 /* Name of the counter on the device table. */
182 char ctr_name[RTE_ETH_XSTATS_NAME_SIZE];
183 uint32_t dev:1; /**< Nonzero for dev counters. */
186 struct mlx5_xstats_ctrl {
187 /* Number of device stats. */
189 /* Number of device stats identified by PMD. */
190 uint16_t mlx5_stats_n;
191 /* Index in the device counters table. */
192 uint16_t dev_table_idx[MLX5_MAX_XSTATS];
193 uint64_t base[MLX5_MAX_XSTATS];
194 uint64_t xstats[MLX5_MAX_XSTATS];
195 uint64_t hw_stats[MLX5_MAX_XSTATS];
196 struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS];
199 struct mlx5_stats_ctrl {
200 /* Base for imissed counter. */
201 uint64_t imissed_base;
205 #define MLX5_LRO_SUPPORTED(dev) \
206 (((struct mlx5_priv *)((dev)->data->dev_private))->config.lro.supported)
208 /* Maximal size of coalesced segment for LRO is set in chunks of 256 Bytes. */
209 #define MLX5_LRO_SEG_CHUNK_SIZE 256u
211 /* Maximal size of aggregated LRO packet. */
212 #define MLX5_MAX_LRO_SIZE (UINT8_MAX * MLX5_LRO_SEG_CHUNK_SIZE)
214 /* Maximal number of segments to split. */
215 #define MLX5_MAX_RXQ_NSEG (1u << MLX5_MAX_LOG_RQ_SEGS)
217 /* LRO configurations structure. */
218 struct mlx5_lro_config {
219 uint32_t supported:1; /* Whether LRO is supported. */
220 uint32_t timeout; /* User configuration. */
224 * Device configuration structure.
226 * Merged configuration from:
228 * - Device capabilities,
229 * - User device parameters disabled features.
231 struct mlx5_dev_config {
232 unsigned int hw_csum:1; /* Checksum offload is supported. */
233 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */
234 unsigned int hw_vlan_insert:1; /* VLAN insertion in WQE is supported. */
235 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */
236 unsigned int hw_padding:1; /* End alignment padding is supported. */
237 unsigned int vf:1; /* This is a VF. */
238 unsigned int sf:1; /* This is a SF. */
239 unsigned int tunnel_en:3;
240 /* Whether tunnel stateless offloads are supported. */
241 unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */
242 unsigned int cqe_comp:1; /* CQE compression is enabled. */
243 unsigned int cqe_comp_fmt:3; /* CQE compression format. */
244 unsigned int tso:1; /* Whether TSO is supported. */
245 unsigned int rx_vec_en:1; /* Rx vector is enabled. */
246 unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */
247 unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */
248 unsigned int dv_esw_en:1; /* Enable E-Switch DV flow. */
249 unsigned int dv_flow_en:1; /* Enable DV flow. */
250 unsigned int dv_xmeta_en:2; /* Enable extensive flow metadata. */
251 unsigned int lacp_by_user:1;
252 /* Enable user to manage LACP traffic. */
253 unsigned int swp:3; /* Tx generic tunnel checksum and TSO offload. */
254 unsigned int dest_tir:1; /* Whether advanced DR API is available. */
255 unsigned int reclaim_mode:2; /* Memory reclaim mode. */
256 unsigned int rt_timestamp:1; /* realtime timestamp format. */
257 unsigned int decap_en:1; /* Whether decap will be used or not. */
258 unsigned int dv_miss_info:1; /* restore packet after partial hw miss */
259 unsigned int allow_duplicate_pattern:1;
260 /* Allow/Prevent the duplicate rules pattern. */
262 unsigned int enabled:1; /* Whether MPRQ is enabled. */
263 unsigned int stride_num_n; /* Number of strides. */
264 unsigned int stride_size_n; /* Size of a stride. */
265 unsigned int min_stride_size_n; /* Min size of a stride. */
266 unsigned int max_stride_size_n; /* Max size of a stride. */
267 unsigned int max_memcpy_len;
268 /* Maximum packet size to memcpy Rx packets. */
269 unsigned int min_rxqs_num;
270 /* Rx queue count threshold to enable MPRQ. */
271 } mprq; /* Configurations for Multi-Packet RQ. */
272 int mps; /* Multi-packet send supported mode. */
273 unsigned int flow_prio; /* Number of flow priorities. */
274 enum modify_reg flow_mreg_c[MLX5_MREG_C_NUM];
275 /* Availibility of mreg_c's. */
276 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */
277 unsigned int ind_table_max_size; /* Maximum indirection table size. */
278 unsigned int max_dump_files_num; /* Maximum dump files per queue. */
279 unsigned int log_hp_size; /* Single hairpin queue data size in total. */
280 int txqs_inline; /* Queue number threshold for inlining. */
281 int txq_inline_min; /* Minimal amount of data bytes to inline. */
282 int txq_inline_max; /* Max packet size for inlining with SEND. */
283 int txq_inline_mpw; /* Max packet size for inlining with eMPW. */
284 int tx_pp; /* Timestamp scheduling granularity in nanoseconds. */
285 int tx_skew; /* Tx scheduling skew between WQE and data on wire. */
286 struct mlx5_hca_attr hca_attr; /* HCA attributes. */
287 struct mlx5_lro_config lro; /* LRO configuration. */
291 /* Structure for VF VLAN workaround. */
292 struct mlx5_vf_vlan {
297 /* Flow drop context necessary due to Verbs API. */
299 struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */
300 struct mlx5_rxq_obj *rxq; /* Rx queue object. */
303 /* Loopback dummy queue resources required due to Verbs API. */
305 struct ibv_qp *qp; /* QP object. */
306 void *ibv_cq; /* Completion queue. */
307 uint16_t refcnt; /* Reference count for representors. */
310 #define MLX5_COUNTERS_PER_POOL 512
311 #define MLX5_MAX_PENDING_QUERIES 4
312 #define MLX5_CNT_CONTAINER_RESIZE 64
313 #define MLX5_CNT_SHARED_OFFSET 0x80000000
314 #define IS_BATCH_CNT(cnt) (((cnt) & (MLX5_CNT_SHARED_OFFSET - 1)) >= \
315 MLX5_CNT_BATCH_OFFSET)
316 #define MLX5_CNT_SIZE (sizeof(struct mlx5_flow_counter))
317 #define MLX5_AGE_SIZE (sizeof(struct mlx5_age_param))
319 #define MLX5_CNT_LEN(pool) \
321 ((pool)->is_aged ? MLX5_AGE_SIZE : 0))
322 #define MLX5_POOL_GET_CNT(pool, index) \
323 ((struct mlx5_flow_counter *) \
324 ((uint8_t *)((pool) + 1) + (index) * (MLX5_CNT_LEN(pool))))
325 #define MLX5_CNT_ARRAY_IDX(pool, cnt) \
326 ((int)(((uint8_t *)(cnt) - (uint8_t *)((pool) + 1)) / \
329 * The pool index and offset of counter in the pool array makes up the
330 * counter index. In case the counter is from pool 0 and offset 0, it
331 * should plus 1 to avoid index 0, since 0 means invalid counter index
334 #define MLX5_MAKE_CNT_IDX(pi, offset) \
335 ((pi) * MLX5_COUNTERS_PER_POOL + (offset) + 1)
336 #define MLX5_CNT_TO_AGE(cnt) \
337 ((struct mlx5_age_param *)((cnt) + 1))
339 * The maximum single counter is 0x800000 as MLX5_CNT_BATCH_OFFSET
340 * defines. The pool size is 512, pool index should never reach
343 #define POOL_IDX_INVALID UINT16_MAX
347 AGE_FREE, /* Initialized state. */
348 AGE_CANDIDATE, /* Counter assigned to flows. */
349 AGE_TMOUT, /* Timeout, wait for rte_flow_get_aged_flows and destroy. */
352 enum mlx5_counter_type {
353 MLX5_COUNTER_TYPE_ORIGIN,
354 MLX5_COUNTER_TYPE_AGE,
355 MLX5_COUNTER_TYPE_MAX,
358 /* Counter age parameter. */
359 struct mlx5_age_param {
360 uint16_t state; /**< Age state (atomically accessed). */
361 uint16_t port_id; /**< Port id of the counter. */
362 uint32_t timeout:24; /**< Aging timeout in seconds. */
363 uint32_t sec_since_last_hit;
364 /**< Time in seconds since last hit (atomically accessed). */
365 void *context; /**< Flow counter age context. */
368 struct flow_counter_stats {
373 /* Shared counters information for counters. */
374 struct mlx5_flow_counter_shared {
376 uint32_t refcnt; /* Only for shared action management. */
377 uint32_t id; /* User counter ID for legacy sharing. */
381 struct mlx5_flow_counter_pool;
382 /* Generic counters information. */
383 struct mlx5_flow_counter {
386 * User-defined counter shared info is only used during
387 * counter active time. And aging counter sharing is not
388 * supported, so active shared counter will not be chained
389 * to the aging list. For shared counter, only when it is
390 * released, the TAILQ entry memory will be used, at that
391 * time, shared memory is not used anymore.
393 * Similarly to none-batch counter dcs, since it doesn't
394 * support aging, while counter is allocated, the entry
395 * memory is not used anymore. In this case, as bytes
396 * memory is used only when counter is allocated, and
397 * entry memory is used only when counter is free. The
398 * dcs pointer can be saved to these two different place
399 * at different stage. It will eliminate the individual
400 * counter extend struct.
402 TAILQ_ENTRY(mlx5_flow_counter) next;
403 /**< Pointer to the next flow counter structure. */
405 struct mlx5_flow_counter_shared shared_info;
406 /**< Shared counter information. */
407 void *dcs_when_active;
409 * For non-batch mode, the dcs will be saved
410 * here when the counter is free.
415 uint64_t hits; /**< Reset value of hits packets. */
416 struct mlx5_flow_counter_pool *pool; /**< Counter pool. */
419 uint64_t bytes; /**< Reset value of bytes. */
422 * For non-batch mode, the dcs will be saved here
423 * when the counter is free.
426 void *action; /**< Pointer to the dv action. */
429 TAILQ_HEAD(mlx5_counters, mlx5_flow_counter);
431 /* Generic counter pool structure - query is in pool resolution. */
432 struct mlx5_flow_counter_pool {
433 TAILQ_ENTRY(mlx5_flow_counter_pool) next;
434 struct mlx5_counters counters[2]; /* Free counter list. */
435 struct mlx5_devx_obj *min_dcs;
436 /* The devx object of the minimum counter ID. */
437 uint64_t time_of_last_age_check;
438 /* System time (from rte_rdtsc()) read in the last aging check. */
439 uint32_t index:30; /* Pool index in container. */
440 uint32_t is_aged:1; /* Pool with aging counter. */
441 volatile uint32_t query_gen:1; /* Query round. */
442 rte_spinlock_t sl; /* The pool lock. */
443 rte_spinlock_t csl; /* The pool counter free list lock. */
444 struct mlx5_counter_stats_raw *raw;
445 struct mlx5_counter_stats_raw *raw_hw;
446 /* The raw on HW working. */
449 /* Memory management structure for group of counter statistics raws. */
450 struct mlx5_counter_stats_mem_mng {
451 LIST_ENTRY(mlx5_counter_stats_mem_mng) next;
452 struct mlx5_counter_stats_raw *raws;
453 struct mlx5_devx_obj *dm;
457 /* Raw memory structure for the counter statistics values of a pool. */
458 struct mlx5_counter_stats_raw {
459 LIST_ENTRY(mlx5_counter_stats_raw) next;
460 struct mlx5_counter_stats_mem_mng *mem_mng;
461 volatile struct flow_counter_stats *data;
464 TAILQ_HEAD(mlx5_counter_pools, mlx5_flow_counter_pool);
466 /* Counter global management structure. */
467 struct mlx5_flow_counter_mng {
468 volatile uint16_t n_valid; /* Number of valid pools. */
469 uint16_t n; /* Number of pools. */
470 uint16_t last_pool_idx; /* Last used pool index */
471 int min_id; /* The minimum counter ID in the pools. */
472 int max_id; /* The maximum counter ID in the pools. */
473 rte_spinlock_t pool_update_sl; /* The pool update lock. */
474 rte_spinlock_t csl[MLX5_COUNTER_TYPE_MAX];
475 /* The counter free list lock. */
476 struct mlx5_counters counters[MLX5_COUNTER_TYPE_MAX];
477 /* Free counter list. */
478 struct mlx5_flow_counter_pool **pools; /* Counter pool array. */
479 struct mlx5_counter_stats_mem_mng *mem_mng;
480 /* Hold the memory management for the next allocated pools raws. */
481 struct mlx5_counters flow_counters; /* Legacy flow counter list. */
482 uint8_t pending_queries;
484 uint8_t query_thread_on;
485 bool relaxed_ordering_read;
486 bool relaxed_ordering_write;
487 bool counter_fallback; /* Use counter fallback management. */
488 LIST_HEAD(mem_mngs, mlx5_counter_stats_mem_mng) mem_mngs;
489 LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws;
492 /* ASO structures. */
493 #define MLX5_ASO_QUEUE_LOG_DESC 10
498 struct mlx5_devx_cq cq_obj;
502 struct mlx5_aso_sq_elem {
505 struct mlx5_aso_age_pool *pool;
508 struct mlx5_aso_mtr *mtr;
510 struct mlx5_aso_ct_action *ct;
519 struct mlx5_aso_cq cq;
520 struct mlx5_devx_sq sq_obj;
521 volatile uint64_t *uar_addr;
522 struct mlx5_pmd_mr mr;
527 struct mlx5_aso_sq_elem elts[1 << MLX5_ASO_QUEUE_LOG_DESC];
528 uint16_t next; /* Pool index of the next pool to query. */
531 struct mlx5_aso_age_action {
532 LIST_ENTRY(mlx5_aso_age_action) next;
535 /* Following fields relevant only when action is active. */
536 uint16_t offset; /* Offset of ASO Flow Hit flag in DevX object. */
537 struct mlx5_age_param age_params;
540 #define MLX5_ASO_AGE_ACTIONS_PER_POOL 512
542 struct mlx5_aso_age_pool {
543 struct mlx5_devx_obj *flow_hit_aso_obj;
544 uint16_t index; /* Pool index in pools array. */
545 uint64_t time_of_last_age_check; /* In seconds. */
546 struct mlx5_aso_age_action actions[MLX5_ASO_AGE_ACTIONS_PER_POOL];
549 LIST_HEAD(aso_age_list, mlx5_aso_age_action);
551 struct mlx5_aso_age_mng {
552 struct mlx5_aso_age_pool **pools;
553 uint16_t n; /* Total number of pools. */
554 uint16_t next; /* Number of pools in use, index of next free pool. */
555 rte_spinlock_t resize_sl; /* Lock for resize objects. */
556 rte_spinlock_t free_sl; /* Lock for free list access. */
557 struct aso_age_list free; /* Free age actions list - ready to use. */
558 struct mlx5_aso_sq aso_sq; /* ASO queue objects. */
561 /* Management structure for geneve tlv option */
562 struct mlx5_geneve_tlv_option_resource {
563 struct mlx5_devx_obj *obj; /* Pointer to the geneve tlv opt object. */
564 rte_be16_t option_class; /* geneve tlv opt class.*/
565 uint8_t option_type; /* geneve tlv opt type.*/
566 uint8_t length; /* geneve tlv opt length. */
567 uint32_t refcnt; /* geneve tlv object reference counter */
571 #define MLX5_AGE_EVENT_NEW 1
572 #define MLX5_AGE_TRIGGER 2
573 #define MLX5_AGE_SET(age_info, BIT) \
574 ((age_info)->flags |= (1 << (BIT)))
575 #define MLX5_AGE_UNSET(age_info, BIT) \
576 ((age_info)->flags &= ~(1 << (BIT)))
577 #define MLX5_AGE_GET(age_info, BIT) \
578 ((age_info)->flags & (1 << (BIT)))
579 #define GET_PORT_AGE_INFO(priv) \
580 (&((priv)->sh->port[(priv)->dev_port - 1].age_info))
581 /* Current time in seconds. */
582 #define MLX5_CURR_TIME_SEC (rte_rdtsc() / rte_get_tsc_hz())
584 /* Aging information for per port. */
585 struct mlx5_age_info {
586 uint8_t flags; /* Indicate if is new event or need to be triggered. */
587 struct mlx5_counters aged_counters; /* Aged counter list. */
588 struct aso_age_list aged_aso; /* Aged ASO actions list. */
589 rte_spinlock_t aged_sl; /* Aged flow list lock. */
592 /* Per port data of shared IB device. */
593 struct mlx5_dev_shared_port {
595 uint32_t devx_ih_port_id;
597 * Interrupt handler port_id. Used by shared interrupt
598 * handler to find the corresponding rte_eth device
599 * by IB port index. If value is equal or greater
600 * RTE_MAX_ETHPORTS it means there is no subhandler
601 * installed for specified IB port index.
603 struct mlx5_age_info age_info;
604 /* Aging information for per port. */
608 * Max number of actions per DV flow.
609 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED
610 * in rdma-core file providers/mlx5/verbs.c.
612 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8
614 /* ASO flow meter structures */
615 /* Modify this value if enum rte_mtr_color changes. */
616 #define RTE_MTR_DROPPED RTE_COLORS
617 /* Yellow is now supported. */
618 #define MLX5_MTR_RTE_COLORS (RTE_COLOR_YELLOW + 1)
619 /* table_id 22 bits in mlx5_flow_tbl_key so limit policy number. */
620 #define MLX5_MAX_SUB_POLICY_TBL_NUM 0x3FFFFF
621 #define MLX5_INVALID_POLICY_ID UINT32_MAX
622 /* Suffix table_id on MLX5_FLOW_TABLE_LEVEL_METER. */
623 #define MLX5_MTR_TABLE_ID_SUFFIX 1
624 /* Drop table_id on MLX5_FLOW_TABLE_LEVEL_METER. */
625 #define MLX5_MTR_TABLE_ID_DROP 2
626 /* Priority of the meter policy matcher. */
627 #define MLX5_MTR_POLICY_MATCHER_PRIO 0
628 /* Default policy. */
629 #define MLX5_MTR_POLICY_MODE_DEF 1
630 /* Only green color valid. */
631 #define MLX5_MTR_POLICY_MODE_OG 2
632 /* Only yellow color valid. */
633 #define MLX5_MTR_POLICY_MODE_OY 3
635 enum mlx5_meter_domain {
636 MLX5_MTR_DOMAIN_INGRESS,
637 MLX5_MTR_DOMAIN_EGRESS,
638 MLX5_MTR_DOMAIN_TRANSFER,
641 #define MLX5_MTR_DOMAIN_INGRESS_BIT (1 << MLX5_MTR_DOMAIN_INGRESS)
642 #define MLX5_MTR_DOMAIN_EGRESS_BIT (1 << MLX5_MTR_DOMAIN_EGRESS)
643 #define MLX5_MTR_DOMAIN_TRANSFER_BIT (1 << MLX5_MTR_DOMAIN_TRANSFER)
644 #define MLX5_MTR_ALL_DOMAIN_BIT (MLX5_MTR_DOMAIN_INGRESS_BIT | \
645 MLX5_MTR_DOMAIN_EGRESS_BIT | \
646 MLX5_MTR_DOMAIN_TRANSFER_BIT)
648 /* The color tag rule structure. */
649 struct mlx5_sub_policy_color_rule {
651 /* The color rule. */
652 struct mlx5_flow_dv_matcher *matcher;
653 /* The color matcher. */
654 TAILQ_ENTRY(mlx5_sub_policy_color_rule) next_port;
655 /**< Pointer to the next color rule structure. */
657 /* On which src port this rule applied. */
660 TAILQ_HEAD(mlx5_sub_policy_color_rules, mlx5_sub_policy_color_rule);
663 * Meter sub-policy structure.
664 * Each RSS TIR in meter policy need its own sub-policy resource.
666 struct mlx5_flow_meter_sub_policy {
667 uint32_t main_policy_id:1;
668 /* Main policy id is same as this sub_policy id. */
670 /* Index to sub_policy ipool entity. */
672 /* Point to struct mlx5_flow_meter_policy. */
673 struct mlx5_flow_tbl_resource *tbl_rsc;
674 /* The sub-policy table resource. */
675 uint32_t rix_hrxq[MLX5_MTR_RTE_COLORS];
676 /* Index to TIR resource. */
677 struct mlx5_flow_tbl_resource *jump_tbl[MLX5_MTR_RTE_COLORS];
678 /* Meter jump/drop table. */
679 struct mlx5_sub_policy_color_rules color_rules[RTE_COLORS];
680 /* List for the color rules. */
683 struct mlx5_meter_policy_acts {
685 /* Number of actions. */
686 void *dv_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS];
690 struct mlx5_meter_policy_action_container {
692 /* Index to the mark action. */
693 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
694 /* Pointer to modify header resource in cache. */
696 /* Fate action type. */
698 struct rte_flow_action *rss;
699 /* Rss action configuration. */
700 uint32_t rix_port_id_action;
701 /* Index to port ID action resource. */
702 void *dr_jump_action[MLX5_MTR_DOMAIN_MAX];
703 /* Jump/drop action per color. */
705 /* Queue action configuration. */
707 uint32_t next_mtr_id;
708 /* The next meter id. */
709 void *next_sub_policy;
710 /* Next meter's sub-policy. */
715 /* Flow meter policy parameter structure. */
716 struct mlx5_flow_meter_policy {
717 struct rte_eth_dev *dev;
718 /* The port dev on which policy is created. */
720 /* Is RSS policy table. */
722 /* Rule applies to ingress domain. */
724 /* Rule applies to egress domain. */
726 /* Rule applies to transfer domain. */
728 /* Is queue action in policy table. */
729 uint32_t is_hierarchy:1;
730 /* Is meter action in policy table. */
732 /* If yellow color policy is skipped. */
734 /* If green color policy is skipped. */
738 struct mlx5_meter_policy_action_container act_cnt[MLX5_MTR_RTE_COLORS];
739 /* Policy actions container. */
740 void *dr_drop_action[MLX5_MTR_DOMAIN_MAX];
741 /* drop action for red color. */
742 uint16_t sub_policy_num;
743 /* Count sub policy tables, 3 bits per domain. */
744 struct mlx5_flow_meter_sub_policy **sub_policys[MLX5_MTR_DOMAIN_MAX];
745 /* Sub policy table array must be the end of struct. */
748 /* The maximum sub policy is relate to struct mlx5_rss_hash_fields[]. */
749 #define MLX5_MTR_RSS_MAX_SUB_POLICY 7
750 #define MLX5_MTR_SUB_POLICY_NUM_SHIFT 3
751 #define MLX5_MTR_SUB_POLICY_NUM_MASK 0x7
752 #define MLX5_MTRS_DEFAULT_RULE_PRIORITY 0xFFFF
753 #define MLX5_MTR_CHAIN_MAX_NUM 8
755 /* Flow meter default policy parameter structure.
756 * Policy index 0 is reserved by default policy table.
757 * Action per color as below:
758 * green - do nothing, yellow - do nothing, red - drop
760 struct mlx5_flow_meter_def_policy {
761 struct mlx5_flow_meter_sub_policy sub_policy;
762 /* Policy rules jump to other tables. */
763 void *dr_jump_action[RTE_COLORS];
764 /* Jump action per color. */
767 /* Meter parameter structure. */
768 struct mlx5_flow_meter_info {
772 /* Policy id, the first sub_policy idx. */
773 struct mlx5_flow_meter_profile *profile;
774 /**< Meter profile parameters. */
775 rte_spinlock_t sl; /**< Meter action spinlock. */
776 /** Set of stats counters to be enabled.
777 * @see enum rte_mtr_stats_type
779 uint32_t bytes_dropped:1;
780 /** Set bytes dropped stats to be enabled. */
781 uint32_t pkts_dropped:1;
782 /** Set packets dropped stats to be enabled. */
783 uint32_t active_state:1;
784 /**< Meter hw active state. */
786 /**< Meter shared or not. */
787 uint32_t is_enable:1;
788 /**< Meter disable/enable state. */
790 /**< Rule applies to egress traffic. */
793 * Instead of simply matching the properties of traffic as it would
794 * appear on a given DPDK port ID, enabling this attribute transfers
795 * a flow rule to the lowest possible level of any device endpoints
796 * found in the pattern.
798 * When supported, this effectively enables an application to
799 * re-route traffic not necessarily intended for it (e.g. coming
800 * from or addressed to different physical ports, VFs or
801 * applications) at the device level.
803 * It complements the behavior of some pattern items such as
804 * RTE_FLOW_ITEM_TYPE_PHY_PORT and is meaningless without them.
806 * When transferring flow rules, ingress and egress attributes keep
807 * their original meaning, as if processing traffic emitted or
808 * received by the application.
811 uint32_t def_policy:1;
812 /* Meter points to default policy. */
813 void *drop_rule[MLX5_MTR_DOMAIN_MAX];
814 /* Meter drop rule in drop table. */
816 /**< Color counter for drop. */
819 struct mlx5_indexed_pool *flow_ipool;
820 /**< Index pool for flow id. */
822 /**< Flow meter action. */
825 /* PPS(packets per second) map to BPS(Bytes per second).
826 * HW treat packet as 128bytes in PPS mode
828 #define MLX5_MTRS_PPS_MAP_BPS_SHIFT 7
830 /* RFC2697 parameter structure. */
831 struct mlx5_flow_meter_srtcm_rfc2697_prm {
834 * bit 24-28: cbs_exponent, bit 16-23 cbs_mantissa,
835 * bit 8-12: cir_exponent, bit 0-7 cir_mantissa.
839 * bit 24-28: ebs_exponent, bit 16-23 ebs_mantissa,
840 * bit 8-12: eir_exponent, bit 0-7 eir_mantissa.
844 /* Flow meter profile structure. */
845 struct mlx5_flow_meter_profile {
846 TAILQ_ENTRY(mlx5_flow_meter_profile) next;
847 /**< Pointer to the next flow meter structure. */
848 uint32_t id; /**< Profile id. */
849 struct rte_mtr_meter_profile profile; /**< Profile detail. */
851 struct mlx5_flow_meter_srtcm_rfc2697_prm srtcm_prm;
852 /**< srtcm_rfc2697 struct. */
854 uint32_t ref_cnt; /**< Use count. */
855 uint32_t g_support:1; /**< If G color will be generated. */
856 uint32_t y_support:1; /**< If Y color will be generated. */
859 /* 2 meters in each ASO cache line */
860 #define MLX5_MTRS_CONTAINER_RESIZE 64
862 * The pool index and offset of meter in the pool array makes up the
863 * meter index. In case the meter is from pool 0 and offset 0, it
864 * should plus 1 to avoid index 0, since 0 means invalid meter index
867 #define MLX5_MAKE_MTR_IDX(pi, offset) \
868 ((pi) * MLX5_ASO_MTRS_PER_POOL + (offset) + 1)
870 /*aso flow meter state*/
871 enum mlx5_aso_mtr_state {
872 ASO_METER_FREE, /* In free list. */
873 ASO_METER_WAIT, /* ACCESS_ASO WQE in progress. */
874 ASO_METER_READY, /* CQE received. */
877 /* Generic aso_flow_meter information. */
878 struct mlx5_aso_mtr {
879 LIST_ENTRY(mlx5_aso_mtr) next;
880 struct mlx5_flow_meter_info fm;
881 /**< Pointer to the next aso flow meter structure. */
882 uint8_t state; /**< ASO flow meter state. */
886 /* Generic aso_flow_meter pool structure. */
887 struct mlx5_aso_mtr_pool {
888 struct mlx5_aso_mtr mtrs[MLX5_ASO_MTRS_PER_POOL];
889 /*Must be the first in pool*/
890 struct mlx5_devx_obj *devx_obj;
891 /* The devx object of the minimum aso flow meter ID. */
892 uint32_t index; /* Pool index in management structure. */
895 LIST_HEAD(aso_meter_list, mlx5_aso_mtr);
896 /* Pools management structure for ASO flow meter pools. */
897 struct mlx5_aso_mtr_pools_mng {
898 volatile uint16_t n_valid; /* Number of valid pools. */
899 uint16_t n; /* Number of pools. */
900 rte_spinlock_t mtrsl; /* The ASO flow meter free list lock. */
901 struct aso_meter_list meters; /* Free ASO flow meter list. */
902 struct mlx5_aso_sq sq; /*SQ using by ASO flow meter. */
903 struct mlx5_aso_mtr_pool **pools; /* ASO flow meter pool array. */
906 /* Meter management structure for global flow meter resource. */
907 struct mlx5_flow_mtr_mng {
908 struct mlx5_aso_mtr_pools_mng pools_mng;
909 /* Pools management structure for ASO flow meter pools. */
910 struct mlx5_flow_meter_def_policy *def_policy[MLX5_MTR_DOMAIN_MAX];
911 /* Default policy table. */
912 uint32_t def_policy_id;
913 /* Default policy id. */
914 uint32_t def_policy_ref_cnt;
915 /** def_policy meter use count. */
916 struct mlx5_flow_tbl_resource *drop_tbl[MLX5_MTR_DOMAIN_MAX];
917 /* Meter drop table. */
918 struct mlx5_flow_dv_matcher *
919 drop_matcher[MLX5_MTR_DOMAIN_MAX][MLX5_REG_BITS];
920 /* Matcher meter in drop table. */
921 struct mlx5_flow_dv_matcher *def_matcher[MLX5_MTR_DOMAIN_MAX];
922 /* Default matcher in drop table. */
923 void *def_rule[MLX5_MTR_DOMAIN_MAX];
924 /* Default rule in drop table. */
925 uint8_t max_mtr_bits;
926 /* Indicate how many bits are used by meter id at the most. */
927 uint8_t max_mtr_flow_bits;
928 /* Indicate how many bits are used by meter flow id at the most. */
931 /* Table key of the hash organization. */
932 union mlx5_flow_tbl_key {
934 /* Table ID should be at the lowest address. */
935 uint32_t level; /**< Level of the table. */
936 uint32_t id:22; /**< ID of the table. */
937 uint32_t dummy:1; /**< Dummy table for DV API. */
938 uint32_t is_fdb:1; /**< 1 - FDB, 0 - NIC TX/RX. */
939 uint32_t is_egress:1; /**< 1 - egress, 0 - ingress. */
940 uint32_t reserved:7; /**< must be zero for comparison. */
942 uint64_t v64; /**< full 64bits value of key */
945 /* Table structure. */
946 struct mlx5_flow_tbl_resource {
947 void *obj; /**< Pointer to DR table object. */
948 uint32_t refcnt; /**< Reference counter. */
951 #define MLX5_MAX_TABLES UINT16_MAX
952 #define MLX5_HAIRPIN_TX_TABLE (UINT16_MAX - 1)
953 /* Reserve the last two tables for metadata register copy. */
954 #define MLX5_FLOW_MREG_ACT_TABLE_GROUP (MLX5_MAX_TABLES - 1)
955 #define MLX5_FLOW_MREG_CP_TABLE_GROUP (MLX5_MAX_TABLES - 2)
956 /* Tables for metering splits should be added here. */
957 #define MLX5_FLOW_TABLE_LEVEL_METER (MLX5_MAX_TABLES - 3)
958 #define MLX5_FLOW_TABLE_LEVEL_POLICY (MLX5_MAX_TABLES - 4)
959 #define MLX5_MAX_TABLES_EXTERNAL MLX5_FLOW_TABLE_LEVEL_POLICY
960 #define MLX5_MAX_TABLES_FDB UINT16_MAX
961 #define MLX5_FLOW_TABLE_FACTOR 10
963 /* ID generation structure. */
964 struct mlx5_flow_id_pool {
965 uint32_t *free_arr; /**< Pointer to the a array of free values. */
967 /**< The next index that can be used without any free elements. */
968 uint32_t *curr; /**< Pointer to the index to pop. */
969 uint32_t *last; /**< Pointer to the last element in the empty arrray. */
970 uint32_t max_id; /**< Maximum id can be allocated from the pool. */
973 /* Tx pacing queue structure - for Clock and Rearm queues. */
974 struct mlx5_txpp_wq {
975 /* Completion Queue related data.*/
976 struct mlx5_devx_cq cq_obj;
979 /* Send Queue related data.*/
980 struct mlx5_devx_sq sq_obj;
981 uint16_t sq_size; /* Number of WQEs in the queue. */
982 uint16_t sq_ci; /* Next WQE to execute. */
985 /* Tx packet pacing internal timestamp. */
986 struct mlx5_txpp_ts {
991 /* Tx packet pacing structure. */
992 struct mlx5_dev_txpp {
993 pthread_mutex_t mutex; /* Pacing create/destroy mutex. */
994 uint32_t refcnt; /* Pacing reference counter. */
995 uint32_t freq; /* Timestamp frequency, Hz. */
996 uint32_t tick; /* Completion tick duration in nanoseconds. */
997 uint32_t test; /* Packet pacing test mode. */
998 int32_t skew; /* Scheduling skew. */
999 struct rte_intr_handle intr_handle; /* Periodic interrupt. */
1000 void *echan; /* Event Channel. */
1001 struct mlx5_txpp_wq clock_queue; /* Clock Queue. */
1002 struct mlx5_txpp_wq rearm_queue; /* Clock Queue. */
1003 void *pp; /* Packet pacing context. */
1004 uint16_t pp_id; /* Packet pacing context index. */
1005 uint16_t ts_n; /* Number of captured timestamps. */
1006 uint16_t ts_p; /* Pointer to statisticks timestamp. */
1007 struct mlx5_txpp_ts *tsa; /* Timestamps sliding window stats. */
1008 struct mlx5_txpp_ts ts; /* Cached completion id/timestamp. */
1009 uint32_t sync_lost:1; /* ci/timestamp synchronization lost. */
1010 /* Statistics counters. */
1011 uint64_t err_miss_int; /* Missed service interrupt. */
1012 uint64_t err_rearm_queue; /* Rearm Queue errors. */
1013 uint64_t err_clock_queue; /* Clock Queue errors. */
1014 uint64_t err_ts_past; /* Timestamp in the past. */
1015 uint64_t err_ts_future; /* Timestamp in the distant future. */
1018 /* Supported flex parser profile ID. */
1019 enum mlx5_flex_parser_profile_id {
1020 MLX5_FLEX_PARSER_ECPRI_0 = 0,
1021 MLX5_FLEX_PARSER_MAX = 8,
1024 /* Sample ID information of flex parser structure. */
1025 struct mlx5_flex_parser_profiles {
1026 uint32_t num; /* Actual number of samples. */
1027 uint32_t ids[8]; /* Sample IDs for this profile. */
1028 uint8_t offset[8]; /* Bytes offset of each parser. */
1029 void *obj; /* Flex parser node object. */
1032 /* Max member ports per bonding device. */
1033 #define MLX5_BOND_MAX_PORTS 2
1035 /* Bonding device information. */
1036 struct mlx5_bond_info {
1037 int n_port; /* Number of bond member ports. */
1039 char ifname[MLX5_NAMESIZE + 1];
1041 char ifname[MLX5_NAMESIZE + 1];
1043 struct rte_pci_addr pci_addr;
1044 } ports[MLX5_BOND_MAX_PORTS];
1047 /* Number of connection tracking objects per pool: must be a power of 2. */
1048 #define MLX5_ASO_CT_ACTIONS_PER_POOL 64
1050 /* Generate incremental and unique CT index from pool and offset. */
1051 #define MLX5_MAKE_CT_IDX(pool, offset) \
1052 ((pool) * MLX5_ASO_CT_ACTIONS_PER_POOL + (offset) + 1)
1054 /* ASO Conntrack state. */
1055 enum mlx5_aso_ct_state {
1056 ASO_CONNTRACK_FREE, /* Inactive, in the free list. */
1057 ASO_CONNTRACK_WAIT, /* WQE sent in the SQ. */
1058 ASO_CONNTRACK_READY, /* CQE received w/o error. */
1059 ASO_CONNTRACK_QUERY, /* WQE for query sent. */
1060 ASO_CONNTRACK_MAX, /* Guard. */
1063 /* Generic ASO connection tracking structure. */
1064 struct mlx5_aso_ct_action {
1065 LIST_ENTRY(mlx5_aso_ct_action) next; /* Pointer to the next ASO CT. */
1066 void *dr_action_orig; /* General action object for original dir. */
1067 void *dr_action_rply; /* General action object for reply dir. */
1068 uint32_t refcnt; /* Action used count in device flows. */
1069 uint16_t offset; /* Offset of ASO CT in DevX objects bulk. */
1070 uint16_t peer; /* The only peer port index could also use this CT. */
1071 enum mlx5_aso_ct_state state; /* ASO CT state. */
1072 bool is_original; /* The direction of the DR action to be used. */
1075 /* CT action object state update. */
1076 #define MLX5_ASO_CT_UPDATE_STATE(c, s) \
1077 __atomic_store_n(&((c)->state), (s), __ATOMIC_RELAXED)
1079 /* ASO connection tracking software pool definition. */
1080 struct mlx5_aso_ct_pool {
1081 uint16_t index; /* Pool index in pools array. */
1082 struct mlx5_devx_obj *devx_obj;
1083 /* The first devx object in the bulk, used for freeing (not yet). */
1084 struct mlx5_aso_ct_action actions[MLX5_ASO_CT_ACTIONS_PER_POOL];
1085 /* CT action structures bulk. */
1088 LIST_HEAD(aso_ct_list, mlx5_aso_ct_action);
1090 /* Pools management structure for ASO connection tracking pools. */
1091 struct mlx5_aso_ct_pools_mng {
1092 struct mlx5_aso_ct_pool **pools;
1093 uint16_t n; /* Total number of pools. */
1094 uint16_t next; /* Number of pools in use, index of next free pool. */
1095 rte_spinlock_t ct_sl; /* The ASO CT free list lock. */
1096 rte_rwlock_t resize_rwl; /* The ASO CT pool resize lock. */
1097 struct aso_ct_list free_cts; /* Free ASO CT objects list. */
1098 struct mlx5_aso_sq aso_sq; /* ASO queue objects. */
1102 * Shared Infiniband device context for Master/Representors
1103 * which belong to same IB device with multiple IB ports.
1105 struct mlx5_dev_ctx_shared {
1106 LIST_ENTRY(mlx5_dev_ctx_shared) next;
1108 uint32_t devx:1; /* Opened with DV. */
1109 uint32_t flow_hit_aso_en:1; /* Flow Hit ASO is supported. */
1110 uint32_t steering_format_version:4;
1111 /* Indicates the device steering logic format. */
1112 uint32_t meter_aso_en:1; /* Flow Meter ASO is supported. */
1113 uint32_t ct_aso_en:1; /* Connection Tracking ASO is supported. */
1114 uint32_t tunnel_header_0_1:1; /* tunnel_header_0_1 is supported. */
1115 uint32_t misc5_cap:1; /* misc5 matcher parameter is supported. */
1116 uint32_t reclaim_mode:1; /* Reclaim memory. */
1117 uint32_t max_port; /* Maximal IB device port index. */
1118 struct mlx5_bond_info bond; /* Bonding information. */
1119 struct mlx5_common_device *cdev; /* Backend mlx5 device. */
1120 uint32_t tdn; /* Transport Domain number. */
1121 char ibdev_name[MLX5_FS_NAME_MAX]; /* SYSFS dev name. */
1122 char ibdev_path[MLX5_FS_PATH_MAX]; /* SYSFS dev path for secondary */
1123 struct mlx5_dev_attr device_attr; /* Device properties. */
1124 int numa_node; /* Numa node of backing physical device. */
1125 /* Packet pacing related structure. */
1126 struct mlx5_dev_txpp txpp;
1127 /* Shared DV/DR flow data section. */
1128 uint32_t dv_meta_mask; /* flow META metadata supported mask. */
1129 uint32_t dv_mark_mask; /* flow MARK metadata supported mask. */
1130 uint32_t dv_regc0_mask; /* available bits of metatada reg_c[0]. */
1131 void *fdb_domain; /* FDB Direct Rules name space handle. */
1132 void *rx_domain; /* RX Direct Rules name space handle. */
1133 void *tx_domain; /* TX Direct Rules name space handle. */
1135 rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */
1136 rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX];
1137 /* UAR same-page access control required in 32bit implementations. */
1139 struct mlx5_hlist *flow_tbls;
1140 struct mlx5_flow_tunnel_hub *tunnel_hub;
1141 /* Direct Rules tables for FDB, NIC TX+RX */
1142 void *dr_drop_action; /* Pointer to DR drop action, any domain. */
1143 void *pop_vlan_action; /* Pointer to DR pop VLAN action. */
1144 struct mlx5_hlist *encaps_decaps; /* Encap/decap action hash list. */
1145 struct mlx5_hlist *modify_cmds;
1146 struct mlx5_hlist *tag_table;
1147 struct mlx5_list *port_id_action_list; /* Port ID action list. */
1148 struct mlx5_list *push_vlan_action_list; /* Push VLAN actions. */
1149 struct mlx5_list *sample_action_list; /* List of sample actions. */
1150 struct mlx5_list *dest_array_list;
1151 /* List of destination array actions. */
1152 struct mlx5_flow_counter_mng cmng; /* Counters management structure. */
1153 void *default_miss_action; /* Default miss action. */
1154 struct mlx5_indexed_pool *ipool[MLX5_IPOOL_MAX];
1155 struct mlx5_indexed_pool *mdh_ipools[MLX5_MAX_MODIFY_NUM];
1156 /* Shared interrupt handler section. */
1157 struct rte_intr_handle intr_handle; /* Interrupt handler for device. */
1158 struct rte_intr_handle intr_handle_devx; /* DEVX interrupt handler. */
1159 void *devx_comp; /* DEVX async comp obj. */
1160 struct mlx5_devx_obj *tis; /* TIS object. */
1161 struct mlx5_devx_obj *td; /* Transport domain. */
1162 void *tx_uar; /* Tx/packet pacing shared UAR. */
1163 struct mlx5_flex_parser_profiles fp[MLX5_FLEX_PARSER_MAX];
1164 /* Flex parser profiles information. */
1165 void *devx_rx_uar; /* DevX UAR for Rx. */
1166 struct mlx5_aso_age_mng *aso_age_mng;
1167 /* Management data for aging mechanism using ASO Flow Hit. */
1168 struct mlx5_geneve_tlv_option_resource *geneve_tlv_option_resource;
1169 /* Management structure for geneve tlv option */
1170 rte_spinlock_t geneve_tlv_opt_sl; /* Lock for geneve tlv resource */
1171 struct mlx5_flow_mtr_mng *mtrmng;
1172 /* Meter management structure. */
1173 struct mlx5_aso_ct_pools_mng *ct_mng;
1174 /* Management data for ASO connection tracking. */
1175 struct mlx5_lb_ctx self_lb; /* QP to enable self loopback for Devx. */
1176 struct mlx5_dev_shared_port port[]; /* per device port data array. */
1180 * Per-process private structure.
1181 * Caution, secondary process may rebuild the struct during port start.
1183 struct mlx5_proc_priv {
1184 size_t uar_table_sz;
1185 /* Size of UAR register table. */
1187 /* Table of UAR registers for each process. */
1190 /* MTR profile list. */
1191 TAILQ_HEAD(mlx5_mtr_profiles, mlx5_flow_meter_profile);
1193 TAILQ_HEAD(mlx5_legacy_flow_meters, mlx5_legacy_flow_meter);
1195 /* RSS description. */
1196 struct mlx5_flow_rss_desc {
1198 uint32_t queue_num; /**< Number of entries in @p queue. */
1199 uint64_t types; /**< Specific RSS hash types (see ETH_RSS_*). */
1200 uint64_t hash_fields; /* Verbs Hash fields. */
1201 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
1202 uint32_t key_len; /**< RSS hash key len. */
1203 uint32_t tunnel; /**< Queue in tunnel. */
1204 uint32_t shared_rss; /**< Shared RSS index. */
1205 struct mlx5_ind_table_obj *ind_tbl;
1206 /**< Indirection table for shared RSS hash RX queues. */
1208 uint16_t *queue; /**< Destination queues. */
1209 const uint16_t *const_q; /**< Const pointer convert. */
1213 #define MLX5_PROC_PRIV(port_id) \
1214 ((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private)
1216 /* Verbs/DevX Rx queue elements. */
1217 struct mlx5_rxq_obj {
1218 LIST_ENTRY(mlx5_rxq_obj) next; /* Pointer to the next element. */
1219 struct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */
1220 int fd; /* File descriptor for event channel */
1224 void *wq; /* Work Queue. */
1225 void *ibv_cq; /* Completion Queue. */
1228 struct mlx5_devx_obj *rq; /* DevX RQ object for hairpin. */
1230 struct mlx5_devx_rq rq_obj; /* DevX RQ object. */
1231 struct mlx5_devx_cq cq_obj; /* DevX CQ object. */
1237 /* Indirection table. */
1238 struct mlx5_ind_table_obj {
1239 LIST_ENTRY(mlx5_ind_table_obj) next; /* Pointer to the next element. */
1240 uint32_t refcnt; /* Reference counter. */
1243 void *ind_table; /**< Indirection table. */
1244 struct mlx5_devx_obj *rqt; /* DevX RQT object. */
1246 uint32_t queues_n; /**< Number of queues in the list. */
1247 uint16_t *queues; /**< Queue list. */
1250 /* Hash Rx queue. */
1253 struct mlx5_list_entry entry; /* List entry. */
1254 uint32_t standalone:1; /* This object used in shared action. */
1255 struct mlx5_ind_table_obj *ind_table; /* Indirection table. */
1258 void *qp; /* Verbs queue pair. */
1259 struct mlx5_devx_obj *tir; /* DevX TIR object. */
1261 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
1262 void *action; /* DV QP action pointer. */
1264 uint64_t hash_fields; /* Verbs Hash fields. */
1265 uint32_t rss_key_len; /* Hash key length in bytes. */
1266 uint32_t idx; /* Hash Rx queue index. */
1267 uint8_t rss_key[]; /* Hash key. */
1270 /* Verbs/DevX Tx queue elements. */
1271 struct mlx5_txq_obj {
1272 LIST_ENTRY(mlx5_txq_obj) next; /* Pointer to the next element. */
1273 struct mlx5_txq_ctrl *txq_ctrl; /* Pointer to the control queue. */
1277 void *cq; /* Completion Queue. */
1278 void *qp; /* Queue Pair. */
1281 struct mlx5_devx_obj *sq;
1282 /* DevX object for Sx queue. */
1283 struct mlx5_devx_obj *tis; /* The TIS object. */
1286 struct rte_eth_dev *dev;
1287 struct mlx5_devx_cq cq_obj;
1288 /* DevX CQ object and its resources. */
1289 struct mlx5_devx_sq sq_obj;
1290 /* DevX SQ object and its resources. */
1295 enum mlx5_rxq_modify_type {
1296 MLX5_RXQ_MOD_ERR2RST, /* modify state from error to reset. */
1297 MLX5_RXQ_MOD_RST2RDY, /* modify state from reset to ready. */
1298 MLX5_RXQ_MOD_RDY2ERR, /* modify state from ready to error. */
1299 MLX5_RXQ_MOD_RDY2RST, /* modify state from ready to reset. */
1302 enum mlx5_txq_modify_type {
1303 MLX5_TXQ_MOD_RST2RDY, /* modify state from reset to ready. */
1304 MLX5_TXQ_MOD_RDY2RST, /* modify state from ready to reset. */
1305 MLX5_TXQ_MOD_ERR2RDY, /* modify state from error to ready. */
1308 /* HW objects operations structure. */
1309 struct mlx5_obj_ops {
1310 int (*rxq_obj_modify_vlan_strip)(struct mlx5_rxq_obj *rxq_obj, int on);
1311 int (*rxq_obj_new)(struct rte_eth_dev *dev, uint16_t idx);
1312 int (*rxq_event_get)(struct mlx5_rxq_obj *rxq_obj);
1313 int (*rxq_obj_modify)(struct mlx5_rxq_obj *rxq_obj, uint8_t type);
1314 void (*rxq_obj_release)(struct mlx5_rxq_obj *rxq_obj);
1315 int (*ind_table_new)(struct rte_eth_dev *dev, const unsigned int log_n,
1316 struct mlx5_ind_table_obj *ind_tbl);
1317 int (*ind_table_modify)(struct rte_eth_dev *dev,
1318 const unsigned int log_n,
1319 const uint16_t *queues, const uint32_t queues_n,
1320 struct mlx5_ind_table_obj *ind_tbl);
1321 void (*ind_table_destroy)(struct mlx5_ind_table_obj *ind_tbl);
1322 int (*hrxq_new)(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq,
1323 int tunnel __rte_unused);
1324 int (*hrxq_modify)(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq,
1325 const uint8_t *rss_key,
1326 uint64_t hash_fields,
1327 const struct mlx5_ind_table_obj *ind_tbl);
1328 void (*hrxq_destroy)(struct mlx5_hrxq *hrxq);
1329 int (*drop_action_create)(struct rte_eth_dev *dev);
1330 void (*drop_action_destroy)(struct rte_eth_dev *dev);
1331 int (*txq_obj_new)(struct rte_eth_dev *dev, uint16_t idx);
1332 int (*txq_obj_modify)(struct mlx5_txq_obj *obj,
1333 enum mlx5_txq_modify_type type, uint8_t dev_port);
1334 void (*txq_obj_release)(struct mlx5_txq_obj *txq_obj);
1335 int (*lb_dummy_queue_create)(struct rte_eth_dev *dev);
1336 void (*lb_dummy_queue_release)(struct rte_eth_dev *dev);
1339 #define MLX5_RSS_HASH_FIELDS_LEN RTE_DIM(mlx5_rss_hash_fields)
1342 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */
1343 struct mlx5_dev_ctx_shared *sh; /* Shared device context. */
1344 uint32_t dev_port; /* Device port number. */
1345 struct rte_pci_device *pci_dev; /* Backend PCI device. */
1346 struct rte_ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */
1347 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES);
1348 /* Bit-field of MAC addresses owned by the PMD. */
1349 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */
1350 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */
1351 /* Device properties. */
1352 uint16_t mtu; /* Configured MTU. */
1353 unsigned int isolated:1; /* Whether isolated mode is enabled. */
1354 unsigned int representor:1; /* Device is a port representor. */
1355 unsigned int master:1; /* Device is a E-Switch master. */
1356 unsigned int txpp_en:1; /* Tx packet pacing enabled. */
1357 unsigned int sampler_en:1; /* Whether support sampler. */
1358 unsigned int mtr_en:1; /* Whether support meter. */
1359 unsigned int mtr_reg_share:1; /* Whether support meter REG_C share. */
1360 unsigned int lb_used:1; /* Loopback queue is referred to. */
1361 uint16_t domain_id; /* Switch domain identifier. */
1362 uint16_t vport_id; /* Associated VF vport index (if any). */
1363 uint32_t vport_meta_tag; /* Used for vport index match ove VF LAG. */
1364 uint32_t vport_meta_mask; /* Used for vport index field match mask. */
1365 uint16_t representor_id; /* UINT16_MAX if not a representor. */
1366 int32_t pf_bond; /* >=0, representor owner PF index in bonding. */
1367 unsigned int if_index; /* Associated kernel network device index. */
1369 unsigned int rxqs_n; /* RX queues array size. */
1370 unsigned int txqs_n; /* TX queues array size. */
1371 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */
1372 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */
1373 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
1374 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */
1375 unsigned int (*reta_idx)[]; /* RETA index table. */
1376 unsigned int reta_idx_n; /* RETA index size. */
1377 struct mlx5_drop drop_queue; /* Flow drop queues. */
1378 void *root_drop_action; /* Pointer to root drop action. */
1379 struct mlx5_indexed_pool *flows[MLX5_FLOW_TYPE_MAXI];
1380 /* RTE Flow rules. */
1381 uint32_t ctrl_flows; /* Control flow rules. */
1382 rte_spinlock_t flow_list_lock;
1383 struct mlx5_obj_ops obj_ops; /* HW objects operations. */
1384 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */
1385 LIST_HEAD(rxqobj, mlx5_rxq_obj) rxqsobj; /* Verbs/DevX Rx queues. */
1386 struct mlx5_list *hrxqs; /* Hash Rx queues. */
1387 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */
1388 LIST_HEAD(txqobj, mlx5_txq_obj) txqsobj; /* Verbs/DevX Tx queues. */
1389 /* Indirection tables. */
1390 LIST_HEAD(ind_tables, mlx5_ind_table_obj) ind_tbls;
1391 /* Pointer to next element. */
1392 rte_rwlock_t ind_tbls_lock;
1393 uint32_t refcnt; /**< Reference counter. */
1394 /**< Verbs modify header action object. */
1395 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
1396 uint8_t max_lro_msg_size;
1397 uint32_t link_speed_capa; /* Link speed capabilities. */
1398 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */
1399 struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */
1400 struct mlx5_dev_config config; /* Device configuration. */
1401 /* Context for Verbs allocator. */
1402 int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */
1403 int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */
1404 struct mlx5_nl_vlan_vmwa_context *vmwa_context; /* VLAN WA context. */
1405 struct mlx5_hlist *mreg_cp_tbl;
1406 /* Hash table of Rx metadata register copy table. */
1407 uint8_t mtr_sfx_reg; /* Meter prefix-suffix flow match REG_C. */
1408 uint8_t mtr_color_reg; /* Meter color match REG_C. */
1409 struct mlx5_legacy_flow_meters flow_meters; /* MTR list. */
1410 struct mlx5_l3t_tbl *mtr_profile_tbl; /* Meter index lookup table. */
1411 struct mlx5_l3t_tbl *policy_idx_tbl; /* Policy index lookup table. */
1412 struct mlx5_l3t_tbl *mtr_idx_tbl; /* Meter index lookup table. */
1413 uint8_t skip_default_rss_reta; /* Skip configuration of default reta. */
1414 uint8_t fdb_def_rule; /* Whether fdb jump to table 1 is configured. */
1415 struct mlx5_mp_id mp_id; /* ID of a multi-process process */
1416 LIST_HEAD(fdir, mlx5_fdir_flow) fdir_flows; /* fdir flows. */
1417 rte_spinlock_t shared_act_sl; /* Shared actions spinlock. */
1418 uint32_t rss_shared_actions; /* RSS shared actions. */
1419 struct mlx5_devx_obj *q_counters; /* DevX queue counter object. */
1420 uint32_t counter_set_id; /* Queue counter ID to set in DevX objects. */
1423 #define PORT_ID(priv) ((priv)->dev_data->port_id)
1424 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)])
1426 struct rte_hairpin_peer_info {
1430 uint16_t tx_explicit;
1431 uint16_t manual_bind;
1434 #define BUF_SIZE 1024
1435 enum dr_dump_rec_type {
1436 DR_DUMP_REC_TYPE_PMD_PKT_REFORMAT = 4410,
1437 DR_DUMP_REC_TYPE_PMD_MODIFY_HDR = 4420,
1438 DR_DUMP_REC_TYPE_PMD_COUNTER = 4430,
1443 int mlx5_getenv_int(const char *);
1444 int mlx5_proc_priv_init(struct rte_eth_dev *dev);
1445 void mlx5_proc_priv_uninit(struct rte_eth_dev *dev);
1446 int mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev,
1447 struct rte_eth_udp_tunnel *udp_tunnel);
1448 uint16_t mlx5_eth_find_next(uint16_t port_id, struct rte_device *odev);
1449 int mlx5_dev_close(struct rte_eth_dev *dev);
1450 int mlx5_net_remove(struct mlx5_common_device *cdev);
1451 bool mlx5_is_hpf(struct rte_eth_dev *dev);
1452 bool mlx5_is_sf_repr(struct rte_eth_dev *dev);
1453 void mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh);
1455 /* Macro to iterate over all valid ports for mlx5 driver. */
1456 #define MLX5_ETH_FOREACH_DEV(port_id, dev) \
1457 for (port_id = mlx5_eth_find_next(0, dev); \
1458 port_id < RTE_MAX_ETHPORTS; \
1459 port_id = mlx5_eth_find_next(port_id + 1, dev))
1460 int mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs);
1461 struct mlx5_dev_ctx_shared *
1462 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
1463 const struct mlx5_dev_config *config);
1464 void mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh);
1465 int mlx5_dev_ctx_shared_mempool_subscribe(struct rte_eth_dev *dev);
1466 void mlx5_free_table_hash_list(struct mlx5_priv *priv);
1467 int mlx5_alloc_table_hash_list(struct mlx5_priv *priv);
1468 void mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1469 struct mlx5_dev_config *config);
1470 void mlx5_set_metadata_mask(struct rte_eth_dev *dev);
1471 int mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
1472 struct mlx5_dev_config *config,
1473 struct rte_device *dpdk_dev);
1474 int mlx5_dev_configure(struct rte_eth_dev *dev);
1475 int mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info);
1476 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size);
1477 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
1478 int mlx5_hairpin_cap_get(struct rte_eth_dev *dev,
1479 struct rte_eth_hairpin_cap *cap);
1480 bool mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev);
1481 int mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev);
1482 int mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh);
1483 int mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh);
1484 int mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh);
1488 int mlx5_dev_configure(struct rte_eth_dev *dev);
1489 int mlx5_representor_info_get(struct rte_eth_dev *dev,
1490 struct rte_eth_representor_info *info);
1491 #define MLX5_REPRESENTOR_ID(pf, type, repr) \
1492 (((pf) << 14) + ((type) << 12) + ((repr) & 0xfff))
1493 #define MLX5_REPRESENTOR_REPR(repr_id) \
1495 #define MLX5_REPRESENTOR_TYPE(repr_id) \
1496 (((repr_id) >> 12) & 3)
1497 uint16_t mlx5_representor_id_encode(const struct mlx5_switch_info *info,
1498 enum rte_eth_representor_type hpf_type);
1499 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver,
1501 int mlx5_dev_infos_get(struct rte_eth_dev *dev,
1502 struct rte_eth_dev_info *info);
1503 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev);
1504 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
1505 int mlx5_hairpin_cap_get(struct rte_eth_dev *dev,
1506 struct rte_eth_hairpin_cap *cap);
1507 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev);
1508 struct mlx5_priv *mlx5_port_to_eswitch_info(uint16_t port, bool valid);
1509 struct mlx5_priv *mlx5_dev_to_eswitch_info(struct rte_eth_dev *dev);
1510 int mlx5_dev_configure_rss_reta(struct rte_eth_dev *dev);
1512 /* mlx5_ethdev_os.c */
1514 int mlx5_get_ifname(const struct rte_eth_dev *dev,
1515 char (*ifname)[MLX5_NAMESIZE]);
1516 unsigned int mlx5_ifindex(const struct rte_eth_dev *dev);
1517 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]);
1518 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu);
1519 int mlx5_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
1520 int mlx5_read_clock(struct rte_eth_dev *dev, uint64_t *clock);
1521 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete);
1522 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev,
1523 struct rte_eth_fc_conf *fc_conf);
1524 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev,
1525 struct rte_eth_fc_conf *fc_conf);
1526 void mlx5_dev_interrupt_handler(void *arg);
1527 void mlx5_dev_interrupt_handler_devx(void *arg);
1528 int mlx5_set_link_down(struct rte_eth_dev *dev);
1529 int mlx5_set_link_up(struct rte_eth_dev *dev);
1530 int mlx5_is_removed(struct rte_eth_dev *dev);
1531 int mlx5_sysfs_switch_info(unsigned int ifindex,
1532 struct mlx5_switch_info *info);
1533 void mlx5_translate_port_name(const char *port_name_in,
1534 struct mlx5_switch_info *port_info_out);
1535 void mlx5_intr_callback_unregister(const struct rte_intr_handle *handle,
1536 rte_intr_callback_fn cb_fn, void *cb_arg);
1537 int mlx5_sysfs_bond_info(unsigned int pf_ifindex, unsigned int *ifindex,
1539 int mlx5_get_module_info(struct rte_eth_dev *dev,
1540 struct rte_eth_dev_module_info *modinfo);
1541 int mlx5_get_module_eeprom(struct rte_eth_dev *dev,
1542 struct rte_dev_eeprom_info *info);
1543 int mlx5_os_read_dev_stat(struct mlx5_priv *priv,
1544 const char *ctr_name, uint64_t *stat);
1545 int mlx5_os_read_dev_counters(struct rte_eth_dev *dev, uint64_t *stats);
1546 int mlx5_os_get_stats_n(struct rte_eth_dev *dev);
1547 void mlx5_os_stats_init(struct rte_eth_dev *dev);
1551 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
1552 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
1553 uint32_t index, uint32_t vmdq);
1554 int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr);
1555 int mlx5_set_mc_addr_list(struct rte_eth_dev *dev,
1556 struct rte_ether_addr *mc_addr_set,
1557 uint32_t nb_mc_addr);
1561 int mlx5_rss_hash_update(struct rte_eth_dev *dev,
1562 struct rte_eth_rss_conf *rss_conf);
1563 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev,
1564 struct rte_eth_rss_conf *rss_conf);
1565 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size);
1566 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev,
1567 struct rte_eth_rss_reta_entry64 *reta_conf,
1568 uint16_t reta_size);
1569 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev,
1570 struct rte_eth_rss_reta_entry64 *reta_conf,
1571 uint16_t reta_size);
1575 int mlx5_promiscuous_enable(struct rte_eth_dev *dev);
1576 int mlx5_promiscuous_disable(struct rte_eth_dev *dev);
1577 int mlx5_allmulticast_enable(struct rte_eth_dev *dev);
1578 int mlx5_allmulticast_disable(struct rte_eth_dev *dev);
1582 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
1583 int mlx5_stats_reset(struct rte_eth_dev *dev);
1584 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats,
1586 int mlx5_xstats_reset(struct rte_eth_dev *dev);
1587 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
1588 struct rte_eth_xstat_name *xstats_names,
1593 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
1594 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on);
1595 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask);
1597 /* mlx5_vlan_os.c */
1599 void mlx5_vlan_vmwa_exit(void *ctx);
1600 void mlx5_vlan_vmwa_release(struct rte_eth_dev *dev,
1601 struct mlx5_vf_vlan *vf_vlan);
1602 void mlx5_vlan_vmwa_acquire(struct rte_eth_dev *dev,
1603 struct mlx5_vf_vlan *vf_vlan);
1604 void *mlx5_vlan_vmwa_init(struct rte_eth_dev *dev, uint32_t ifindex);
1606 /* mlx5_trigger.c */
1608 int mlx5_dev_start(struct rte_eth_dev *dev);
1609 int mlx5_dev_stop(struct rte_eth_dev *dev);
1610 int mlx5_traffic_enable(struct rte_eth_dev *dev);
1611 void mlx5_traffic_disable(struct rte_eth_dev *dev);
1612 int mlx5_traffic_restart(struct rte_eth_dev *dev);
1613 int mlx5_hairpin_queue_peer_update(struct rte_eth_dev *dev, uint16_t peer_queue,
1614 struct rte_hairpin_peer_info *current_info,
1615 struct rte_hairpin_peer_info *peer_info,
1616 uint32_t direction);
1617 int mlx5_hairpin_queue_peer_bind(struct rte_eth_dev *dev, uint16_t cur_queue,
1618 struct rte_hairpin_peer_info *peer_info,
1619 uint32_t direction);
1620 int mlx5_hairpin_queue_peer_unbind(struct rte_eth_dev *dev, uint16_t cur_queue,
1621 uint32_t direction);
1622 int mlx5_hairpin_bind(struct rte_eth_dev *dev, uint16_t rx_port);
1623 int mlx5_hairpin_unbind(struct rte_eth_dev *dev, uint16_t rx_port);
1624 int mlx5_hairpin_get_peer_ports(struct rte_eth_dev *dev, uint16_t *peer_ports,
1625 size_t len, uint32_t direction);
1629 int mlx5_flow_discover_mreg_c(struct rte_eth_dev *eth_dev);
1630 bool mlx5_flow_ext_mreg_supported(struct rte_eth_dev *dev);
1631 void mlx5_flow_print(struct rte_flow *flow);
1632 int mlx5_flow_validate(struct rte_eth_dev *dev,
1633 const struct rte_flow_attr *attr,
1634 const struct rte_flow_item items[],
1635 const struct rte_flow_action actions[],
1636 struct rte_flow_error *error);
1637 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev,
1638 const struct rte_flow_attr *attr,
1639 const struct rte_flow_item items[],
1640 const struct rte_flow_action actions[],
1641 struct rte_flow_error *error);
1642 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow,
1643 struct rte_flow_error *error);
1644 void mlx5_flow_list_flush(struct rte_eth_dev *dev, enum mlx5_flow_type type,
1646 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error);
1647 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow,
1648 const struct rte_flow_action *action, void *data,
1649 struct rte_flow_error *error);
1650 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable,
1651 struct rte_flow_error *error);
1652 int mlx5_flow_ops_get(struct rte_eth_dev *dev, const struct rte_flow_ops **ops);
1653 int mlx5_flow_start_default(struct rte_eth_dev *dev);
1654 void mlx5_flow_stop_default(struct rte_eth_dev *dev);
1655 int mlx5_flow_verify(struct rte_eth_dev *dev);
1656 int mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, uint32_t queue);
1657 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev,
1658 struct rte_flow_item_eth *eth_spec,
1659 struct rte_flow_item_eth *eth_mask,
1660 struct rte_flow_item_vlan *vlan_spec,
1661 struct rte_flow_item_vlan *vlan_mask);
1662 int mlx5_ctrl_flow(struct rte_eth_dev *dev,
1663 struct rte_flow_item_eth *eth_spec,
1664 struct rte_flow_item_eth *eth_mask);
1665 int mlx5_flow_lacp_miss(struct rte_eth_dev *dev);
1666 struct rte_flow *mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev);
1667 void mlx5_flow_async_pool_query_handle(struct mlx5_dev_ctx_shared *sh,
1668 uint64_t async_id, int status);
1669 void mlx5_set_query_alarm(struct mlx5_dev_ctx_shared *sh);
1670 void mlx5_flow_query_alarm(void *arg);
1671 uint32_t mlx5_counter_alloc(struct rte_eth_dev *dev);
1672 void mlx5_counter_free(struct rte_eth_dev *dev, uint32_t cnt);
1673 int mlx5_counter_query(struct rte_eth_dev *dev, uint32_t cnt,
1674 bool clear, uint64_t *pkts, uint64_t *bytes);
1675 int mlx5_flow_dev_dump(struct rte_eth_dev *dev, struct rte_flow *flow,
1676 FILE *file, struct rte_flow_error *error);
1677 int save_dump_file(const unsigned char *data, uint32_t size,
1678 uint32_t type, uint32_t id, void *arg, FILE *file);
1679 int mlx5_flow_query_counter(struct rte_eth_dev *dev, struct rte_flow *flow,
1680 struct rte_flow_query_count *count, struct rte_flow_error *error);
1681 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1682 int mlx5_flow_dev_dump_ipool(struct rte_eth_dev *dev, struct rte_flow *flow,
1683 FILE *file, struct rte_flow_error *error);
1685 void mlx5_flow_rxq_dynf_metadata_set(struct rte_eth_dev *dev);
1686 int mlx5_flow_get_aged_flows(struct rte_eth_dev *dev, void **contexts,
1687 uint32_t nb_contexts, struct rte_flow_error *error);
1688 int mlx5_validate_action_ct(struct rte_eth_dev *dev,
1689 const struct rte_flow_action_conntrack *conntrack,
1690 struct rte_flow_error *error);
1695 int mlx5_mp_os_primary_handle(const struct rte_mp_msg *mp_msg,
1697 int mlx5_mp_os_secondary_handle(const struct rte_mp_msg *mp_msg,
1699 void mlx5_mp_os_req_start_rxtx(struct rte_eth_dev *dev);
1700 void mlx5_mp_os_req_stop_rxtx(struct rte_eth_dev *dev);
1701 int mlx5_mp_os_req_queue_control(struct rte_eth_dev *dev, uint16_t queue_id,
1702 enum mlx5_mp_req_type req_type);
1706 int mlx5_pmd_socket_init(void);
1708 /* mlx5_flow_meter.c */
1710 int mlx5_flow_meter_ops_get(struct rte_eth_dev *dev, void *arg);
1711 struct mlx5_flow_meter_info *mlx5_flow_meter_find(struct mlx5_priv *priv,
1712 uint32_t meter_id, uint32_t *mtr_idx);
1713 struct mlx5_flow_meter_info *
1714 flow_dv_meter_find_by_idx(struct mlx5_priv *priv, uint32_t idx);
1715 int mlx5_flow_meter_attach(struct mlx5_priv *priv,
1716 struct mlx5_flow_meter_info *fm,
1717 const struct rte_flow_attr *attr,
1718 struct rte_flow_error *error);
1719 void mlx5_flow_meter_detach(struct mlx5_priv *priv,
1720 struct mlx5_flow_meter_info *fm);
1721 struct mlx5_flow_meter_policy *mlx5_flow_meter_policy_find
1722 (struct rte_eth_dev *dev,
1724 uint32_t *policy_idx);
1725 struct mlx5_flow_meter_policy *
1726 mlx5_flow_meter_hierarchy_get_final_policy(struct rte_eth_dev *dev,
1727 struct mlx5_flow_meter_policy *policy);
1728 int mlx5_flow_meter_flush(struct rte_eth_dev *dev,
1729 struct rte_mtr_error *error);
1730 void mlx5_flow_meter_rxq_flush(struct rte_eth_dev *dev);
1733 struct rte_pci_driver;
1734 int mlx5_os_get_dev_attr(struct mlx5_common_device *dev,
1735 struct mlx5_dev_attr *dev_attr);
1736 void mlx5_os_free_shared_dr(struct mlx5_priv *priv);
1737 int mlx5_os_net_probe(struct mlx5_common_device *cdev);
1738 void mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh);
1739 void mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh);
1740 void mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
1741 int mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
1743 int mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv, unsigned int iface_idx,
1744 struct rte_ether_addr *mac_addr,
1746 int mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable);
1747 int mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable);
1748 int mlx5_os_set_nonblock_channel_fd(int fd);
1749 void mlx5_os_mac_addr_flush(struct rte_eth_dev *dev);
1753 int mlx5_txpp_start(struct rte_eth_dev *dev);
1754 void mlx5_txpp_stop(struct rte_eth_dev *dev);
1755 int mlx5_txpp_read_clock(struct rte_eth_dev *dev, uint64_t *timestamp);
1756 int mlx5_txpp_xstats_get(struct rte_eth_dev *dev,
1757 struct rte_eth_xstat *stats,
1758 unsigned int n, unsigned int n_used);
1759 int mlx5_txpp_xstats_reset(struct rte_eth_dev *dev);
1760 int mlx5_txpp_xstats_get_names(struct rte_eth_dev *dev,
1761 struct rte_eth_xstat_name *xstats_names,
1762 unsigned int n, unsigned int n_used);
1763 void mlx5_txpp_interrupt_handler(void *cb_arg);
1767 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev);
1769 /* mlx5_flow_aso.c */
1771 int mlx5_aso_queue_init(struct mlx5_dev_ctx_shared *sh,
1772 enum mlx5_access_aso_opc_mod aso_opc_mod);
1773 int mlx5_aso_flow_hit_queue_poll_start(struct mlx5_dev_ctx_shared *sh);
1774 int mlx5_aso_flow_hit_queue_poll_stop(struct mlx5_dev_ctx_shared *sh);
1775 void mlx5_aso_queue_uninit(struct mlx5_dev_ctx_shared *sh,
1776 enum mlx5_access_aso_opc_mod aso_opc_mod);
1777 int mlx5_aso_meter_update_by_wqe(struct mlx5_dev_ctx_shared *sh,
1778 struct mlx5_aso_mtr *mtr);
1779 int mlx5_aso_mtr_wait(struct mlx5_dev_ctx_shared *sh,
1780 struct mlx5_aso_mtr *mtr);
1781 int mlx5_aso_ct_update_by_wqe(struct mlx5_dev_ctx_shared *sh,
1782 struct mlx5_aso_ct_action *ct,
1783 const struct rte_flow_action_conntrack *profile);
1784 int mlx5_aso_ct_wait_ready(struct mlx5_dev_ctx_shared *sh,
1785 struct mlx5_aso_ct_action *ct);
1786 int mlx5_aso_ct_query_by_wqe(struct mlx5_dev_ctx_shared *sh,
1787 struct mlx5_aso_ct_action *ct,
1788 struct rte_flow_action_conntrack *profile);
1789 int mlx5_aso_ct_available(struct mlx5_dev_ctx_shared *sh,
1790 struct mlx5_aso_ct_action *ct);
1792 mlx5_get_supported_sw_parsing_offloads(const struct mlx5_hca_attr *attr);
1794 mlx5_get_supported_tunneling_offloads(const struct mlx5_hca_attr *attr);
1796 #endif /* RTE_PMD_MLX5_H_ */