1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_H_
7 #define RTE_PMD_MLX5_H_
13 #include <sys/queue.h>
16 #include <rte_ether.h>
17 #include <ethdev_driver.h>
18 #include <rte_rwlock.h>
19 #include <rte_interrupts.h>
20 #include <rte_errno.h>
24 #include <mlx5_glue.h>
25 #include <mlx5_devx_cmds.h>
27 #include <mlx5_common_mp.h>
28 #include <mlx5_common_mr.h>
29 #include <mlx5_common_devx.h>
31 #include "mlx5_defs.h"
32 #include "mlx5_utils.h"
34 #include "mlx5_autoconf.h"
37 #define MLX5_SH(dev) (((struct mlx5_priv *)(dev)->data->dev_private)->sh)
39 enum mlx5_ipool_index {
40 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
41 MLX5_IPOOL_DECAP_ENCAP = 0, /* Pool for encap/decap resource. */
42 MLX5_IPOOL_PUSH_VLAN, /* Pool for push vlan resource. */
43 MLX5_IPOOL_TAG, /* Pool for tag resource. */
44 MLX5_IPOOL_PORT_ID, /* Pool for port id resource. */
45 MLX5_IPOOL_JUMP, /* Pool for jump resource. */
46 MLX5_IPOOL_SAMPLE, /* Pool for sample resource. */
47 MLX5_IPOOL_DEST_ARRAY, /* Pool for destination array resource. */
48 MLX5_IPOOL_TUNNEL_ID, /* Pool for tunnel offload context */
49 MLX5_IPOOL_TNL_TBL_ID, /* Pool for tunnel table ID. */
51 MLX5_IPOOL_MTR, /* Pool for meter resource. */
52 MLX5_IPOOL_MCP, /* Pool for metadata resource. */
53 MLX5_IPOOL_HRXQ, /* Pool for hrxq resource. */
54 MLX5_IPOOL_MLX5_FLOW, /* Pool for mlx5 flow handle. */
55 MLX5_IPOOL_RTE_FLOW, /* Pool for rte_flow. */
56 MLX5_IPOOL_RSS_EXPANTION_FLOW_ID, /* Pool for Queue/RSS flow ID. */
57 MLX5_IPOOL_RSS_SHARED_ACTIONS, /* Pool for RSS shared actions. */
58 MLX5_IPOOL_MTR_POLICY, /* Pool for meter policy resource. */
63 * There are three reclaim memory mode supported.
64 * 0(none) means no memory reclaim.
65 * 1(light) means only PMD level reclaim.
66 * 2(aggressive) means both PMD and rdma-core level reclaim.
68 enum mlx5_reclaim_mem_mode {
69 MLX5_RCM_NONE, /* Don't reclaim memory. */
70 MLX5_RCM_LIGHT, /* Reclaim PMD level. */
71 MLX5_RCM_AGGR, /* Reclaim PMD and rdma-core level. */
74 /* Hash and cache list callback context. */
75 struct mlx5_flow_cb_ctx {
76 struct rte_eth_dev *dev;
77 struct rte_flow_error *error;
81 /* Device attributes used in mlx5 PMD */
82 struct mlx5_dev_attr {
83 uint64_t device_cap_flags_ex;
93 uint32_t raw_packet_caps;
94 uint32_t max_rwq_indirection_table_size;
96 uint32_t tso_supported_qpts;
99 uint32_t sw_parsing_offloads;
100 uint32_t min_single_stride_log_num_of_bytes;
101 uint32_t max_single_stride_log_num_of_bytes;
102 uint32_t min_single_wqe_log_num_of_strides;
103 uint32_t max_single_wqe_log_num_of_strides;
104 uint32_t stride_supported_qpts;
105 uint32_t tunnel_offloads_caps;
109 /** Data associated with devices to spawn. */
110 struct mlx5_dev_spawn_data {
111 uint32_t ifindex; /**< Network interface index. */
112 uint32_t max_port; /**< Device maximal port index. */
113 uint32_t phys_port; /**< Device physical port index. */
114 int pf_bond; /**< bonding device PF index. < 0 - no bonding */
115 struct mlx5_switch_info info; /**< Switch information. */
116 void *phys_dev; /**< Associated physical device. */
117 struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */
118 struct rte_pci_device *pci_dev; /**< Backend PCI device. */
119 struct mlx5_bond_info *bond_info;
122 /** Data associated with socket messages. */
123 struct mlx5_flow_dump_req {
124 uint32_t port_id; /**< There are plans in DPDK to extend port_id. */
128 struct mlx5_flow_dump_ack {
129 int rc; /**< Return code. */
132 /** Key string for IPC. */
133 #define MLX5_MP_NAME "net_mlx5_mp"
136 LIST_HEAD(mlx5_dev_list, mlx5_dev_ctx_shared);
138 /* Shared data between primary and secondary processes. */
139 struct mlx5_shared_data {
141 /* Global spinlock for primary and secondary processes. */
142 int init_done; /* Whether primary has done initialization. */
143 unsigned int secondary_cnt; /* Number of secondary processes init'd. */
144 struct mlx5_dev_list mem_event_cb_list;
145 rte_rwlock_t mem_event_rwlock;
148 /* Per-process data structure, not visible to other processes. */
149 struct mlx5_local_data {
150 int init_done; /* Whether a secondary has done initialization. */
153 extern struct mlx5_shared_data *mlx5_shared_data;
155 /* Dev ops structs */
156 extern const struct eth_dev_ops mlx5_dev_ops;
157 extern const struct eth_dev_ops mlx5_dev_sec_ops;
158 extern const struct eth_dev_ops mlx5_dev_ops_isolate;
160 struct mlx5_counter_ctrl {
161 /* Name of the counter. */
162 char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE];
163 /* Name of the counter on the device table. */
164 char ctr_name[RTE_ETH_XSTATS_NAME_SIZE];
165 uint32_t dev:1; /**< Nonzero for dev counters. */
168 struct mlx5_xstats_ctrl {
169 /* Number of device stats. */
171 /* Number of device stats identified by PMD. */
172 uint16_t mlx5_stats_n;
173 /* Index in the device counters table. */
174 uint16_t dev_table_idx[MLX5_MAX_XSTATS];
175 uint64_t base[MLX5_MAX_XSTATS];
176 uint64_t xstats[MLX5_MAX_XSTATS];
177 uint64_t hw_stats[MLX5_MAX_XSTATS];
178 struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS];
181 struct mlx5_stats_ctrl {
182 /* Base for imissed counter. */
183 uint64_t imissed_base;
187 /* Default PMD specific parameter value. */
188 #define MLX5_ARG_UNSET (-1)
190 #define MLX5_LRO_SUPPORTED(dev) \
191 (((struct mlx5_priv *)((dev)->data->dev_private))->config.lro.supported)
193 /* Maximal size of coalesced segment for LRO is set in chunks of 256 Bytes. */
194 #define MLX5_LRO_SEG_CHUNK_SIZE 256u
196 /* Maximal size of aggregated LRO packet. */
197 #define MLX5_MAX_LRO_SIZE (UINT8_MAX * MLX5_LRO_SEG_CHUNK_SIZE)
199 /* Maximal number of segments to split. */
200 #define MLX5_MAX_RXQ_NSEG (1u << MLX5_MAX_LOG_RQ_SEGS)
202 /* LRO configurations structure. */
203 struct mlx5_lro_config {
204 uint32_t supported:1; /* Whether LRO is supported. */
205 uint32_t timeout; /* User configuration. */
209 * Device configuration structure.
211 * Merged configuration from:
213 * - Device capabilities,
214 * - User device parameters disabled features.
216 struct mlx5_dev_config {
217 unsigned int hw_csum:1; /* Checksum offload is supported. */
218 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */
219 unsigned int hw_vlan_insert:1; /* VLAN insertion in WQE is supported. */
220 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */
221 unsigned int hw_padding:1; /* End alignment padding is supported. */
222 unsigned int vf:1; /* This is a VF. */
223 unsigned int tunnel_en:1;
224 /* Whether tunnel stateless offloads are supported. */
225 unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */
226 unsigned int cqe_comp:1; /* CQE compression is enabled. */
227 unsigned int cqe_comp_fmt:3; /* CQE compression format. */
228 unsigned int tso:1; /* Whether TSO is supported. */
229 unsigned int rx_vec_en:1; /* Rx vector is enabled. */
230 unsigned int mr_ext_memseg_en:1;
231 /* Whether memseg should be extended for MR creation. */
232 unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */
233 unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */
234 unsigned int dv_esw_en:1; /* Enable E-Switch DV flow. */
235 unsigned int dv_flow_en:1; /* Enable DV flow. */
236 unsigned int dv_xmeta_en:2; /* Enable extensive flow metadata. */
237 unsigned int lacp_by_user:1;
238 /* Enable user to manage LACP traffic. */
239 unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */
240 unsigned int devx:1; /* Whether devx interface is available or not. */
241 unsigned int dest_tir:1; /* Whether advanced DR API is available. */
242 unsigned int reclaim_mode:2; /* Memory reclaim mode. */
243 unsigned int rt_timestamp:1; /* realtime timestamp format. */
244 unsigned int sys_mem_en:1; /* The default memory allocator. */
245 unsigned int decap_en:1; /* Whether decap will be used or not. */
246 unsigned int dv_miss_info:1; /* restore packet after partial hw miss */
248 unsigned int enabled:1; /* Whether MPRQ is enabled. */
249 unsigned int stride_num_n; /* Number of strides. */
250 unsigned int stride_size_n; /* Size of a stride. */
251 unsigned int min_stride_size_n; /* Min size of a stride. */
252 unsigned int max_stride_size_n; /* Max size of a stride. */
253 unsigned int max_memcpy_len;
254 /* Maximum packet size to memcpy Rx packets. */
255 unsigned int min_rxqs_num;
256 /* Rx queue count threshold to enable MPRQ. */
257 } mprq; /* Configurations for Multi-Packet RQ. */
258 int mps; /* Multi-packet send supported mode. */
259 int dbnc; /* Skip doorbell register write barrier. */
260 unsigned int flow_prio; /* Number of flow priorities. */
261 enum modify_reg flow_mreg_c[MLX5_MREG_C_NUM];
262 /* Availibility of mreg_c's. */
263 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */
264 unsigned int ind_table_max_size; /* Maximum indirection table size. */
265 unsigned int max_dump_files_num; /* Maximum dump files per queue. */
266 unsigned int log_hp_size; /* Single hairpin queue data size in total. */
267 int txqs_inline; /* Queue number threshold for inlining. */
268 int txq_inline_min; /* Minimal amount of data bytes to inline. */
269 int txq_inline_max; /* Max packet size for inlining with SEND. */
270 int txq_inline_mpw; /* Max packet size for inlining with eMPW. */
271 int tx_pp; /* Timestamp scheduling granularity in nanoseconds. */
272 int tx_skew; /* Tx scheduling skew between WQE and data on wire. */
273 struct mlx5_hca_attr hca_attr; /* HCA attributes. */
274 struct mlx5_lro_config lro; /* LRO configuration. */
278 /* Structure for VF VLAN workaround. */
279 struct mlx5_vf_vlan {
284 /* Flow drop context necessary due to Verbs API. */
286 struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */
287 struct mlx5_rxq_obj *rxq; /* Rx queue object. */
290 #define MLX5_COUNTERS_PER_POOL 512
291 #define MLX5_MAX_PENDING_QUERIES 4
292 #define MLX5_CNT_CONTAINER_RESIZE 64
293 #define MLX5_CNT_SHARED_OFFSET 0x80000000
294 #define IS_LEGACY_SHARED_CNT(cnt) (!!((cnt) & MLX5_CNT_SHARED_OFFSET))
295 #define IS_BATCH_CNT(cnt) (((cnt) & (MLX5_CNT_SHARED_OFFSET - 1)) >= \
296 MLX5_CNT_BATCH_OFFSET)
297 #define MLX5_CNT_SIZE (sizeof(struct mlx5_flow_counter))
298 #define MLX5_AGE_SIZE (sizeof(struct mlx5_age_param))
300 #define MLX5_CNT_LEN(pool) \
302 ((pool)->is_aged ? MLX5_AGE_SIZE : 0))
303 #define MLX5_POOL_GET_CNT(pool, index) \
304 ((struct mlx5_flow_counter *) \
305 ((uint8_t *)((pool) + 1) + (index) * (MLX5_CNT_LEN(pool))))
306 #define MLX5_CNT_ARRAY_IDX(pool, cnt) \
307 ((int)(((uint8_t *)(cnt) - (uint8_t *)((pool) + 1)) / \
310 * The pool index and offset of counter in the pool array makes up the
311 * counter index. In case the counter is from pool 0 and offset 0, it
312 * should plus 1 to avoid index 0, since 0 means invalid counter index
315 #define MLX5_MAKE_CNT_IDX(pi, offset) \
316 ((pi) * MLX5_COUNTERS_PER_POOL + (offset) + 1)
317 #define MLX5_CNT_TO_AGE(cnt) \
318 ((struct mlx5_age_param *)((cnt) + 1))
320 * The maximum single counter is 0x800000 as MLX5_CNT_BATCH_OFFSET
321 * defines. The pool size is 512, pool index should never reach
324 #define POOL_IDX_INVALID UINT16_MAX
328 AGE_FREE, /* Initialized state. */
329 AGE_CANDIDATE, /* Counter assigned to flows. */
330 AGE_TMOUT, /* Timeout, wait for rte_flow_get_aged_flows and destroy. */
333 enum mlx5_counter_type {
334 MLX5_COUNTER_TYPE_ORIGIN,
335 MLX5_COUNTER_TYPE_AGE,
336 MLX5_COUNTER_TYPE_MAX,
339 /* Counter age parameter. */
340 struct mlx5_age_param {
341 uint16_t state; /**< Age state (atomically accessed). */
342 uint16_t port_id; /**< Port id of the counter. */
343 uint32_t timeout:24; /**< Aging timeout in seconds. */
344 uint32_t sec_since_last_hit;
345 /**< Time in seconds since last hit (atomically accessed). */
346 void *context; /**< Flow counter age context. */
349 struct flow_counter_stats {
354 /* Shared counters information for counters. */
355 struct mlx5_flow_counter_shared {
357 uint32_t refcnt; /* Only for shared action management. */
358 uint32_t id; /* User counter ID for legacy sharing. */
362 /* Shared counter configuration. */
363 struct mlx5_shared_counter_conf {
364 struct rte_eth_dev *dev; /* The device shared counter belongs to. */
365 uint32_t id; /* The shared counter ID. */
368 struct mlx5_flow_counter_pool;
369 /* Generic counters information. */
370 struct mlx5_flow_counter {
373 * User-defined counter shared info is only used during
374 * counter active time. And aging counter sharing is not
375 * supported, so active shared counter will not be chained
376 * to the aging list. For shared counter, only when it is
377 * released, the TAILQ entry memory will be used, at that
378 * time, shared memory is not used anymore.
380 * Similarly to none-batch counter dcs, since it doesn't
381 * support aging, while counter is allocated, the entry
382 * memory is not used anymore. In this case, as bytes
383 * memory is used only when counter is allocated, and
384 * entry memory is used only when counter is free. The
385 * dcs pointer can be saved to these two different place
386 * at different stage. It will eliminate the individual
387 * counter extend struct.
389 TAILQ_ENTRY(mlx5_flow_counter) next;
390 /**< Pointer to the next flow counter structure. */
392 struct mlx5_flow_counter_shared shared_info;
393 /**< Shared counter information. */
394 void *dcs_when_active;
396 * For non-batch mode, the dcs will be saved
397 * here when the counter is free.
402 uint64_t hits; /**< Reset value of hits packets. */
403 struct mlx5_flow_counter_pool *pool; /**< Counter pool. */
406 uint64_t bytes; /**< Reset value of bytes. */
409 * For non-batch mode, the dcs will be saved here
410 * when the counter is free.
413 void *action; /**< Pointer to the dv action. */
416 TAILQ_HEAD(mlx5_counters, mlx5_flow_counter);
418 /* Generic counter pool structure - query is in pool resolution. */
419 struct mlx5_flow_counter_pool {
420 TAILQ_ENTRY(mlx5_flow_counter_pool) next;
421 struct mlx5_counters counters[2]; /* Free counter list. */
422 struct mlx5_devx_obj *min_dcs;
423 /* The devx object of the minimum counter ID. */
424 uint64_t time_of_last_age_check;
425 /* System time (from rte_rdtsc()) read in the last aging check. */
426 uint32_t index:30; /* Pool index in container. */
427 uint32_t is_aged:1; /* Pool with aging counter. */
428 volatile uint32_t query_gen:1; /* Query round. */
429 rte_spinlock_t sl; /* The pool lock. */
430 rte_spinlock_t csl; /* The pool counter free list lock. */
431 struct mlx5_counter_stats_raw *raw;
432 struct mlx5_counter_stats_raw *raw_hw;
433 /* The raw on HW working. */
436 /* Memory management structure for group of counter statistics raws. */
437 struct mlx5_counter_stats_mem_mng {
438 LIST_ENTRY(mlx5_counter_stats_mem_mng) next;
439 struct mlx5_counter_stats_raw *raws;
440 struct mlx5_devx_obj *dm;
444 /* Raw memory structure for the counter statistics values of a pool. */
445 struct mlx5_counter_stats_raw {
446 LIST_ENTRY(mlx5_counter_stats_raw) next;
447 struct mlx5_counter_stats_mem_mng *mem_mng;
448 volatile struct flow_counter_stats *data;
451 TAILQ_HEAD(mlx5_counter_pools, mlx5_flow_counter_pool);
453 /* Counter global management structure. */
454 struct mlx5_flow_counter_mng {
455 volatile uint16_t n_valid; /* Number of valid pools. */
456 uint16_t n; /* Number of pools. */
457 uint16_t last_pool_idx; /* Last used pool index */
458 int min_id; /* The minimum counter ID in the pools. */
459 int max_id; /* The maximum counter ID in the pools. */
460 rte_spinlock_t pool_update_sl; /* The pool update lock. */
461 rte_spinlock_t csl[MLX5_COUNTER_TYPE_MAX];
462 /* The counter free list lock. */
463 struct mlx5_counters counters[MLX5_COUNTER_TYPE_MAX];
464 /* Free counter list. */
465 struct mlx5_flow_counter_pool **pools; /* Counter pool array. */
466 struct mlx5_counter_stats_mem_mng *mem_mng;
467 /* Hold the memory management for the next allocated pools raws. */
468 struct mlx5_counters flow_counters; /* Legacy flow counter list. */
469 uint8_t pending_queries;
471 uint8_t query_thread_on;
472 bool relaxed_ordering_read;
473 bool relaxed_ordering_write;
474 bool counter_fallback; /* Use counter fallback management. */
475 LIST_HEAD(mem_mngs, mlx5_counter_stats_mem_mng) mem_mngs;
476 LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws;
479 /* ASO structures. */
480 #define MLX5_ASO_QUEUE_LOG_DESC 10
485 struct mlx5_devx_cq cq_obj;
489 struct mlx5_aso_sq_elem {
492 struct mlx5_aso_age_pool *pool;
495 struct mlx5_aso_mtr *mtr;
497 struct mlx5_aso_ct_action *ct;
506 struct mlx5_aso_cq cq;
507 struct mlx5_devx_sq sq_obj;
508 volatile uint64_t *uar_addr;
509 struct mlx5_pmd_mr mr;
514 struct mlx5_aso_sq_elem elts[1 << MLX5_ASO_QUEUE_LOG_DESC];
515 uint16_t next; /* Pool index of the next pool to query. */
518 struct mlx5_aso_age_action {
519 LIST_ENTRY(mlx5_aso_age_action) next;
522 /* Following fields relevant only when action is active. */
523 uint16_t offset; /* Offset of ASO Flow Hit flag in DevX object. */
524 struct mlx5_age_param age_params;
527 #define MLX5_ASO_AGE_ACTIONS_PER_POOL 512
529 struct mlx5_aso_age_pool {
530 struct mlx5_devx_obj *flow_hit_aso_obj;
531 uint16_t index; /* Pool index in pools array. */
532 uint64_t time_of_last_age_check; /* In seconds. */
533 struct mlx5_aso_age_action actions[MLX5_ASO_AGE_ACTIONS_PER_POOL];
536 LIST_HEAD(aso_age_list, mlx5_aso_age_action);
538 struct mlx5_aso_age_mng {
539 struct mlx5_aso_age_pool **pools;
540 uint16_t n; /* Total number of pools. */
541 uint16_t next; /* Number of pools in use, index of next free pool. */
542 rte_spinlock_t resize_sl; /* Lock for resize objects. */
543 rte_spinlock_t free_sl; /* Lock for free list access. */
544 struct aso_age_list free; /* Free age actions list - ready to use. */
545 struct mlx5_aso_sq aso_sq; /* ASO queue objects. */
548 /* Management structure for geneve tlv option */
549 struct mlx5_geneve_tlv_option_resource {
550 struct mlx5_devx_obj *obj; /* Pointer to the geneve tlv opt object. */
551 rte_be16_t option_class; /* geneve tlv opt class.*/
552 uint8_t option_type; /* geneve tlv opt type.*/
553 uint8_t length; /* geneve tlv opt length. */
554 uint32_t refcnt; /* geneve tlv object reference counter */
558 #define MLX5_AGE_EVENT_NEW 1
559 #define MLX5_AGE_TRIGGER 2
560 #define MLX5_AGE_SET(age_info, BIT) \
561 ((age_info)->flags |= (1 << (BIT)))
562 #define MLX5_AGE_UNSET(age_info, BIT) \
563 ((age_info)->flags &= ~(1 << (BIT)))
564 #define MLX5_AGE_GET(age_info, BIT) \
565 ((age_info)->flags & (1 << (BIT)))
566 #define GET_PORT_AGE_INFO(priv) \
567 (&((priv)->sh->port[(priv)->dev_port - 1].age_info))
568 /* Current time in seconds. */
569 #define MLX5_CURR_TIME_SEC (rte_rdtsc() / rte_get_tsc_hz())
571 /* Aging information for per port. */
572 struct mlx5_age_info {
573 uint8_t flags; /* Indicate if is new event or need to be triggered. */
574 struct mlx5_counters aged_counters; /* Aged counter list. */
575 struct aso_age_list aged_aso; /* Aged ASO actions list. */
576 rte_spinlock_t aged_sl; /* Aged flow list lock. */
579 /* Per port data of shared IB device. */
580 struct mlx5_dev_shared_port {
582 uint32_t devx_ih_port_id;
584 * Interrupt handler port_id. Used by shared interrupt
585 * handler to find the corresponding rte_eth device
586 * by IB port index. If value is equal or greater
587 * RTE_MAX_ETHPORTS it means there is no subhandler
588 * installed for specified IB port index.
590 struct mlx5_age_info age_info;
591 /* Aging information for per port. */
595 * Max number of actions per DV flow.
596 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED
597 * in rdma-core file providers/mlx5/verbs.c.
599 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8
601 /*ASO flow meter structures*/
602 /* Modify this value if enum rte_mtr_color changes. */
603 #define RTE_MTR_DROPPED RTE_COLORS
604 /* Yellow is not supported. */
605 #define MLX5_MTR_RTE_COLORS (RTE_COLOR_GREEN + 1)
606 /* table_id 22 bits in mlx5_flow_tbl_key so limit policy number. */
607 #define MLX5_MAX_SUB_POLICY_TBL_NUM 0x3FFFFF
608 #define MLX5_INVALID_POLICY_ID UINT32_MAX
609 /* Suffix table_id on MLX5_FLOW_TABLE_LEVEL_METER. */
610 #define MLX5_MTR_TABLE_ID_SUFFIX 1
611 /* Drop table_id on MLX5_FLOW_TABLE_LEVEL_METER. */
612 #define MLX5_MTR_TABLE_ID_DROP 2
614 enum mlx5_meter_domain {
615 MLX5_MTR_DOMAIN_INGRESS,
616 MLX5_MTR_DOMAIN_EGRESS,
617 MLX5_MTR_DOMAIN_TRANSFER,
620 #define MLX5_MTR_DOMAIN_INGRESS_BIT (1 << MLX5_MTR_DOMAIN_INGRESS)
621 #define MLX5_MTR_DOMAIN_EGRESS_BIT (1 << MLX5_MTR_DOMAIN_EGRESS)
622 #define MLX5_MTR_DOMAIN_TRANSFER_BIT (1 << MLX5_MTR_DOMAIN_TRANSFER)
623 #define MLX5_MTR_ALL_DOMAIN_BIT (MLX5_MTR_DOMAIN_INGRESS_BIT | \
624 MLX5_MTR_DOMAIN_EGRESS_BIT | \
625 MLX5_MTR_DOMAIN_TRANSFER_BIT)
628 * Meter sub-policy structure.
629 * Each RSS TIR in meter policy need its own sub-policy resource.
631 struct mlx5_flow_meter_sub_policy {
632 uint32_t main_policy_id:1;
633 /* Main policy id is same as this sub_policy id. */
635 /* Index to sub_policy ipool entity. */
637 /* Point to struct mlx5_flow_meter_policy. */
638 struct mlx5_flow_tbl_resource *tbl_rsc;
639 /* The sub-policy table resource. */
640 uint32_t rix_hrxq[MLX5_MTR_RTE_COLORS];
641 /* Index to TIR resource. */
642 struct mlx5_flow_tbl_resource *jump_tbl[MLX5_MTR_RTE_COLORS];
643 /* Meter jump/drop table. */
644 struct mlx5_flow_dv_matcher *color_matcher[RTE_COLORS];
645 /* Matcher for Color. */
646 void *color_rule[RTE_COLORS];
647 /* Meter green/yellow/drop rule. */
650 struct mlx5_meter_policy_acts {
652 /* Number of actions. */
653 void *dv_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS];
657 struct mlx5_meter_policy_action_container {
659 /* Index to the mark action. */
660 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
661 /* Pointer to modify header resource in cache. */
663 /* Fate action type. */
665 struct rte_flow_action *rss;
666 /* Rss action configuration. */
667 uint32_t rix_port_id_action;
668 /* Index to port ID action resource. */
669 void *dr_jump_action[MLX5_MTR_DOMAIN_MAX];
670 /* Jump/drop action per color. */
674 /* Flow meter policy parameter structure. */
675 struct mlx5_flow_meter_policy {
677 /* Is RSS policy table. */
679 /* Rule applies to ingress domain. */
681 /* Rule applies to egress domain. */
683 /* Rule applies to transfer domain. */
687 struct mlx5_meter_policy_action_container act_cnt[MLX5_MTR_RTE_COLORS];
688 /* Policy actions container. */
689 void *dr_drop_action[MLX5_MTR_DOMAIN_MAX];
690 /* drop action for red color. */
691 uint16_t sub_policy_num;
692 /* Count sub policy tables, 3 bits per domain. */
693 struct mlx5_flow_meter_sub_policy **sub_policys[MLX5_MTR_DOMAIN_MAX];
694 /* Sub policy table array must be the end of struct. */
697 /* The maximum sub policy is relate to struct mlx5_rss_hash_fields[]. */
698 #define MLX5_MTR_RSS_MAX_SUB_POLICY 7
699 #define MLX5_MTR_SUB_POLICY_NUM_SHIFT 3
700 #define MLX5_MTR_SUB_POLICY_NUM_MASK 0x7
701 #define MLX5_MTRS_DEFAULT_RULE_PRIORITY 0xFFFF
703 /* Flow meter default policy parameter structure.
704 * Policy index 0 is reserved by default policy table.
705 * Action per color as below:
706 * green - do nothing, yellow - do nothing, red - drop
708 struct mlx5_flow_meter_def_policy {
709 struct mlx5_flow_meter_sub_policy sub_policy;
710 /* Policy rules jump to other tables. */
711 void *dr_jump_action[RTE_COLORS];
712 /* Jump action per color. */
715 /* Meter parameter structure. */
716 struct mlx5_flow_meter_info {
720 /* Policy id, the first sub_policy idx. */
721 struct mlx5_flow_meter_profile *profile;
722 /**< Meter profile parameters. */
723 rte_spinlock_t sl; /**< Meter action spinlock. */
724 /** Set of stats counters to be enabled.
725 * @see enum rte_mtr_stats_type
727 uint32_t bytes_dropped:1;
728 /** Set bytes dropped stats to be enabled. */
729 uint32_t pkts_dropped:1;
730 /** Set packets dropped stats to be enabled. */
731 uint32_t active_state:1;
732 /**< Meter hw active state. */
734 /**< Meter shared or not. */
735 uint32_t is_enable:1;
736 /**< Meter disable/enable state. */
738 /**< Rule applies to egress traffic. */
741 * Instead of simply matching the properties of traffic as it would
742 * appear on a given DPDK port ID, enabling this attribute transfers
743 * a flow rule to the lowest possible level of any device endpoints
744 * found in the pattern.
746 * When supported, this effectively enables an application to
747 * re-route traffic not necessarily intended for it (e.g. coming
748 * from or addressed to different physical ports, VFs or
749 * applications) at the device level.
751 * It complements the behavior of some pattern items such as
752 * RTE_FLOW_ITEM_TYPE_PHY_PORT and is meaningless without them.
754 * When transferring flow rules, ingress and egress attributes keep
755 * their original meaning, as if processing traffic emitted or
756 * received by the application.
759 uint32_t def_policy:1;
760 /* Meter points to default policy. */
761 void *drop_rule[MLX5_MTR_DOMAIN_MAX];
762 /* Meter drop rule in drop table. */
764 /**< Color counter for drop. */
767 struct mlx5_indexed_pool *flow_ipool;
768 /**< Index pool for flow id. */
770 /**< Flow meter action. */
773 /* PPS(packets per second) map to BPS(Bytes per second).
774 * HW treat packet as 128bytes in PPS mode
776 #define MLX5_MTRS_PPS_MAP_BPS_SHIFT 7
778 /* RFC2697 parameter structure. */
779 struct mlx5_flow_meter_srtcm_rfc2697_prm {
782 * bit 24-28: cbs_exponent, bit 16-23 cbs_mantissa,
783 * bit 8-12: cir_exponent, bit 0-7 cir_mantissa.
787 * bit 24-28: ebs_exponent, bit 16-23 ebs_mantissa,
788 * bit 8-12: eir_exponent, bit 0-7 eir_mantissa.
792 /* Flow meter profile structure. */
793 struct mlx5_flow_meter_profile {
794 TAILQ_ENTRY(mlx5_flow_meter_profile) next;
795 /**< Pointer to the next flow meter structure. */
796 uint32_t id; /**< Profile id. */
797 struct rte_mtr_meter_profile profile; /**< Profile detail. */
799 struct mlx5_flow_meter_srtcm_rfc2697_prm srtcm_prm;
800 /**< srtcm_rfc2697 struct. */
802 uint32_t ref_cnt; /**< Use count. */
805 /* 2 meters in each ASO cache line */
806 #define MLX5_MTRS_CONTAINER_RESIZE 64
808 * The pool index and offset of meter in the pool array makes up the
809 * meter index. In case the meter is from pool 0 and offset 0, it
810 * should plus 1 to avoid index 0, since 0 means invalid meter index
813 #define MLX5_MAKE_MTR_IDX(pi, offset) \
814 ((pi) * MLX5_ASO_MTRS_PER_POOL + (offset) + 1)
816 /*aso flow meter state*/
817 enum mlx5_aso_mtr_state {
818 ASO_METER_FREE, /* In free list. */
819 ASO_METER_WAIT, /* ACCESS_ASO WQE in progress. */
820 ASO_METER_READY, /* CQE received. */
823 /* Generic aso_flow_meter information. */
824 struct mlx5_aso_mtr {
825 LIST_ENTRY(mlx5_aso_mtr) next;
826 struct mlx5_flow_meter_info fm;
827 /**< Pointer to the next aso flow meter structure. */
828 uint8_t state; /**< ASO flow meter state. */
832 /* Generic aso_flow_meter pool structure. */
833 struct mlx5_aso_mtr_pool {
834 struct mlx5_aso_mtr mtrs[MLX5_ASO_MTRS_PER_POOL];
835 /*Must be the first in pool*/
836 struct mlx5_devx_obj *devx_obj;
837 /* The devx object of the minimum aso flow meter ID. */
838 uint32_t index; /* Pool index in management structure. */
841 LIST_HEAD(aso_meter_list, mlx5_aso_mtr);
842 /* Pools management structure for ASO flow meter pools. */
843 struct mlx5_aso_mtr_pools_mng {
844 volatile uint16_t n_valid; /* Number of valid pools. */
845 uint16_t n; /* Number of pools. */
846 rte_spinlock_t mtrsl; /* The ASO flow meter free list lock. */
847 struct aso_meter_list meters; /* Free ASO flow meter list. */
848 struct mlx5_aso_sq sq; /*SQ using by ASO flow meter. */
849 struct mlx5_aso_mtr_pool **pools; /* ASO flow meter pool array. */
852 /* Meter management structure for global flow meter resource. */
853 struct mlx5_flow_mtr_mng {
854 struct mlx5_aso_mtr_pools_mng pools_mng;
855 /* Pools management structure for ASO flow meter pools. */
856 struct mlx5_flow_meter_def_policy *def_policy[MLX5_MTR_DOMAIN_MAX];
857 /* Default policy table. */
858 uint32_t def_policy_id;
859 /* Default policy id. */
860 uint32_t def_policy_ref_cnt;
861 /** def_policy meter use count. */
862 struct mlx5_l3t_tbl *policy_idx_tbl;
863 /* Policy index lookup table. */
864 struct mlx5_flow_tbl_resource *drop_tbl[MLX5_MTR_DOMAIN_MAX];
865 /* Meter drop table. */
866 struct mlx5_flow_dv_matcher *
867 drop_matcher[MLX5_MTR_DOMAIN_MAX][MLX5_REG_BITS];
868 /* Matcher meter in drop table. */
869 struct mlx5_flow_dv_matcher *def_matcher[MLX5_MTR_DOMAIN_MAX];
870 /* Default matcher in drop table. */
871 void *def_rule[MLX5_MTR_DOMAIN_MAX];
872 /* Default rule in drop table. */
873 uint8_t max_mtr_bits;
874 /* Indicate how many bits are used by meter id at the most. */
875 uint8_t max_mtr_flow_bits;
876 /* Indicate how many bits are used by meter flow id at the most. */
879 /* Table key of the hash organization. */
880 union mlx5_flow_tbl_key {
882 /* Table ID should be at the lowest address. */
883 uint32_t level; /**< Level of the table. */
884 uint32_t id:22; /**< ID of the table. */
885 uint32_t dummy:1; /**< Dummy table for DV API. */
886 uint32_t is_fdb:1; /**< 1 - FDB, 0 - NIC TX/RX. */
887 uint32_t is_egress:1; /**< 1 - egress, 0 - ingress. */
888 uint32_t reserved:7; /**< must be zero for comparison. */
890 uint64_t v64; /**< full 64bits value of key */
893 /* Table structure. */
894 struct mlx5_flow_tbl_resource {
895 void *obj; /**< Pointer to DR table object. */
896 uint32_t refcnt; /**< Reference counter. */
899 #define MLX5_MAX_TABLES UINT16_MAX
900 #define MLX5_HAIRPIN_TX_TABLE (UINT16_MAX - 1)
901 /* Reserve the last two tables for metadata register copy. */
902 #define MLX5_FLOW_MREG_ACT_TABLE_GROUP (MLX5_MAX_TABLES - 1)
903 #define MLX5_FLOW_MREG_CP_TABLE_GROUP (MLX5_MAX_TABLES - 2)
904 /* Tables for metering splits should be added here. */
905 #define MLX5_FLOW_TABLE_LEVEL_METER (MLX5_MAX_TABLES - 3)
906 #define MLX5_FLOW_TABLE_LEVEL_POLICY (MLX5_MAX_TABLES - 4)
907 #define MLX5_MAX_TABLES_EXTERNAL MLX5_FLOW_TABLE_LEVEL_POLICY
908 #define MLX5_MAX_TABLES_FDB UINT16_MAX
909 #define MLX5_FLOW_TABLE_FACTOR 10
911 /* ID generation structure. */
912 struct mlx5_flow_id_pool {
913 uint32_t *free_arr; /**< Pointer to the a array of free values. */
915 /**< The next index that can be used without any free elements. */
916 uint32_t *curr; /**< Pointer to the index to pop. */
917 uint32_t *last; /**< Pointer to the last element in the empty arrray. */
918 uint32_t max_id; /**< Maximum id can be allocated from the pool. */
921 /* Tx pacing queue structure - for Clock and Rearm queues. */
922 struct mlx5_txpp_wq {
923 /* Completion Queue related data.*/
924 struct mlx5_devx_cq cq_obj;
927 /* Send Queue related data.*/
928 struct mlx5_devx_sq sq_obj;
929 uint16_t sq_size; /* Number of WQEs in the queue. */
930 uint16_t sq_ci; /* Next WQE to execute. */
933 /* Tx packet pacing internal timestamp. */
934 struct mlx5_txpp_ts {
939 /* Tx packet pacing structure. */
940 struct mlx5_dev_txpp {
941 pthread_mutex_t mutex; /* Pacing create/destroy mutex. */
942 uint32_t refcnt; /* Pacing reference counter. */
943 uint32_t freq; /* Timestamp frequency, Hz. */
944 uint32_t tick; /* Completion tick duration in nanoseconds. */
945 uint32_t test; /* Packet pacing test mode. */
946 int32_t skew; /* Scheduling skew. */
947 struct rte_intr_handle intr_handle; /* Periodic interrupt. */
948 void *echan; /* Event Channel. */
949 struct mlx5_txpp_wq clock_queue; /* Clock Queue. */
950 struct mlx5_txpp_wq rearm_queue; /* Clock Queue. */
951 void *pp; /* Packet pacing context. */
952 uint16_t pp_id; /* Packet pacing context index. */
953 uint16_t ts_n; /* Number of captured timestamps. */
954 uint16_t ts_p; /* Pointer to statisticks timestamp. */
955 struct mlx5_txpp_ts *tsa; /* Timestamps sliding window stats. */
956 struct mlx5_txpp_ts ts; /* Cached completion id/timestamp. */
957 uint32_t sync_lost:1; /* ci/timestamp synchronization lost. */
958 /* Statistics counters. */
959 uint64_t err_miss_int; /* Missed service interrupt. */
960 uint64_t err_rearm_queue; /* Rearm Queue errors. */
961 uint64_t err_clock_queue; /* Clock Queue errors. */
962 uint64_t err_ts_past; /* Timestamp in the past. */
963 uint64_t err_ts_future; /* Timestamp in the distant future. */
966 /* Supported flex parser profile ID. */
967 enum mlx5_flex_parser_profile_id {
968 MLX5_FLEX_PARSER_ECPRI_0 = 0,
969 MLX5_FLEX_PARSER_MAX = 8,
972 /* Sample ID information of flex parser structure. */
973 struct mlx5_flex_parser_profiles {
974 uint32_t num; /* Actual number of samples. */
975 uint32_t ids[8]; /* Sample IDs for this profile. */
976 uint8_t offset[8]; /* Bytes offset of each parser. */
977 void *obj; /* Flex parser node object. */
980 /* Max member ports per bonding device. */
981 #define MLX5_BOND_MAX_PORTS 2
983 /* Bonding device information. */
984 struct mlx5_bond_info {
985 int n_port; /* Number of bond member ports. */
987 char ifname[MLX5_NAMESIZE + 1];
989 char ifname[MLX5_NAMESIZE + 1];
991 struct rte_pci_addr pci_addr;
992 } ports[MLX5_BOND_MAX_PORTS];
995 /* Number of connection tracking objects per pool: must be a power of 2. */
996 #define MLX5_ASO_CT_ACTIONS_PER_POOL 64
998 /* Generate incremental and unique CT index from pool and offset. */
999 #define MLX5_MAKE_CT_IDX(pool, offset) \
1000 ((pool) * MLX5_ASO_CT_ACTIONS_PER_POOL + (offset) + 1)
1002 /* ASO Conntrack state. */
1003 enum mlx5_aso_ct_state {
1004 ASO_CONNTRACK_FREE, /* Inactive, in the free list. */
1005 ASO_CONNTRACK_WAIT, /* WQE sent in the SQ. */
1006 ASO_CONNTRACK_READY, /* CQE received w/o error. */
1007 ASO_CONNTRACK_QUERY, /* WQE for query sent. */
1008 ASO_CONNTRACK_MAX, /* Guard. */
1011 /* Generic ASO connection tracking structure. */
1012 struct mlx5_aso_ct_action {
1013 LIST_ENTRY(mlx5_aso_ct_action) next; /* Pointer to the next ASO CT. */
1014 void *dr_action_orig; /* General action object for original dir. */
1015 void *dr_action_rply; /* General action object for reply dir. */
1016 uint32_t refcnt; /* Action used count in device flows. */
1017 uint16_t offset; /* Offset of ASO CT in DevX objects bulk. */
1018 uint16_t peer; /* The only peer port index could also use this CT. */
1019 enum mlx5_aso_ct_state state; /* ASO CT state. */
1020 bool is_original; /* The direction of the DR action to be used. */
1023 /* CT action object state update. */
1024 #define MLX5_ASO_CT_UPDATE_STATE(c, s) \
1025 __atomic_store_n(&((c)->state), (s), __ATOMIC_RELAXED)
1027 /* ASO connection tracking software pool definition. */
1028 struct mlx5_aso_ct_pool {
1029 uint16_t index; /* Pool index in pools array. */
1030 struct mlx5_devx_obj *devx_obj;
1031 /* The first devx object in the bulk, used for freeing (not yet). */
1032 struct mlx5_aso_ct_action actions[MLX5_ASO_CT_ACTIONS_PER_POOL];
1033 /* CT action structures bulk. */
1036 LIST_HEAD(aso_ct_list, mlx5_aso_ct_action);
1038 /* Pools management structure for ASO connection tracking pools. */
1039 struct mlx5_aso_ct_pools_mng {
1040 struct mlx5_aso_ct_pool **pools;
1041 uint16_t n; /* Total number of pools. */
1042 uint16_t next; /* Number of pools in use, index of next free pool. */
1043 rte_spinlock_t ct_sl; /* The ASO CT free list lock. */
1044 rte_rwlock_t resize_rwl; /* The ASO CT pool resize lock. */
1045 struct aso_ct_list free_cts; /* Free ASO CT objects list. */
1046 struct mlx5_aso_sq aso_sq; /* ASO queue objects. */
1050 * Shared Infiniband device context for Master/Representors
1051 * which belong to same IB device with multiple IB ports.
1053 struct mlx5_dev_ctx_shared {
1054 LIST_ENTRY(mlx5_dev_ctx_shared) next;
1056 uint32_t devx:1; /* Opened with DV. */
1057 uint32_t flow_hit_aso_en:1; /* Flow Hit ASO is supported. */
1058 uint32_t rq_ts_format:2; /* RQ timestamp formats supported. */
1059 uint32_t sq_ts_format:2; /* SQ timestamp formats supported. */
1060 uint32_t qp_ts_format:2; /* QP timestamp formats supported. */
1061 uint32_t meter_aso_en:1; /* Flow Meter ASO is supported. */
1062 uint32_t ct_aso_en:1; /* Connection Tracking ASO is supported. */
1063 uint32_t max_port; /* Maximal IB device port index. */
1064 struct mlx5_bond_info bond; /* Bonding information. */
1065 void *ctx; /* Verbs/DV/DevX context. */
1066 void *pd; /* Protection Domain. */
1067 uint32_t pdn; /* Protection Domain number. */
1068 uint32_t tdn; /* Transport Domain number. */
1069 char ibdev_name[MLX5_FS_NAME_MAX]; /* SYSFS dev name. */
1070 char ibdev_path[MLX5_FS_PATH_MAX]; /* SYSFS dev path for secondary */
1071 struct mlx5_dev_attr device_attr; /* Device properties. */
1072 int numa_node; /* Numa node of backing physical device. */
1073 LIST_ENTRY(mlx5_dev_ctx_shared) mem_event_cb;
1074 /**< Called by memory event callback. */
1075 struct mlx5_mr_share_cache share_cache;
1076 /* Packet pacing related structure. */
1077 struct mlx5_dev_txpp txpp;
1078 /* Shared DV/DR flow data section. */
1079 uint32_t dv_meta_mask; /* flow META metadata supported mask. */
1080 uint32_t dv_mark_mask; /* flow MARK metadata supported mask. */
1081 uint32_t dv_regc0_mask; /* available bits of metatada reg_c[0]. */
1082 void *fdb_domain; /* FDB Direct Rules name space handle. */
1083 void *rx_domain; /* RX Direct Rules name space handle. */
1084 void *tx_domain; /* TX Direct Rules name space handle. */
1086 rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */
1087 rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX];
1088 /* UAR same-page access control required in 32bit implementations. */
1090 struct mlx5_hlist *flow_tbls;
1091 struct mlx5_flow_tunnel_hub *tunnel_hub;
1092 /* Direct Rules tables for FDB, NIC TX+RX */
1093 void *dr_drop_action; /* Pointer to DR drop action, any domain. */
1094 void *pop_vlan_action; /* Pointer to DR pop VLAN action. */
1095 struct mlx5_hlist *encaps_decaps; /* Encap/decap action hash list. */
1096 struct mlx5_hlist *modify_cmds;
1097 struct mlx5_hlist *tag_table;
1098 struct mlx5_cache_list port_id_action_list; /* Port ID action cache. */
1099 struct mlx5_cache_list push_vlan_action_list; /* Push VLAN actions. */
1100 struct mlx5_cache_list sample_action_list; /* List of sample actions. */
1101 struct mlx5_cache_list dest_array_list;
1102 /* List of destination array actions. */
1103 struct mlx5_flow_counter_mng cmng; /* Counters management structure. */
1104 void *default_miss_action; /* Default miss action. */
1105 struct mlx5_indexed_pool *ipool[MLX5_IPOOL_MAX];
1106 /* Memory Pool for mlx5 flow resources. */
1107 struct mlx5_l3t_tbl *cnt_id_tbl; /* Shared counter lookup table. */
1108 /* Shared interrupt handler section. */
1109 struct rte_intr_handle intr_handle; /* Interrupt handler for device. */
1110 struct rte_intr_handle intr_handle_devx; /* DEVX interrupt handler. */
1111 void *devx_comp; /* DEVX async comp obj. */
1112 struct mlx5_devx_obj *tis; /* TIS object. */
1113 struct mlx5_devx_obj *td; /* Transport domain. */
1114 void *tx_uar; /* Tx/packet pacing shared UAR. */
1115 struct mlx5_flex_parser_profiles fp[MLX5_FLEX_PARSER_MAX];
1116 /* Flex parser profiles information. */
1117 void *devx_rx_uar; /* DevX UAR for Rx. */
1118 struct mlx5_aso_age_mng *aso_age_mng;
1119 /* Management data for aging mechanism using ASO Flow Hit. */
1120 struct mlx5_geneve_tlv_option_resource *geneve_tlv_option_resource;
1121 /* Management structure for geneve tlv option */
1122 rte_spinlock_t geneve_tlv_opt_sl; /* Lock for geneve tlv resource */
1123 struct mlx5_flow_mtr_mng *mtrmng;
1124 /* Meter management structure. */
1125 struct mlx5_aso_ct_pools_mng *ct_mng;
1126 /* Management data for ASO connection tracking. */
1127 struct mlx5_dev_shared_port port[]; /* per device port data array. */
1131 * Per-process private structure.
1132 * Caution, secondary process may rebuild the struct during port start.
1134 struct mlx5_proc_priv {
1135 size_t uar_table_sz;
1136 /* Size of UAR register table. */
1138 /* Table of UAR registers for each process. */
1141 /* MTR profile list. */
1142 TAILQ_HEAD(mlx5_mtr_profiles, mlx5_flow_meter_profile);
1144 TAILQ_HEAD(mlx5_legacy_flow_meters, mlx5_legacy_flow_meter);
1146 /* RSS description. */
1147 struct mlx5_flow_rss_desc {
1149 uint32_t queue_num; /**< Number of entries in @p queue. */
1150 uint64_t types; /**< Specific RSS hash types (see ETH_RSS_*). */
1151 uint64_t hash_fields; /* Verbs Hash fields. */
1152 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
1153 uint32_t key_len; /**< RSS hash key len. */
1154 uint32_t tunnel; /**< Queue in tunnel. */
1155 uint32_t shared_rss; /**< Shared RSS index. */
1156 struct mlx5_ind_table_obj *ind_tbl;
1157 /**< Indirection table for shared RSS hash RX queues. */
1159 uint16_t *queue; /**< Destination queues. */
1160 const uint16_t *const_q; /**< Const pointer convert. */
1164 #define MLX5_PROC_PRIV(port_id) \
1165 ((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private)
1167 /* Verbs/DevX Rx queue elements. */
1168 struct mlx5_rxq_obj {
1169 LIST_ENTRY(mlx5_rxq_obj) next; /* Pointer to the next element. */
1170 struct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */
1171 int fd; /* File descriptor for event channel */
1175 void *wq; /* Work Queue. */
1176 void *ibv_cq; /* Completion Queue. */
1179 struct mlx5_devx_obj *rq; /* DevX RQ object for hairpin. */
1181 struct mlx5_devx_rq rq_obj; /* DevX RQ object. */
1182 struct mlx5_devx_cq cq_obj; /* DevX CQ object. */
1188 /* Indirection table. */
1189 struct mlx5_ind_table_obj {
1190 LIST_ENTRY(mlx5_ind_table_obj) next; /* Pointer to the next element. */
1191 uint32_t refcnt; /* Reference counter. */
1194 void *ind_table; /**< Indirection table. */
1195 struct mlx5_devx_obj *rqt; /* DevX RQT object. */
1197 uint32_t queues_n; /**< Number of queues in the list. */
1198 uint16_t *queues; /**< Queue list. */
1201 /* Hash Rx queue. */
1204 struct mlx5_cache_entry entry; /* Cache entry. */
1205 uint32_t standalone:1; /* This object used in shared action. */
1206 struct mlx5_ind_table_obj *ind_table; /* Indirection table. */
1209 void *qp; /* Verbs queue pair. */
1210 struct mlx5_devx_obj *tir; /* DevX TIR object. */
1212 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
1213 void *action; /* DV QP action pointer. */
1215 uint64_t hash_fields; /* Verbs Hash fields. */
1216 uint32_t rss_key_len; /* Hash key length in bytes. */
1217 uint32_t idx; /* Hash Rx queue index. */
1218 uint8_t rss_key[]; /* Hash key. */
1221 /* Verbs/DevX Tx queue elements. */
1222 struct mlx5_txq_obj {
1223 LIST_ENTRY(mlx5_txq_obj) next; /* Pointer to the next element. */
1224 struct mlx5_txq_ctrl *txq_ctrl; /* Pointer to the control queue. */
1228 void *cq; /* Completion Queue. */
1229 void *qp; /* Queue Pair. */
1232 struct mlx5_devx_obj *sq;
1233 /* DevX object for Sx queue. */
1234 struct mlx5_devx_obj *tis; /* The TIS object. */
1237 struct rte_eth_dev *dev;
1238 struct mlx5_devx_cq cq_obj;
1239 /* DevX CQ object and its resources. */
1240 struct mlx5_devx_sq sq_obj;
1241 /* DevX SQ object and its resources. */
1246 enum mlx5_rxq_modify_type {
1247 MLX5_RXQ_MOD_ERR2RST, /* modify state from error to reset. */
1248 MLX5_RXQ_MOD_RST2RDY, /* modify state from reset to ready. */
1249 MLX5_RXQ_MOD_RDY2ERR, /* modify state from ready to error. */
1250 MLX5_RXQ_MOD_RDY2RST, /* modify state from ready to reset. */
1253 enum mlx5_txq_modify_type {
1254 MLX5_TXQ_MOD_RST2RDY, /* modify state from reset to ready. */
1255 MLX5_TXQ_MOD_RDY2RST, /* modify state from ready to reset. */
1256 MLX5_TXQ_MOD_ERR2RDY, /* modify state from error to ready. */
1259 /* HW objects operations structure. */
1260 struct mlx5_obj_ops {
1261 int (*rxq_obj_modify_vlan_strip)(struct mlx5_rxq_obj *rxq_obj, int on);
1262 int (*rxq_obj_new)(struct rte_eth_dev *dev, uint16_t idx);
1263 int (*rxq_event_get)(struct mlx5_rxq_obj *rxq_obj);
1264 int (*rxq_obj_modify)(struct mlx5_rxq_obj *rxq_obj, uint8_t type);
1265 void (*rxq_obj_release)(struct mlx5_rxq_obj *rxq_obj);
1266 int (*ind_table_new)(struct rte_eth_dev *dev, const unsigned int log_n,
1267 struct mlx5_ind_table_obj *ind_tbl);
1268 int (*ind_table_modify)(struct rte_eth_dev *dev,
1269 const unsigned int log_n,
1270 const uint16_t *queues, const uint32_t queues_n,
1271 struct mlx5_ind_table_obj *ind_tbl);
1272 void (*ind_table_destroy)(struct mlx5_ind_table_obj *ind_tbl);
1273 int (*hrxq_new)(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq,
1274 int tunnel __rte_unused);
1275 int (*hrxq_modify)(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq,
1276 const uint8_t *rss_key,
1277 uint64_t hash_fields,
1278 const struct mlx5_ind_table_obj *ind_tbl);
1279 void (*hrxq_destroy)(struct mlx5_hrxq *hrxq);
1280 int (*drop_action_create)(struct rte_eth_dev *dev);
1281 void (*drop_action_destroy)(struct rte_eth_dev *dev);
1282 int (*txq_obj_new)(struct rte_eth_dev *dev, uint16_t idx);
1283 int (*txq_obj_modify)(struct mlx5_txq_obj *obj,
1284 enum mlx5_txq_modify_type type, uint8_t dev_port);
1285 void (*txq_obj_release)(struct mlx5_txq_obj *txq_obj);
1288 #define MLX5_RSS_HASH_FIELDS_LEN RTE_DIM(mlx5_rss_hash_fields)
1290 /* MR operations structure. */
1291 struct mlx5_mr_ops {
1292 mlx5_reg_mr_t reg_mr;
1293 mlx5_dereg_mr_t dereg_mr;
1297 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */
1298 struct mlx5_dev_ctx_shared *sh; /* Shared device context. */
1299 uint32_t dev_port; /* Device port number. */
1300 struct rte_pci_device *pci_dev; /* Backend PCI device. */
1301 struct rte_ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */
1302 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES);
1303 /* Bit-field of MAC addresses owned by the PMD. */
1304 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */
1305 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */
1306 /* Device properties. */
1307 uint16_t mtu; /* Configured MTU. */
1308 unsigned int isolated:1; /* Whether isolated mode is enabled. */
1309 unsigned int representor:1; /* Device is a port representor. */
1310 unsigned int master:1; /* Device is a E-Switch master. */
1311 unsigned int txpp_en:1; /* Tx packet pacing enabled. */
1312 unsigned int sampler_en:1; /* Whether support sampler. */
1313 unsigned int mtr_en:1; /* Whether support meter. */
1314 unsigned int mtr_reg_share:1; /* Whether support meter REG_C share. */
1315 uint16_t domain_id; /* Switch domain identifier. */
1316 uint16_t vport_id; /* Associated VF vport index (if any). */
1317 uint32_t vport_meta_tag; /* Used for vport index match ove VF LAG. */
1318 uint32_t vport_meta_mask; /* Used for vport index field match mask. */
1319 int32_t representor_id; /* -1 if not a representor. */
1320 int32_t pf_bond; /* >=0, representor owner PF index in bonding. */
1321 unsigned int if_index; /* Associated kernel network device index. */
1323 unsigned int rxqs_n; /* RX queues array size. */
1324 unsigned int txqs_n; /* TX queues array size. */
1325 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */
1326 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */
1327 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
1328 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */
1329 unsigned int (*reta_idx)[]; /* RETA index table. */
1330 unsigned int reta_idx_n; /* RETA index size. */
1331 struct mlx5_drop drop_queue; /* Flow drop queues. */
1332 uint32_t flows; /* RTE Flow rules. */
1333 uint32_t ctrl_flows; /* Control flow rules. */
1334 rte_spinlock_t flow_list_lock;
1335 struct mlx5_obj_ops obj_ops; /* HW objects operations. */
1336 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */
1337 LIST_HEAD(rxqobj, mlx5_rxq_obj) rxqsobj; /* Verbs/DevX Rx queues. */
1338 struct mlx5_cache_list hrxqs; /* Hash Rx queues. */
1339 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */
1340 LIST_HEAD(txqobj, mlx5_txq_obj) txqsobj; /* Verbs/DevX Tx queues. */
1341 /* Indirection tables. */
1342 LIST_HEAD(ind_tables, mlx5_ind_table_obj) ind_tbls;
1343 /* Pointer to next element. */
1344 uint32_t refcnt; /**< Reference counter. */
1345 /**< Verbs modify header action object. */
1346 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
1347 uint8_t max_lro_msg_size;
1348 /* Tags resources cache. */
1349 uint32_t link_speed_capa; /* Link speed capabilities. */
1350 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */
1351 struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */
1352 struct mlx5_dev_config config; /* Device configuration. */
1353 /* Context for Verbs allocator. */
1354 int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */
1355 int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */
1356 struct mlx5_nl_vlan_vmwa_context *vmwa_context; /* VLAN WA context. */
1357 struct mlx5_hlist *mreg_cp_tbl;
1358 /* Hash table of Rx metadata register copy table. */
1359 uint8_t mtr_sfx_reg; /* Meter prefix-suffix flow match REG_C. */
1360 uint8_t mtr_color_reg; /* Meter color match REG_C. */
1361 struct mlx5_mtr_profiles flow_meter_profiles; /* MTR profile list. */
1362 struct mlx5_legacy_flow_meters flow_meters; /* MTR list. */
1363 struct mlx5_l3t_tbl *mtr_idx_tbl; /* Meter index lookup table. */
1364 uint8_t skip_default_rss_reta; /* Skip configuration of default reta. */
1365 uint8_t fdb_def_rule; /* Whether fdb jump to table 1 is configured. */
1366 struct mlx5_mp_id mp_id; /* ID of a multi-process process */
1367 LIST_HEAD(fdir, mlx5_fdir_flow) fdir_flows; /* fdir flows. */
1368 rte_spinlock_t shared_act_sl; /* Shared actions spinlock. */
1369 uint32_t rss_shared_actions; /* RSS shared actions. */
1370 struct mlx5_devx_obj *q_counters; /* DevX queue counter object. */
1371 uint32_t counter_set_id; /* Queue counter ID to set in DevX objects. */
1374 #define PORT_ID(priv) ((priv)->dev_data->port_id)
1375 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)])
1377 struct rte_hairpin_peer_info {
1381 uint16_t tx_explicit;
1382 uint16_t manual_bind;
1387 int mlx5_getenv_int(const char *);
1388 int mlx5_proc_priv_init(struct rte_eth_dev *dev);
1389 void mlx5_proc_priv_uninit(struct rte_eth_dev *dev);
1390 int mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev,
1391 struct rte_eth_udp_tunnel *udp_tunnel);
1392 uint16_t mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev);
1393 int mlx5_dev_close(struct rte_eth_dev *dev);
1394 bool mlx5_is_hpf(struct rte_eth_dev *dev);
1395 void mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh);
1397 /* Macro to iterate over all valid ports for mlx5 driver. */
1398 #define MLX5_ETH_FOREACH_DEV(port_id, pci_dev) \
1399 for (port_id = mlx5_eth_find_next(0, pci_dev); \
1400 port_id < RTE_MAX_ETHPORTS; \
1401 port_id = mlx5_eth_find_next(port_id + 1, pci_dev))
1402 int mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs);
1403 struct mlx5_dev_ctx_shared *
1404 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
1405 const struct mlx5_dev_config *config);
1406 void mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh);
1407 void mlx5_free_table_hash_list(struct mlx5_priv *priv);
1408 int mlx5_alloc_table_hash_list(struct mlx5_priv *priv);
1409 void mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1410 struct mlx5_dev_config *config);
1411 void mlx5_set_metadata_mask(struct rte_eth_dev *dev);
1412 int mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
1413 struct mlx5_dev_config *config);
1414 int mlx5_dev_configure(struct rte_eth_dev *dev);
1415 int mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info);
1416 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size);
1417 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
1418 int mlx5_hairpin_cap_get(struct rte_eth_dev *dev,
1419 struct rte_eth_hairpin_cap *cap);
1420 bool mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev);
1421 int mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev);
1422 int mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh);
1423 int mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh);
1424 int mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh);
1428 int mlx5_dev_configure(struct rte_eth_dev *dev);
1429 int mlx5_representor_info_get(struct rte_eth_dev *dev,
1430 struct rte_eth_representor_info *info);
1431 #define MLX5_REPRESENTOR_ID(pf, type, repr) \
1432 (((pf) << 14) + ((type) << 12) + ((repr) & 0xfff))
1433 #define MLX5_REPRESENTOR_REPR(repr_id) \
1435 #define MLX5_REPRESENTOR_TYPE(repr_id) \
1436 (((repr_id) >> 12) & 3)
1437 uint16_t mlx5_representor_id_encode(const struct mlx5_switch_info *info,
1438 enum rte_eth_representor_type hpf_type);
1439 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver,
1441 int mlx5_dev_infos_get(struct rte_eth_dev *dev,
1442 struct rte_eth_dev_info *info);
1443 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev);
1444 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
1445 int mlx5_hairpin_cap_get(struct rte_eth_dev *dev,
1446 struct rte_eth_hairpin_cap *cap);
1447 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev);
1448 struct mlx5_priv *mlx5_port_to_eswitch_info(uint16_t port, bool valid);
1449 struct mlx5_priv *mlx5_dev_to_eswitch_info(struct rte_eth_dev *dev);
1450 int mlx5_dev_configure_rss_reta(struct rte_eth_dev *dev);
1452 /* mlx5_ethdev_os.c */
1454 int mlx5_get_ifname(const struct rte_eth_dev *dev,
1455 char (*ifname)[MLX5_NAMESIZE]);
1456 unsigned int mlx5_ifindex(const struct rte_eth_dev *dev);
1457 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]);
1458 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu);
1459 int mlx5_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
1460 int mlx5_read_clock(struct rte_eth_dev *dev, uint64_t *clock);
1461 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete);
1462 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev,
1463 struct rte_eth_fc_conf *fc_conf);
1464 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev,
1465 struct rte_eth_fc_conf *fc_conf);
1466 void mlx5_dev_interrupt_handler(void *arg);
1467 void mlx5_dev_interrupt_handler_devx(void *arg);
1468 int mlx5_set_link_down(struct rte_eth_dev *dev);
1469 int mlx5_set_link_up(struct rte_eth_dev *dev);
1470 int mlx5_is_removed(struct rte_eth_dev *dev);
1471 int mlx5_sysfs_switch_info(unsigned int ifindex,
1472 struct mlx5_switch_info *info);
1473 void mlx5_translate_port_name(const char *port_name_in,
1474 struct mlx5_switch_info *port_info_out);
1475 void mlx5_intr_callback_unregister(const struct rte_intr_handle *handle,
1476 rte_intr_callback_fn cb_fn, void *cb_arg);
1477 int mlx5_sysfs_bond_info(unsigned int pf_ifindex, unsigned int *ifindex,
1479 int mlx5_get_module_info(struct rte_eth_dev *dev,
1480 struct rte_eth_dev_module_info *modinfo);
1481 int mlx5_get_module_eeprom(struct rte_eth_dev *dev,
1482 struct rte_dev_eeprom_info *info);
1483 int mlx5_os_read_dev_stat(struct mlx5_priv *priv,
1484 const char *ctr_name, uint64_t *stat);
1485 int mlx5_os_read_dev_counters(struct rte_eth_dev *dev, uint64_t *stats);
1486 int mlx5_os_get_stats_n(struct rte_eth_dev *dev);
1487 void mlx5_os_stats_init(struct rte_eth_dev *dev);
1491 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
1492 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
1493 uint32_t index, uint32_t vmdq);
1494 int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr);
1495 int mlx5_set_mc_addr_list(struct rte_eth_dev *dev,
1496 struct rte_ether_addr *mc_addr_set,
1497 uint32_t nb_mc_addr);
1501 int mlx5_rss_hash_update(struct rte_eth_dev *dev,
1502 struct rte_eth_rss_conf *rss_conf);
1503 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev,
1504 struct rte_eth_rss_conf *rss_conf);
1505 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size);
1506 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev,
1507 struct rte_eth_rss_reta_entry64 *reta_conf,
1508 uint16_t reta_size);
1509 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev,
1510 struct rte_eth_rss_reta_entry64 *reta_conf,
1511 uint16_t reta_size);
1515 int mlx5_promiscuous_enable(struct rte_eth_dev *dev);
1516 int mlx5_promiscuous_disable(struct rte_eth_dev *dev);
1517 int mlx5_allmulticast_enable(struct rte_eth_dev *dev);
1518 int mlx5_allmulticast_disable(struct rte_eth_dev *dev);
1522 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
1523 int mlx5_stats_reset(struct rte_eth_dev *dev);
1524 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats,
1526 int mlx5_xstats_reset(struct rte_eth_dev *dev);
1527 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
1528 struct rte_eth_xstat_name *xstats_names,
1533 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
1534 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on);
1535 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask);
1537 /* mlx5_vlan_os.c */
1539 void mlx5_vlan_vmwa_exit(void *ctx);
1540 void mlx5_vlan_vmwa_release(struct rte_eth_dev *dev,
1541 struct mlx5_vf_vlan *vf_vlan);
1542 void mlx5_vlan_vmwa_acquire(struct rte_eth_dev *dev,
1543 struct mlx5_vf_vlan *vf_vlan);
1544 void *mlx5_vlan_vmwa_init(struct rte_eth_dev *dev, uint32_t ifindex);
1546 /* mlx5_trigger.c */
1548 int mlx5_dev_start(struct rte_eth_dev *dev);
1549 int mlx5_dev_stop(struct rte_eth_dev *dev);
1550 int mlx5_traffic_enable(struct rte_eth_dev *dev);
1551 void mlx5_traffic_disable(struct rte_eth_dev *dev);
1552 int mlx5_traffic_restart(struct rte_eth_dev *dev);
1553 int mlx5_hairpin_queue_peer_update(struct rte_eth_dev *dev, uint16_t peer_queue,
1554 struct rte_hairpin_peer_info *current_info,
1555 struct rte_hairpin_peer_info *peer_info,
1556 uint32_t direction);
1557 int mlx5_hairpin_queue_peer_bind(struct rte_eth_dev *dev, uint16_t cur_queue,
1558 struct rte_hairpin_peer_info *peer_info,
1559 uint32_t direction);
1560 int mlx5_hairpin_queue_peer_unbind(struct rte_eth_dev *dev, uint16_t cur_queue,
1561 uint32_t direction);
1562 int mlx5_hairpin_bind(struct rte_eth_dev *dev, uint16_t rx_port);
1563 int mlx5_hairpin_unbind(struct rte_eth_dev *dev, uint16_t rx_port);
1564 int mlx5_hairpin_get_peer_ports(struct rte_eth_dev *dev, uint16_t *peer_ports,
1565 size_t len, uint32_t direction);
1569 int mlx5_flow_discover_mreg_c(struct rte_eth_dev *eth_dev);
1570 bool mlx5_flow_ext_mreg_supported(struct rte_eth_dev *dev);
1571 void mlx5_flow_print(struct rte_flow *flow);
1572 int mlx5_flow_validate(struct rte_eth_dev *dev,
1573 const struct rte_flow_attr *attr,
1574 const struct rte_flow_item items[],
1575 const struct rte_flow_action actions[],
1576 struct rte_flow_error *error);
1577 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev,
1578 const struct rte_flow_attr *attr,
1579 const struct rte_flow_item items[],
1580 const struct rte_flow_action actions[],
1581 struct rte_flow_error *error);
1582 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow,
1583 struct rte_flow_error *error);
1584 void mlx5_flow_list_flush(struct rte_eth_dev *dev, uint32_t *list, bool active);
1585 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error);
1586 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow,
1587 const struct rte_flow_action *action, void *data,
1588 struct rte_flow_error *error);
1589 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable,
1590 struct rte_flow_error *error);
1591 int mlx5_flow_ops_get(struct rte_eth_dev *dev, const struct rte_flow_ops **ops);
1592 int mlx5_flow_start_default(struct rte_eth_dev *dev);
1593 void mlx5_flow_stop_default(struct rte_eth_dev *dev);
1594 int mlx5_flow_verify(struct rte_eth_dev *dev);
1595 int mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, uint32_t queue);
1596 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev,
1597 struct rte_flow_item_eth *eth_spec,
1598 struct rte_flow_item_eth *eth_mask,
1599 struct rte_flow_item_vlan *vlan_spec,
1600 struct rte_flow_item_vlan *vlan_mask);
1601 int mlx5_ctrl_flow(struct rte_eth_dev *dev,
1602 struct rte_flow_item_eth *eth_spec,
1603 struct rte_flow_item_eth *eth_mask);
1604 int mlx5_flow_lacp_miss(struct rte_eth_dev *dev);
1605 struct rte_flow *mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev);
1606 void mlx5_flow_async_pool_query_handle(struct mlx5_dev_ctx_shared *sh,
1607 uint64_t async_id, int status);
1608 void mlx5_set_query_alarm(struct mlx5_dev_ctx_shared *sh);
1609 void mlx5_flow_query_alarm(void *arg);
1610 uint32_t mlx5_counter_alloc(struct rte_eth_dev *dev);
1611 void mlx5_counter_free(struct rte_eth_dev *dev, uint32_t cnt);
1612 int mlx5_counter_query(struct rte_eth_dev *dev, uint32_t cnt,
1613 bool clear, uint64_t *pkts, uint64_t *bytes);
1614 int mlx5_flow_dev_dump(struct rte_eth_dev *dev, struct rte_flow *flow,
1615 FILE *file, struct rte_flow_error *error);
1616 void mlx5_flow_rxq_dynf_metadata_set(struct rte_eth_dev *dev);
1617 int mlx5_flow_get_aged_flows(struct rte_eth_dev *dev, void **contexts,
1618 uint32_t nb_contexts, struct rte_flow_error *error);
1619 int mlx5_validate_action_ct(struct rte_eth_dev *dev,
1620 const struct rte_flow_action_conntrack *conntrack,
1621 struct rte_flow_error *error);
1626 int mlx5_mp_os_primary_handle(const struct rte_mp_msg *mp_msg,
1628 int mlx5_mp_os_secondary_handle(const struct rte_mp_msg *mp_msg,
1630 void mlx5_mp_os_req_start_rxtx(struct rte_eth_dev *dev);
1631 void mlx5_mp_os_req_stop_rxtx(struct rte_eth_dev *dev);
1632 int mlx5_mp_os_req_queue_control(struct rte_eth_dev *dev, uint16_t queue_id,
1633 enum mlx5_mp_req_type req_type);
1637 int mlx5_pmd_socket_init(void);
1639 /* mlx5_flow_meter.c */
1641 int mlx5_flow_meter_ops_get(struct rte_eth_dev *dev, void *arg);
1642 struct mlx5_flow_meter_info *mlx5_flow_meter_find(struct mlx5_priv *priv,
1643 uint32_t meter_id, uint32_t *mtr_idx);
1644 struct mlx5_flow_meter_info *
1645 flow_dv_meter_find_by_idx(struct mlx5_priv *priv, uint32_t idx);
1646 int mlx5_flow_meter_attach(struct mlx5_priv *priv,
1647 struct mlx5_flow_meter_info *fm,
1648 const struct rte_flow_attr *attr,
1649 struct rte_flow_error *error);
1650 void mlx5_flow_meter_detach(struct mlx5_priv *priv,
1651 struct mlx5_flow_meter_info *fm);
1652 struct mlx5_flow_meter_policy *mlx5_flow_meter_policy_find
1653 (struct rte_eth_dev *dev,
1655 uint32_t *policy_idx);
1656 int mlx5_flow_meter_flush(struct rte_eth_dev *dev,
1657 struct rte_mtr_error *error);
1660 struct rte_pci_driver;
1661 int mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *dev_attr);
1662 void mlx5_os_free_shared_dr(struct mlx5_priv *priv);
1663 int mlx5_os_open_device(const struct mlx5_dev_spawn_data *spawn,
1664 const struct mlx5_dev_config *config,
1665 struct mlx5_dev_ctx_shared *sh);
1666 int mlx5_os_get_pdn(void *pd, uint32_t *pdn);
1667 int mlx5_os_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1668 struct rte_pci_device *pci_dev);
1669 void mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh);
1670 void mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh);
1671 void mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb,
1672 mlx5_dereg_mr_t *dereg_mr_cb);
1673 void mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
1674 int mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
1676 int mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv, unsigned int iface_idx,
1677 struct rte_ether_addr *mac_addr,
1679 int mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable);
1680 int mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable);
1681 int mlx5_os_set_nonblock_channel_fd(int fd);
1682 void mlx5_os_mac_addr_flush(struct rte_eth_dev *dev);
1686 int mlx5_txpp_start(struct rte_eth_dev *dev);
1687 void mlx5_txpp_stop(struct rte_eth_dev *dev);
1688 int mlx5_txpp_read_clock(struct rte_eth_dev *dev, uint64_t *timestamp);
1689 int mlx5_txpp_xstats_get(struct rte_eth_dev *dev,
1690 struct rte_eth_xstat *stats,
1691 unsigned int n, unsigned int n_used);
1692 int mlx5_txpp_xstats_reset(struct rte_eth_dev *dev);
1693 int mlx5_txpp_xstats_get_names(struct rte_eth_dev *dev,
1694 struct rte_eth_xstat_name *xstats_names,
1695 unsigned int n, unsigned int n_used);
1696 void mlx5_txpp_interrupt_handler(void *cb_arg);
1700 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev);
1702 /* mlx5_flow_aso.c */
1704 int mlx5_aso_queue_init(struct mlx5_dev_ctx_shared *sh,
1705 enum mlx5_access_aso_opc_mod aso_opc_mod);
1706 int mlx5_aso_flow_hit_queue_poll_start(struct mlx5_dev_ctx_shared *sh);
1707 int mlx5_aso_flow_hit_queue_poll_stop(struct mlx5_dev_ctx_shared *sh);
1708 void mlx5_aso_queue_uninit(struct mlx5_dev_ctx_shared *sh,
1709 enum mlx5_access_aso_opc_mod aso_opc_mod);
1710 int mlx5_aso_meter_update_by_wqe(struct mlx5_dev_ctx_shared *sh,
1711 struct mlx5_aso_mtr *mtr);
1712 int mlx5_aso_mtr_wait(struct mlx5_dev_ctx_shared *sh,
1713 struct mlx5_aso_mtr *mtr);
1714 int mlx5_aso_ct_update_by_wqe(struct mlx5_dev_ctx_shared *sh,
1715 struct mlx5_aso_ct_action *ct,
1716 const struct rte_flow_action_conntrack *profile);
1717 int mlx5_aso_ct_wait_ready(struct mlx5_dev_ctx_shared *sh,
1718 struct mlx5_aso_ct_action *ct);
1719 int mlx5_aso_ct_query_by_wqe(struct mlx5_dev_ctx_shared *sh,
1720 struct mlx5_aso_ct_action *ct,
1721 struct rte_flow_action_conntrack *profile);
1722 int mlx5_aso_ct_available(struct mlx5_dev_ctx_shared *sh,
1723 struct mlx5_aso_ct_action *ct);
1725 #endif /* RTE_PMD_MLX5_H_ */