1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_H_
7 #define RTE_PMD_MLX5_H_
13 #include <netinet/in.h>
14 #include <sys/queue.h>
17 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
19 #pragma GCC diagnostic ignored "-Wpedantic"
21 #include <infiniband/verbs.h>
23 #pragma GCC diagnostic error "-Wpedantic"
27 #include <rte_ether.h>
28 #include <rte_ethdev_driver.h>
29 #include <rte_rwlock.h>
30 #include <rte_interrupts.h>
31 #include <rte_errno.h>
34 #include "mlx5_utils.h"
36 #include "mlx5_autoconf.h"
37 #include "mlx5_defs.h"
40 PCI_VENDOR_ID_MELLANOX = 0x15b3,
44 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013,
45 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014,
46 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015,
47 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016,
48 PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017,
49 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018,
50 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019,
51 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a,
52 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF = 0xa2d2,
53 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF = 0xa2d3,
54 PCI_DEVICE_ID_MELLANOX_CONNECTX6 = 0x101b,
55 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF = 0x101c,
58 /* Request types for IPC. */
59 enum mlx5_mp_req_type {
60 MLX5_MP_REQ_VERBS_CMD_FD = 1,
61 MLX5_MP_REQ_CREATE_MR,
62 MLX5_MP_REQ_START_RXTX,
63 MLX5_MP_REQ_STOP_RXTX,
66 /* Pameters for IPC. */
67 struct mlx5_mp_param {
68 enum mlx5_mp_req_type type;
73 uintptr_t addr; /* MLX5_MP_REQ_CREATE_MR */
77 /** Request timeout for IPC. */
78 #define MLX5_MP_REQ_TIMEOUT_SEC 5
80 /** Key string for IPC. */
81 #define MLX5_MP_NAME "net_mlx5_mp"
83 /* Recognized Infiniband device physical port name types. */
84 enum mlx5_phys_port_name_type {
85 MLX5_PHYS_PORT_NAME_TYPE_NOTSET = 0, /* Not set. */
86 MLX5_PHYS_PORT_NAME_TYPE_LEGACY, /* before kernel ver < 5.0 */
87 MLX5_PHYS_PORT_NAME_TYPE_UPLINK, /* p0, kernel ver >= 5.0 */
88 MLX5_PHYS_PORT_NAME_TYPE_PFVF, /* pf0vf0, kernel ver >= 5.0 */
89 MLX5_PHYS_PORT_NAME_TYPE_UNKNOWN, /* Unrecognized. */
92 /** Switch information returned by mlx5_nl_switch_info(). */
93 struct mlx5_switch_info {
94 uint32_t master:1; /**< Master device. */
95 uint32_t representor:1; /**< Representor device. */
96 enum mlx5_phys_port_name_type name_type; /** < Port name type. */
97 int32_t pf_num; /**< PF number (valid for pfxvfx format only). */
98 int32_t port_name; /**< Representor port name. */
99 uint64_t switch_id; /**< Switch identifier. */
102 LIST_HEAD(mlx5_dev_list, mlx5_ibv_shared);
104 /* Shared data between primary and secondary processes. */
105 struct mlx5_shared_data {
107 /* Global spinlock for primary and secondary processes. */
108 int init_done; /* Whether primary has done initialization. */
109 unsigned int secondary_cnt; /* Number of secondary processes init'd. */
110 struct mlx5_dev_list mem_event_cb_list;
111 rte_rwlock_t mem_event_rwlock;
114 /* Per-process data structure, not visible to other processes. */
115 struct mlx5_local_data {
116 int init_done; /* Whether a secondary has done initialization. */
119 extern struct mlx5_shared_data *mlx5_shared_data;
121 struct mlx5_counter_ctrl {
122 /* Name of the counter. */
123 char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE];
124 /* Name of the counter on the device table. */
125 char ctr_name[RTE_ETH_XSTATS_NAME_SIZE];
126 uint32_t ib:1; /**< Nonzero for IB counters. */
129 struct mlx5_xstats_ctrl {
130 /* Number of device stats. */
132 /* Number of device stats identified by PMD. */
133 uint16_t mlx5_stats_n;
134 /* Index in the device counters table. */
135 uint16_t dev_table_idx[MLX5_MAX_XSTATS];
136 uint64_t base[MLX5_MAX_XSTATS];
137 struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS];
140 struct mlx5_stats_ctrl {
141 /* Base for imissed counter. */
142 uint64_t imissed_base;
145 /* devx counter object */
146 struct mlx5_devx_counter_set {
147 struct mlx5dv_devx_obj *obj;
148 int id; /* Flow counter ID */
151 /* HCA attributes. */
152 struct mlx5_hca_attr {
153 uint32_t eswitch_manager:1;
157 TAILQ_HEAD(mlx5_flows, rte_flow);
159 /* Default PMD specific parameter value. */
160 #define MLX5_ARG_UNSET (-1)
163 * Device configuration structure.
165 * Merged configuration from:
167 * - Device capabilities,
168 * - User device parameters disabled features.
170 struct mlx5_dev_config {
171 unsigned int hw_csum:1; /* Checksum offload is supported. */
172 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */
173 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */
174 unsigned int hw_padding:1; /* End alignment padding is supported. */
175 unsigned int vf:1; /* This is a VF. */
176 unsigned int tunnel_en:1;
177 /* Whether tunnel stateless offloads are supported. */
178 unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */
179 unsigned int cqe_comp:1; /* CQE compression is enabled. */
180 unsigned int cqe_pad:1; /* CQE padding is enabled. */
181 unsigned int tso:1; /* Whether TSO is supported. */
182 unsigned int tx_vec_en:1; /* Tx vector is enabled. */
183 unsigned int rx_vec_en:1; /* Rx vector is enabled. */
184 unsigned int mpw_hdr_dseg:1; /* Enable DSEGs in the title WQEBB. */
185 unsigned int mr_ext_memseg_en:1;
186 /* Whether memseg should be extended for MR creation. */
187 unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */
188 unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */
189 unsigned int dv_esw_en:1; /* Enable E-Switch DV flow. */
190 unsigned int dv_flow_en:1; /* Enable DV flow. */
191 unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */
192 unsigned int devx:1; /* Whether devx interface is available or not. */
194 unsigned int enabled:1; /* Whether MPRQ is enabled. */
195 unsigned int stride_num_n; /* Number of strides. */
196 unsigned int min_stride_size_n; /* Min size of a stride. */
197 unsigned int max_stride_size_n; /* Max size of a stride. */
198 unsigned int max_memcpy_len;
199 /* Maximum packet size to memcpy Rx packets. */
200 unsigned int min_rxqs_num;
201 /* Rx queue count threshold to enable MPRQ. */
202 } mprq; /* Configurations for Multi-Packet RQ. */
203 int mps; /* Multi-packet send supported mode. */
204 unsigned int flow_prio; /* Number of flow priorities. */
205 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */
206 unsigned int ind_table_max_size; /* Maximum indirection table size. */
207 unsigned int max_dump_files_num; /* Maximum dump files per queue. */
208 int txq_inline; /* Maximum packet size for inlining. */
209 int txqs_inline; /* Queue number threshold for inlining. */
210 int txqs_vec; /* Queue number threshold for vectorized Tx. */
211 int inline_max_packet_sz; /* Max packet size for inlining. */
212 struct mlx5_hca_attr hca_attr; /* HCA attributes. */
216 * Type of objet being allocated.
218 enum mlx5_verbs_alloc_type {
219 MLX5_VERBS_ALLOC_TYPE_NONE,
220 MLX5_VERBS_ALLOC_TYPE_TX_QUEUE,
221 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE,
225 * Verbs allocator needs a context to know in the callback which kind of
226 * resources it is allocating.
228 struct mlx5_verbs_alloc_ctx {
229 enum mlx5_verbs_alloc_type type; /* Kind of object being allocated. */
230 const void *obj; /* Pointer to the DPDK object. */
233 LIST_HEAD(mlx5_mr_list, mlx5_mr);
235 /* Flow drop context necessary due to Verbs API. */
237 struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */
238 struct mlx5_rxq_ibv *rxq; /* Verbs Rx queue. */
241 struct mlx5_flow_tcf_context;
243 /* Per port data of shared IB device. */
244 struct mlx5_ibv_shared_port {
247 * Interrupt handler port_id. Used by shared interrupt
248 * handler to find the corresponding rte_eth device
249 * by IB port index. If value is equal or greater
250 * RTE_MAX_ETHPORTS it means there is no subhandler
251 * installed for specified IB port index.
255 /* Table structure. */
256 struct mlx5_flow_tbl_resource {
257 void *obj; /**< Pointer to DR table object. */
258 rte_atomic32_t refcnt; /**< Reference counter. */
261 #define MLX5_MAX_TABLES 1024
262 #define MLX5_MAX_TABLES_FDB 32
263 #define MLX5_GROUP_FACTOR 1
266 * Shared Infiniband device context for Master/Representors
267 * which belong to same IB device with multiple IB ports.
269 struct mlx5_ibv_shared {
270 LIST_ENTRY(mlx5_ibv_shared) next;
272 uint32_t devx:1; /* Opened with DV. */
273 uint32_t max_port; /* Maximal IB device port index. */
274 struct ibv_context *ctx; /* Verbs/DV context. */
275 struct ibv_pd *pd; /* Protection Domain. */
276 char ibdev_name[IBV_SYSFS_NAME_MAX]; /* IB device name. */
277 char ibdev_path[IBV_SYSFS_PATH_MAX]; /* IB device path for secondary */
278 struct ibv_device_attr_ex device_attr; /* Device properties. */
279 struct rte_pci_device *pci_dev; /* Backend PCI device. */
280 LIST_ENTRY(mlx5_ibv_shared) mem_event_cb;
281 /**< Called by memory event callback. */
283 uint32_t dev_gen; /* Generation number to flush local caches. */
284 rte_rwlock_t rwlock; /* MR Lock. */
285 struct mlx5_mr_btree cache; /* Global MR cache table. */
286 struct mlx5_mr_list mr_list; /* Registered MR list. */
287 struct mlx5_mr_list mr_free_list; /* Freed MR list. */
289 /* Shared DV/DR flow data section. */
290 pthread_mutex_t dv_mutex; /* DV context mutex. */
291 uint32_t dv_refcnt; /* DV/DR data reference counter. */
292 void *fdb_domain; /* FDB Direct Rules name space handle. */
293 struct mlx5_flow_tbl_resource fdb_tbl[MLX5_MAX_TABLES_FDB];
294 /* FDB Direct Rules tables. */
295 void *rx_domain; /* RX Direct Rules name space handle. */
296 struct mlx5_flow_tbl_resource rx_tbl[MLX5_MAX_TABLES];
297 /* RX Direct Rules tables. */
298 void *tx_domain; /* TX Direct Rules name space handle. */
299 struct mlx5_flow_tbl_resource tx_tbl[MLX5_MAX_TABLES];
300 void *esw_drop_action; /* Pointer to DR E-Switch drop action. */
301 /* TX Direct Rules tables/ */
302 LIST_HEAD(matchers, mlx5_flow_dv_matcher) matchers;
303 LIST_HEAD(encap_decap, mlx5_flow_dv_encap_decap_resource) encaps_decaps;
304 LIST_HEAD(modify_cmd, mlx5_flow_dv_modify_hdr_resource) modify_cmds;
305 LIST_HEAD(tag, mlx5_flow_dv_tag_resource) tags;
306 LIST_HEAD(jump, mlx5_flow_dv_jump_tbl_resource) jump_tbl;
307 LIST_HEAD(port_id_action_list, mlx5_flow_dv_port_id_action_resource)
308 port_id_action_list; /* List of port ID actions. */
309 /* Shared interrupt handler section. */
310 pthread_mutex_t intr_mutex; /* Interrupt config mutex. */
311 uint32_t intr_cnt; /* Interrupt handler reference counter. */
312 struct rte_intr_handle intr_handle; /* Interrupt handler for device. */
313 struct mlx5_ibv_shared_port port[]; /* per device port data array. */
316 /* Per-process private structure. */
317 struct mlx5_proc_priv {
319 /* Size of UAR register table. */
321 /* Table of UAR registers for each process. */
324 #define MLX5_PROC_PRIV(port_id) \
325 ((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private)
328 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */
329 struct mlx5_ibv_shared *sh; /* Shared IB device context. */
330 uint32_t ibv_port; /* IB device port number. */
331 struct rte_ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */
332 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES);
333 /* Bit-field of MAC addresses owned by the PMD. */
334 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */
335 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */
336 /* Device properties. */
337 uint16_t mtu; /* Configured MTU. */
338 unsigned int isolated:1; /* Whether isolated mode is enabled. */
339 unsigned int representor:1; /* Device is a port representor. */
340 unsigned int master:1; /* Device is a E-Switch master. */
341 unsigned int dr_shared:1; /* DV/DR data is shared. */
342 uint16_t domain_id; /* Switch domain identifier. */
343 uint16_t vport_id; /* Associated VF vport index (if any). */
344 int32_t representor_id; /* Port representor identifier. */
346 unsigned int rxqs_n; /* RX queues array size. */
347 unsigned int txqs_n; /* TX queues array size. */
348 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */
349 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */
350 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
351 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */
352 unsigned int (*reta_idx)[]; /* RETA index table. */
353 unsigned int reta_idx_n; /* RETA index size. */
354 struct mlx5_drop drop_queue; /* Flow drop queues. */
355 struct mlx5_flows flows; /* RTE Flow rules. */
356 struct mlx5_flows ctrl_flows; /* Control flow rules. */
357 LIST_HEAD(counters, mlx5_flow_counter) flow_counters;
359 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */
360 LIST_HEAD(rxqibv, mlx5_rxq_ibv) rxqsibv; /* Verbs Rx queues. */
361 LIST_HEAD(hrxq, mlx5_hrxq) hrxqs; /* Verbs Hash Rx queues. */
362 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */
363 LIST_HEAD(txqibv, mlx5_txq_ibv) txqsibv; /* Verbs Tx queues. */
364 /* Verbs Indirection tables. */
365 LIST_HEAD(ind_tables, mlx5_ind_table_ibv) ind_tbls;
366 /* Pointer to next element. */
367 rte_atomic32_t refcnt; /**< Reference counter. */
368 struct ibv_flow_action *verbs_action;
369 /**< Verbs modify header action object. */
370 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
371 /* Tags resources cache. */
372 uint32_t link_speed_capa; /* Link speed capabilities. */
373 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */
374 struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */
375 struct mlx5_dev_config config; /* Device configuration. */
376 struct mlx5_verbs_alloc_ctx verbs_alloc_ctx;
377 /* Context for Verbs allocator. */
378 int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */
379 int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */
380 uint32_t nl_sn; /* Netlink message sequence number. */
382 rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */
383 rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX];
384 /* UAR same-page access control required in 32bit implementations. */
386 struct mlx5_flow_tcf_context *tcf_context; /* TC flower context. */
389 #define PORT_ID(priv) ((priv)->dev_data->port_id)
390 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)])
394 int mlx5_getenv_int(const char *);
395 int mlx5_proc_priv_init(struct rte_eth_dev *dev);
399 int mlx5_get_ifname(const struct rte_eth_dev *dev, char (*ifname)[IF_NAMESIZE]);
400 int mlx5_get_master_ifname(const char *ibdev_path, char (*ifname)[IF_NAMESIZE]);
401 unsigned int mlx5_ifindex(const struct rte_eth_dev *dev);
402 int mlx5_ifreq(const struct rte_eth_dev *dev, int req, struct ifreq *ifr);
403 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu);
404 int mlx5_set_flags(struct rte_eth_dev *dev, unsigned int keep,
406 int mlx5_dev_configure(struct rte_eth_dev *dev);
407 void mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info);
408 int mlx5_read_clock(struct rte_eth_dev *dev, uint64_t *clock);
409 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size);
410 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev);
411 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete);
412 int mlx5_force_link_status_change(struct rte_eth_dev *dev, int status);
413 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
414 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev,
415 struct rte_eth_fc_conf *fc_conf);
416 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev,
417 struct rte_eth_fc_conf *fc_conf);
418 int mlx5_ibv_device_to_pci_addr(const struct ibv_device *device,
419 struct rte_pci_addr *pci_addr);
420 void mlx5_dev_link_status_handler(void *arg);
421 void mlx5_dev_interrupt_handler(void *arg);
422 void mlx5_dev_interrupt_handler_uninstall(struct rte_eth_dev *dev);
423 void mlx5_dev_interrupt_handler_install(struct rte_eth_dev *dev);
424 int mlx5_set_link_down(struct rte_eth_dev *dev);
425 int mlx5_set_link_up(struct rte_eth_dev *dev);
426 int mlx5_is_removed(struct rte_eth_dev *dev);
427 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev);
428 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev);
429 unsigned int mlx5_dev_to_port_id(const struct rte_device *dev,
431 unsigned int port_list_n);
432 int mlx5_port_to_eswitch_info(uint16_t port, uint16_t *es_domain_id,
433 uint16_t *es_port_id);
434 int mlx5_sysfs_switch_info(unsigned int ifindex,
435 struct mlx5_switch_info *info);
436 void mlx5_sysfs_check_switch_info(bool device_dir,
437 struct mlx5_switch_info *switch_info);
438 void mlx5_nl_check_switch_info(bool nun_vf_set,
439 struct mlx5_switch_info *switch_info);
440 void mlx5_translate_port_name(const char *port_name_in,
441 struct mlx5_switch_info *port_info_out);
442 void mlx5_intr_callback_unregister(const struct rte_intr_handle *handle,
443 rte_intr_callback_fn cb_fn, void *cb_arg);
447 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]);
448 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
449 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
450 uint32_t index, uint32_t vmdq);
451 int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr);
452 int mlx5_set_mc_addr_list(struct rte_eth_dev *dev,
453 struct rte_ether_addr *mc_addr_set,
454 uint32_t nb_mc_addr);
458 int mlx5_rss_hash_update(struct rte_eth_dev *dev,
459 struct rte_eth_rss_conf *rss_conf);
460 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev,
461 struct rte_eth_rss_conf *rss_conf);
462 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size);
463 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev,
464 struct rte_eth_rss_reta_entry64 *reta_conf,
466 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev,
467 struct rte_eth_rss_reta_entry64 *reta_conf,
472 void mlx5_promiscuous_enable(struct rte_eth_dev *dev);
473 void mlx5_promiscuous_disable(struct rte_eth_dev *dev);
474 void mlx5_allmulticast_enable(struct rte_eth_dev *dev);
475 void mlx5_allmulticast_disable(struct rte_eth_dev *dev);
479 void mlx5_stats_init(struct rte_eth_dev *dev);
480 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
481 void mlx5_stats_reset(struct rte_eth_dev *dev);
482 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats,
484 void mlx5_xstats_reset(struct rte_eth_dev *dev);
485 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
486 struct rte_eth_xstat_name *xstats_names,
491 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
492 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on);
493 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask);
497 int mlx5_dev_start(struct rte_eth_dev *dev);
498 void mlx5_dev_stop(struct rte_eth_dev *dev);
499 int mlx5_traffic_enable(struct rte_eth_dev *dev);
500 void mlx5_traffic_disable(struct rte_eth_dev *dev);
501 int mlx5_traffic_restart(struct rte_eth_dev *dev);
505 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
506 void mlx5_flow_print(struct rte_flow *flow);
507 int mlx5_flow_validate(struct rte_eth_dev *dev,
508 const struct rte_flow_attr *attr,
509 const struct rte_flow_item items[],
510 const struct rte_flow_action actions[],
511 struct rte_flow_error *error);
512 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev,
513 const struct rte_flow_attr *attr,
514 const struct rte_flow_item items[],
515 const struct rte_flow_action actions[],
516 struct rte_flow_error *error);
517 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow,
518 struct rte_flow_error *error);
519 void mlx5_flow_list_flush(struct rte_eth_dev *dev, struct mlx5_flows *list);
520 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error);
521 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow,
522 const struct rte_flow_action *action, void *data,
523 struct rte_flow_error *error);
524 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable,
525 struct rte_flow_error *error);
526 int mlx5_dev_filter_ctrl(struct rte_eth_dev *dev,
527 enum rte_filter_type filter_type,
528 enum rte_filter_op filter_op,
530 int mlx5_flow_start(struct rte_eth_dev *dev, struct mlx5_flows *list);
531 void mlx5_flow_stop(struct rte_eth_dev *dev, struct mlx5_flows *list);
532 int mlx5_flow_verify(struct rte_eth_dev *dev);
533 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev,
534 struct rte_flow_item_eth *eth_spec,
535 struct rte_flow_item_eth *eth_mask,
536 struct rte_flow_item_vlan *vlan_spec,
537 struct rte_flow_item_vlan *vlan_mask);
538 int mlx5_ctrl_flow(struct rte_eth_dev *dev,
539 struct rte_flow_item_eth *eth_spec,
540 struct rte_flow_item_eth *eth_mask);
541 int mlx5_flow_create_drop_queue(struct rte_eth_dev *dev);
542 void mlx5_flow_delete_drop_queue(struct rte_eth_dev *dev);
545 void mlx5_mp_req_start_rxtx(struct rte_eth_dev *dev);
546 void mlx5_mp_req_stop_rxtx(struct rte_eth_dev *dev);
547 int mlx5_mp_req_mr_create(struct rte_eth_dev *dev, uintptr_t addr);
548 int mlx5_mp_req_verbs_cmd_fd(struct rte_eth_dev *dev);
549 int mlx5_mp_init_primary(void);
550 void mlx5_mp_uninit_primary(void);
551 int mlx5_mp_init_secondary(void);
552 void mlx5_mp_uninit_secondary(void);
556 int mlx5_nl_init(int protocol);
557 int mlx5_nl_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
559 int mlx5_nl_mac_addr_remove(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
561 void mlx5_nl_mac_addr_sync(struct rte_eth_dev *dev);
562 void mlx5_nl_mac_addr_flush(struct rte_eth_dev *dev);
563 int mlx5_nl_promisc(struct rte_eth_dev *dev, int enable);
564 int mlx5_nl_allmulti(struct rte_eth_dev *dev, int enable);
565 unsigned int mlx5_nl_portnum(int nl, const char *name);
566 unsigned int mlx5_nl_ifindex(int nl, const char *name, uint32_t pindex);
567 int mlx5_nl_switch_info(int nl, unsigned int ifindex,
568 struct mlx5_switch_info *info);
570 /* mlx5_devx_cmds.c */
572 int mlx5_devx_cmd_flow_counter_alloc(struct ibv_context *ctx,
573 struct mlx5_devx_counter_set *dcx);
574 int mlx5_devx_cmd_flow_counter_free(struct mlx5dv_devx_obj *obj);
575 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_counter_set *dcx,
577 uint64_t *pkts, uint64_t *bytes);
578 int mlx5_devx_cmd_query_hca_attr(struct ibv_context *ctx,
579 struct mlx5_hca_attr *attr);
580 #endif /* RTE_PMD_MLX5_H_ */