1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_H_
7 #define RTE_PMD_MLX5_H_
13 #include <netinet/in.h>
14 #include <sys/queue.h>
17 #include <rte_ether.h>
18 #include <rte_ethdev_driver.h>
19 #include <rte_rwlock.h>
20 #include <rte_interrupts.h>
21 #include <rte_errno.h>
24 #include <mlx5_glue.h>
25 #include <mlx5_devx_cmds.h>
27 #include <mlx5_common_mp.h>
28 #include <mlx5_common_mr.h>
30 #include "mlx5_defs.h"
31 #include "mlx5_utils.h"
33 #include "mlx5_autoconf.h"
35 enum mlx5_ipool_index {
36 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
37 MLX5_IPOOL_DECAP_ENCAP = 0, /* Pool for encap/decap resource. */
38 MLX5_IPOOL_PUSH_VLAN, /* Pool for push vlan resource. */
39 MLX5_IPOOL_TAG, /* Pool for tag resource. */
40 MLX5_IPOOL_PORT_ID, /* Pool for port id resource. */
41 MLX5_IPOOL_JUMP, /* Pool for jump resource. */
43 MLX5_IPOOL_MTR, /* Pool for meter resource. */
44 MLX5_IPOOL_MCP, /* Pool for metadata resource. */
45 MLX5_IPOOL_HRXQ, /* Pool for hrxq resource. */
46 MLX5_IPOOL_MLX5_FLOW, /* Pool for mlx5 flow handle. */
47 MLX5_IPOOL_RTE_FLOW, /* Pool for rte_flow. */
52 * There are three reclaim memory mode supported.
53 * 0(none) means no memory reclaim.
54 * 1(light) means only PMD level reclaim.
55 * 2(aggressive) means both PMD and rdma-core level reclaim.
57 enum mlx5_reclaim_mem_mode {
58 MLX5_RCM_NONE, /* Don't reclaim memory. */
59 MLX5_RCM_LIGHT, /* Reclaim PMD level. */
60 MLX5_RCM_AGGR, /* Reclaim PMD and rdma-core level. */
63 /* Device attributes used in mlx5 PMD */
64 struct mlx5_dev_attr {
65 uint64_t device_cap_flags_ex;
70 uint32_t raw_packet_caps;
71 uint32_t max_rwq_indirection_table_size;
73 uint32_t tso_supported_qpts;
76 uint32_t sw_parsing_offloads;
77 uint32_t min_single_stride_log_num_of_bytes;
78 uint32_t max_single_stride_log_num_of_bytes;
79 uint32_t min_single_wqe_log_num_of_strides;
80 uint32_t max_single_wqe_log_num_of_strides;
81 uint32_t stride_supported_qpts;
82 uint32_t tunnel_offloads_caps;
86 /** Data associated with devices to spawn. */
87 struct mlx5_dev_spawn_data {
88 uint32_t ifindex; /**< Network interface index. */
89 uint32_t max_port; /**< Device maximal port index. */
90 uint32_t phys_port; /**< Device physical port index. */
91 int pf_bond; /**< bonding device PF index. < 0 - no bonding */
92 struct mlx5_switch_info info; /**< Switch information. */
93 void *phys_dev; /**< Associated physical device. */
94 struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */
95 struct rte_pci_device *pci_dev; /**< Backend PCI device. */
98 /** Key string for IPC. */
99 #define MLX5_MP_NAME "net_mlx5_mp"
102 LIST_HEAD(mlx5_dev_list, mlx5_dev_ctx_shared);
104 /* Shared data between primary and secondary processes. */
105 struct mlx5_shared_data {
107 /* Global spinlock for primary and secondary processes. */
108 int init_done; /* Whether primary has done initialization. */
109 unsigned int secondary_cnt; /* Number of secondary processes init'd. */
110 struct mlx5_dev_list mem_event_cb_list;
111 rte_rwlock_t mem_event_rwlock;
114 /* Per-process data structure, not visible to other processes. */
115 struct mlx5_local_data {
116 int init_done; /* Whether a secondary has done initialization. */
119 extern struct mlx5_shared_data *mlx5_shared_data;
121 /* Dev ops structs */
122 extern const struct eth_dev_ops mlx5_os_dev_ops;
123 extern const struct eth_dev_ops mlx5_os_dev_sec_ops;
124 extern const struct eth_dev_ops mlx5_os_dev_ops_isolate;
126 struct mlx5_counter_ctrl {
127 /* Name of the counter. */
128 char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE];
129 /* Name of the counter on the device table. */
130 char ctr_name[RTE_ETH_XSTATS_NAME_SIZE];
131 uint32_t dev:1; /**< Nonzero for dev counters. */
134 struct mlx5_xstats_ctrl {
135 /* Number of device stats. */
137 /* Number of device stats identified by PMD. */
138 uint16_t mlx5_stats_n;
139 /* Index in the device counters table. */
140 uint16_t dev_table_idx[MLX5_MAX_XSTATS];
141 uint64_t base[MLX5_MAX_XSTATS];
142 uint64_t xstats[MLX5_MAX_XSTATS];
143 uint64_t hw_stats[MLX5_MAX_XSTATS];
144 struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS];
147 struct mlx5_stats_ctrl {
148 /* Base for imissed counter. */
149 uint64_t imissed_base;
153 /* Default PMD specific parameter value. */
154 #define MLX5_ARG_UNSET (-1)
156 #define MLX5_LRO_SUPPORTED(dev) \
157 (((struct mlx5_priv *)((dev)->data->dev_private))->config.lro.supported)
159 /* Maximal size of coalesced segment for LRO is set in chunks of 256 Bytes. */
160 #define MLX5_LRO_SEG_CHUNK_SIZE 256u
162 /* Maximal size of aggregated LRO packet. */
163 #define MLX5_MAX_LRO_SIZE (UINT8_MAX * MLX5_LRO_SEG_CHUNK_SIZE)
165 /* LRO configurations structure. */
166 struct mlx5_lro_config {
167 uint32_t supported:1; /* Whether LRO is supported. */
168 uint32_t timeout; /* User configuration. */
172 * Device configuration structure.
174 * Merged configuration from:
176 * - Device capabilities,
177 * - User device parameters disabled features.
179 struct mlx5_dev_config {
180 unsigned int hw_csum:1; /* Checksum offload is supported. */
181 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */
182 unsigned int hw_vlan_insert:1; /* VLAN insertion in WQE is supported. */
183 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */
184 unsigned int hw_padding:1; /* End alignment padding is supported. */
185 unsigned int vf:1; /* This is a VF. */
186 unsigned int tunnel_en:1;
187 /* Whether tunnel stateless offloads are supported. */
188 unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */
189 unsigned int cqe_comp:1; /* CQE compression is enabled. */
190 unsigned int cqe_pad:1; /* CQE padding is enabled. */
191 unsigned int tso:1; /* Whether TSO is supported. */
192 unsigned int rx_vec_en:1; /* Rx vector is enabled. */
193 unsigned int mr_ext_memseg_en:1;
194 /* Whether memseg should be extended for MR creation. */
195 unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */
196 unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */
197 unsigned int dv_esw_en:1; /* Enable E-Switch DV flow. */
198 unsigned int dv_flow_en:1; /* Enable DV flow. */
199 unsigned int dv_xmeta_en:2; /* Enable extensive flow metadata. */
200 unsigned int lacp_by_user:1;
201 /* Enable user to manage LACP traffic. */
202 unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */
203 unsigned int devx:1; /* Whether devx interface is available or not. */
204 unsigned int dest_tir:1; /* Whether advanced DR API is available. */
205 unsigned int reclaim_mode:2; /* Memory reclaim mode. */
206 unsigned int rt_timestamp:1; /* realtime timestamp format. */
207 unsigned int sys_mem_en:1; /* The default memory allocator. */
208 unsigned int decap_en:1; /* Whether decap will be used or not. */
210 unsigned int enabled:1; /* Whether MPRQ is enabled. */
211 unsigned int stride_num_n; /* Number of strides. */
212 unsigned int stride_size_n; /* Size of a stride. */
213 unsigned int min_stride_size_n; /* Min size of a stride. */
214 unsigned int max_stride_size_n; /* Max size of a stride. */
215 unsigned int max_memcpy_len;
216 /* Maximum packet size to memcpy Rx packets. */
217 unsigned int min_rxqs_num;
218 /* Rx queue count threshold to enable MPRQ. */
219 } mprq; /* Configurations for Multi-Packet RQ. */
220 int mps; /* Multi-packet send supported mode. */
221 int dbnc; /* Skip doorbell register write barrier. */
222 unsigned int flow_prio; /* Number of flow priorities. */
223 enum modify_reg flow_mreg_c[MLX5_MREG_C_NUM];
224 /* Availibility of mreg_c's. */
225 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */
226 unsigned int ind_table_max_size; /* Maximum indirection table size. */
227 unsigned int max_dump_files_num; /* Maximum dump files per queue. */
228 unsigned int log_hp_size; /* Single hairpin queue data size in total. */
229 int txqs_inline; /* Queue number threshold for inlining. */
230 int txq_inline_min; /* Minimal amount of data bytes to inline. */
231 int txq_inline_max; /* Max packet size for inlining with SEND. */
232 int txq_inline_mpw; /* Max packet size for inlining with eMPW. */
233 int tx_pp; /* Timestamp scheduling granularity in nanoseconds. */
234 int tx_skew; /* Tx scheduling skew between WQE and data on wire. */
235 struct mlx5_hca_attr hca_attr; /* HCA attributes. */
236 struct mlx5_lro_config lro; /* LRO configuration. */
241 * Type of object being allocated.
243 enum mlx5_verbs_alloc_type {
244 MLX5_VERBS_ALLOC_TYPE_NONE,
245 MLX5_VERBS_ALLOC_TYPE_TX_QUEUE,
246 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE,
249 /* Structure for VF VLAN workaround. */
250 struct mlx5_vf_vlan {
256 * Verbs allocator needs a context to know in the callback which kind of
257 * resources it is allocating.
259 struct mlx5_verbs_alloc_ctx {
260 enum mlx5_verbs_alloc_type type; /* Kind of object being allocated. */
261 const void *obj; /* Pointer to the DPDK object. */
264 /* Flow drop context necessary due to Verbs API. */
266 struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */
267 struct mlx5_rxq_obj *rxq; /* Rx queue object. */
270 #define MLX5_COUNTERS_PER_POOL 512
271 #define MLX5_MAX_PENDING_QUERIES 4
272 #define MLX5_CNT_CONTAINER_RESIZE 64
273 #define MLX5_CNT_AGE_OFFSET 0x80000000
274 #define CNT_SIZE (sizeof(struct mlx5_flow_counter))
275 #define CNTEXT_SIZE (sizeof(struct mlx5_flow_counter_ext))
276 #define AGE_SIZE (sizeof(struct mlx5_age_param))
277 #define MLX5_AGING_TIME_DELAY 7
278 #define CNT_POOL_TYPE_EXT (1 << 0)
279 #define CNT_POOL_TYPE_AGE (1 << 1)
280 #define IS_EXT_POOL(pool) (((pool)->type) & CNT_POOL_TYPE_EXT)
281 #define IS_AGE_POOL(pool) (((pool)->type) & CNT_POOL_TYPE_AGE)
282 #define MLX_CNT_IS_AGE(counter) ((counter) & MLX5_CNT_AGE_OFFSET ? 1 : 0)
283 #define MLX5_CNT_LEN(pool) \
285 (IS_AGE_POOL(pool) ? AGE_SIZE : 0) + \
286 (IS_EXT_POOL(pool) ? CNTEXT_SIZE : 0))
287 #define MLX5_POOL_GET_CNT(pool, index) \
288 ((struct mlx5_flow_counter *) \
289 ((uint8_t *)((pool) + 1) + (index) * (MLX5_CNT_LEN(pool))))
290 #define MLX5_CNT_ARRAY_IDX(pool, cnt) \
291 ((int)(((uint8_t *)(cnt) - (uint8_t *)((pool) + 1)) / \
294 * The pool index and offset of counter in the pool array makes up the
295 * counter index. In case the counter is from pool 0 and offset 0, it
296 * should plus 1 to avoid index 0, since 0 means invalid counter index
299 #define MLX5_MAKE_CNT_IDX(pi, offset) \
300 ((pi) * MLX5_COUNTERS_PER_POOL + (offset) + 1)
301 #define MLX5_CNT_TO_CNT_EXT(pool, cnt) \
302 ((struct mlx5_flow_counter_ext *)\
303 ((uint8_t *)((cnt) + 1) + \
304 (IS_AGE_POOL(pool) ? AGE_SIZE : 0)))
305 #define MLX5_GET_POOL_CNT_EXT(pool, offset) \
306 MLX5_CNT_TO_CNT_EXT(pool, MLX5_POOL_GET_CNT((pool), (offset)))
307 #define MLX5_CNT_TO_AGE(cnt) \
308 ((struct mlx5_age_param *)((cnt) + 1))
310 * The maximum single counter is 0x800000 as MLX5_CNT_BATCH_OFFSET
311 * defines. The pool size is 512, pool index should never reach
314 #define POOL_IDX_INVALID UINT16_MAX
316 struct mlx5_flow_counter_pool;
320 AGE_FREE, /* Initialized state. */
321 AGE_CANDIDATE, /* Counter assigned to flows. */
322 AGE_TMOUT, /* Timeout, wait for rte_flow_get_aged_flows and destroy. */
325 #define MLX5_CNT_CONTAINER(sh, batch, age) (&(sh)->cmng.ccont \
326 [(batch) * 2 + (age)])
329 MLX5_CCONT_TYPE_SINGLE,
330 MLX5_CCONT_TYPE_SINGLE_FOR_AGE,
331 MLX5_CCONT_TYPE_BATCH,
332 MLX5_CCONT_TYPE_BATCH_FOR_AGE,
336 /* Counter age parameter. */
337 struct mlx5_age_param {
338 rte_atomic16_t state; /**< Age state. */
339 uint16_t port_id; /**< Port id of the counter. */
340 uint32_t timeout:15; /**< Age timeout in unit of 0.1sec. */
341 uint32_t expire:16; /**< Expire time(0.1sec) in the future. */
342 void *context; /**< Flow counter age context. */
345 struct flow_counter_stats {
350 struct mlx5_flow_counter_pool;
351 /* Generic counters information. */
352 struct mlx5_flow_counter {
353 TAILQ_ENTRY(mlx5_flow_counter) next;
354 /**< Pointer to the next flow counter structure. */
356 uint64_t hits; /**< Reset value of hits packets. */
357 struct mlx5_flow_counter_pool *pool; /**< Counter pool. */
359 uint64_t bytes; /**< Reset value of bytes. */
360 void *action; /**< Pointer to the dv action. */
363 /* Extend counters information for none batch counters. */
364 struct mlx5_flow_counter_ext {
365 uint32_t shared:1; /**< Share counter ID with other flow rules. */
367 uint32_t skipped:1; /* This counter is skipped or not. */
368 /**< Whether the counter was allocated by batch command. */
369 uint32_t ref_cnt:29; /**< Reference counter. */
370 uint32_t id; /**< User counter ID. */
371 union { /**< Holds the counters for the rule. */
372 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42)
373 struct ibv_counter_set *cs;
374 #elif defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
375 struct ibv_counters *cs;
377 struct mlx5_devx_obj *dcs; /**< Counter Devx object. */
381 TAILQ_HEAD(mlx5_counters, mlx5_flow_counter);
383 /* Generic counter pool structure - query is in pool resolution. */
384 struct mlx5_flow_counter_pool {
385 TAILQ_ENTRY(mlx5_flow_counter_pool) next;
386 struct mlx5_counters counters[2]; /* Free counter list. */
388 struct mlx5_devx_obj *min_dcs;
389 rte_atomic64_t a64_dcs;
391 /* The devx object of the minimum counter ID. */
392 uint32_t index:28; /* Pool index in container. */
393 uint32_t type:2; /* Memory type behind the counter array. */
394 uint32_t skip_cnt:1; /* Pool contains skipped counter. */
395 volatile uint32_t query_gen:1; /* Query round. */
396 rte_spinlock_t sl; /* The pool lock. */
397 struct mlx5_counter_stats_raw *raw;
398 struct mlx5_counter_stats_raw *raw_hw; /* The raw on HW working. */
401 struct mlx5_counter_stats_raw;
403 /* Memory management structure for group of counter statistics raws. */
404 struct mlx5_counter_stats_mem_mng {
405 LIST_ENTRY(mlx5_counter_stats_mem_mng) next;
406 struct mlx5_counter_stats_raw *raws;
407 struct mlx5_devx_obj *dm;
411 /* Raw memory structure for the counter statistics values of a pool. */
412 struct mlx5_counter_stats_raw {
413 LIST_ENTRY(mlx5_counter_stats_raw) next;
415 struct mlx5_counter_stats_mem_mng *mem_mng;
416 volatile struct flow_counter_stats *data;
419 TAILQ_HEAD(mlx5_counter_pools, mlx5_flow_counter_pool);
421 /* Container structure for counter pools. */
422 struct mlx5_pools_container {
423 rte_atomic16_t n_valid; /* Number of valid pools. */
424 uint16_t n; /* Number of pools. */
425 uint16_t last_pool_idx; /* Last used pool index */
426 int min_id; /* The minimum counter ID in the pools. */
427 int max_id; /* The maximum counter ID in the pools. */
428 rte_spinlock_t resize_sl; /* The resize lock. */
429 rte_spinlock_t csl; /* The counter free list lock. */
430 struct mlx5_counters counters; /* Free counter list. */
431 struct mlx5_counter_pools pool_list; /* Counter pool list. */
432 struct mlx5_flow_counter_pool **pools; /* Counter pool array. */
433 struct mlx5_counter_stats_mem_mng *mem_mng;
434 /* Hold the memory management for the next allocated pools raws. */
437 /* Counter global management structure. */
438 struct mlx5_flow_counter_mng {
439 struct mlx5_pools_container ccont[MLX5_CCONT_TYPE_MAX];
440 struct mlx5_counters flow_counters; /* Legacy flow counter list. */
441 uint8_t pending_queries;
445 uint8_t query_thread_on;
446 LIST_HEAD(mem_mngs, mlx5_counter_stats_mem_mng) mem_mngs;
447 LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws;
450 /* Default miss action resource structure. */
451 struct mlx5_flow_default_miss_resource {
452 void *action; /* Pointer to the rdma-core action. */
453 rte_atomic32_t refcnt; /* Default miss action reference counter. */
456 #define MLX5_AGE_EVENT_NEW 1
457 #define MLX5_AGE_TRIGGER 2
458 #define MLX5_AGE_SET(age_info, BIT) \
459 ((age_info)->flags |= (1 << (BIT)))
460 #define MLX5_AGE_GET(age_info, BIT) \
461 ((age_info)->flags & (1 << (BIT)))
462 #define GET_PORT_AGE_INFO(priv) \
463 (&((priv)->sh->port[(priv)->dev_port - 1].age_info))
465 /* Aging information for per port. */
466 struct mlx5_age_info {
467 uint8_t flags; /*Indicate if is new event or need be trigered*/
468 struct mlx5_counters aged_counters; /* Aged flow counter list. */
469 rte_spinlock_t aged_sl; /* Aged flow counter list lock. */
472 /* Per port data of shared IB device. */
473 struct mlx5_dev_shared_port {
475 uint32_t devx_ih_port_id;
477 * Interrupt handler port_id. Used by shared interrupt
478 * handler to find the corresponding rte_eth device
479 * by IB port index. If value is equal or greater
480 * RTE_MAX_ETHPORTS it means there is no subhandler
481 * installed for specified IB port index.
483 struct mlx5_age_info age_info;
484 /* Aging information for per port. */
487 /* Table key of the hash organization. */
488 union mlx5_flow_tbl_key {
490 /* Table ID should be at the lowest address. */
491 uint32_t table_id; /**< ID of the table. */
492 uint16_t reserved; /**< must be zero for comparison. */
493 uint8_t domain; /**< 1 - FDB, 0 - NIC TX/RX. */
494 uint8_t direction; /**< 1 - egress, 0 - ingress. */
496 uint64_t v64; /**< full 64bits value of key */
499 /* Table structure. */
500 struct mlx5_flow_tbl_resource {
501 void *obj; /**< Pointer to DR table object. */
502 rte_atomic32_t refcnt; /**< Reference counter. */
505 #define MLX5_MAX_TABLES UINT16_MAX
506 #define MLX5_FLOW_TABLE_LEVEL_METER (UINT16_MAX - 3)
507 #define MLX5_FLOW_TABLE_LEVEL_SUFFIX (UINT16_MAX - 2)
508 #define MLX5_HAIRPIN_TX_TABLE (UINT16_MAX - 1)
509 /* Reserve the last two tables for metadata register copy. */
510 #define MLX5_FLOW_MREG_ACT_TABLE_GROUP (MLX5_MAX_TABLES - 1)
511 #define MLX5_FLOW_MREG_CP_TABLE_GROUP (MLX5_MAX_TABLES - 2)
512 /* Tables for metering splits should be added here. */
513 #define MLX5_MAX_TABLES_EXTERNAL (MLX5_MAX_TABLES - 3)
514 #define MLX5_MAX_TABLES_FDB UINT16_MAX
516 /* ID generation structure. */
517 struct mlx5_flow_id_pool {
518 uint32_t *free_arr; /**< Pointer to the a array of free values. */
520 /**< The next index that can be used without any free elements. */
521 uint32_t *curr; /**< Pointer to the index to pop. */
522 uint32_t *last; /**< Pointer to the last element in the empty arrray. */
523 uint32_t max_id; /**< Maximum id can be allocated from the pool. */
526 /* Tx pacing queue structure - for Clock and Rearm queues. */
527 struct mlx5_txpp_wq {
528 /* Completion Queue related data.*/
529 struct mlx5_devx_obj *cq;
532 volatile void *cq_buf;
533 volatile struct mlx5_cqe *cqes;
535 volatile uint32_t *cq_dbrec;
538 /* Send Queue related data.*/
539 struct mlx5_devx_obj *sq;
542 volatile void *sq_buf;
543 volatile struct mlx5_wqe *wqes;
545 uint16_t sq_size; /* Number of WQEs in the queue. */
546 uint16_t sq_ci; /* Next WQE to execute. */
547 volatile uint32_t *sq_dbrec;
550 /* Tx packet pacing internal timestamp. */
551 struct mlx5_txpp_ts {
552 rte_atomic64_t ci_ts;
556 /* Tx packet pacing structure. */
557 struct mlx5_dev_txpp {
558 pthread_mutex_t mutex; /* Pacing create/destroy mutex. */
559 uint32_t refcnt; /* Pacing reference counter. */
560 uint32_t freq; /* Timestamp frequency, Hz. */
561 uint32_t tick; /* Completion tick duration in nanoseconds. */
562 uint32_t test; /* Packet pacing test mode. */
563 int32_t skew; /* Scheduling skew. */
564 uint32_t eqn; /* Event Queue number. */
565 struct rte_intr_handle intr_handle; /* Periodic interrupt. */
566 void *echan; /* Event Channel. */
567 struct mlx5_txpp_wq clock_queue; /* Clock Queue. */
568 struct mlx5_txpp_wq rearm_queue; /* Clock Queue. */
569 void *pp; /* Packet pacing context. */
570 uint16_t pp_id; /* Packet pacing context index. */
571 uint16_t ts_n; /* Number of captured timestamps. */
572 uint16_t ts_p; /* Pointer to statisticks timestamp. */
573 struct mlx5_txpp_ts *tsa; /* Timestamps sliding window stats. */
574 struct mlx5_txpp_ts ts; /* Cached completion id/timestamp. */
575 uint32_t sync_lost:1; /* ci/timestamp synchronization lost. */
576 /* Statistics counters. */
577 rte_atomic32_t err_miss_int; /* Missed service interrupt. */
578 rte_atomic32_t err_rearm_queue; /* Rearm Queue errors. */
579 rte_atomic32_t err_clock_queue; /* Clock Queue errors. */
580 rte_atomic32_t err_ts_past; /* Timestamp in the past. */
581 rte_atomic32_t err_ts_future; /* Timestamp in the distant future. */
584 /* Supported flex parser profile ID. */
585 enum mlx5_flex_parser_profile_id {
586 MLX5_FLEX_PARSER_ECPRI_0 = 0,
587 MLX5_FLEX_PARSER_MAX = 8,
590 /* Sample ID information of flex parser structure. */
591 struct mlx5_flex_parser_profiles {
592 uint32_t num; /* Actual number of samples. */
593 uint32_t ids[8]; /* Sample IDs for this profile. */
594 uint8_t offset[8]; /* Bytes offset of each parser. */
595 void *obj; /* Flex parser node object. */
599 * Shared Infiniband device context for Master/Representors
600 * which belong to same IB device with multiple IB ports.
602 struct mlx5_dev_ctx_shared {
603 LIST_ENTRY(mlx5_dev_ctx_shared) next;
605 uint32_t devx:1; /* Opened with DV. */
606 uint32_t max_port; /* Maximal IB device port index. */
607 void *ctx; /* Verbs/DV/DevX context. */
608 void *pd; /* Protection Domain. */
609 uint32_t pdn; /* Protection Domain number. */
610 uint32_t tdn; /* Transport Domain number. */
611 char ibdev_name[DEV_SYSFS_NAME_MAX]; /* SYSFS dev name. */
612 char ibdev_path[DEV_SYSFS_PATH_MAX]; /* SYSFS dev path for secondary */
613 struct mlx5_dev_attr device_attr; /* Device properties. */
614 int numa_node; /* Numa node of backing physical device. */
615 LIST_ENTRY(mlx5_dev_ctx_shared) mem_event_cb;
616 /**< Called by memory event callback. */
617 struct mlx5_mr_share_cache share_cache;
618 /* Packet pacing related structure. */
619 struct mlx5_dev_txpp txpp;
620 /* Shared DV/DR flow data section. */
621 pthread_mutex_t dv_mutex; /* DV context mutex. */
622 uint32_t dv_meta_mask; /* flow META metadata supported mask. */
623 uint32_t dv_mark_mask; /* flow MARK metadata supported mask. */
624 uint32_t dv_regc0_mask; /* available bits of metatada reg_c[0]. */
625 uint32_t dv_refcnt; /* DV/DR data reference counter. */
626 void *fdb_domain; /* FDB Direct Rules name space handle. */
627 void *rx_domain; /* RX Direct Rules name space handle. */
628 void *tx_domain; /* TX Direct Rules name space handle. */
630 rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */
631 rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX];
632 /* UAR same-page access control required in 32bit implementations. */
634 struct mlx5_hlist *flow_tbls;
635 /* Direct Rules tables for FDB, NIC TX+RX */
636 void *esw_drop_action; /* Pointer to DR E-Switch drop action. */
637 void *pop_vlan_action; /* Pointer to DR pop VLAN action. */
638 uint32_t encaps_decaps; /* Encap/decap action indexed memory list. */
639 struct mlx5_hlist *modify_cmds;
640 struct mlx5_hlist *tag_table;
641 uint32_t port_id_action_list; /* List of port ID actions. */
642 uint32_t push_vlan_action_list; /* List of push VLAN actions. */
643 struct mlx5_flow_counter_mng cmng; /* Counters management structure. */
644 struct mlx5_flow_default_miss_resource default_miss;
645 /* Default miss action resource structure. */
646 struct mlx5_indexed_pool *ipool[MLX5_IPOOL_MAX];
647 /* Memory Pool for mlx5 flow resources. */
648 struct mlx5_l3t_tbl *cnt_id_tbl; /* Shared counter lookup table. */
649 /* Shared interrupt handler section. */
650 struct rte_intr_handle intr_handle; /* Interrupt handler for device. */
651 struct rte_intr_handle intr_handle_devx; /* DEVX interrupt handler. */
652 void *devx_comp; /* DEVX async comp obj. */
653 struct mlx5_devx_obj *tis; /* TIS object. */
654 struct mlx5_devx_obj *td; /* Transport domain. */
655 struct mlx5_flow_id_pool *flow_id_pool; /* Flow ID pool. */
656 void *tx_uar; /* Tx/packet pacing shared UAR. */
657 struct mlx5_flex_parser_profiles fp[MLX5_FLEX_PARSER_MAX];
658 /* Flex parser profiles information. */
659 void *devx_rx_uar; /* DevX UAR for Rx. */
660 struct mlx5_dev_shared_port port[]; /* per device port data array. */
663 /* Per-process private structure. */
664 struct mlx5_proc_priv {
666 /* Size of UAR register table. */
668 /* Table of UAR registers for each process. */
671 /* MTR profile list. */
672 TAILQ_HEAD(mlx5_mtr_profiles, mlx5_flow_meter_profile);
674 TAILQ_HEAD(mlx5_flow_meters, mlx5_flow_meter);
676 #define MLX5_PROC_PRIV(port_id) \
677 ((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private)
679 enum mlx5_rxq_obj_type {
680 MLX5_RXQ_OBJ_TYPE_IBV, /* mlx5_rxq_obj with ibv_wq. */
681 MLX5_RXQ_OBJ_TYPE_DEVX_RQ, /* mlx5_rxq_obj with mlx5_devx_rq. */
682 MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN,
683 /* mlx5_rxq_obj with mlx5_devx_rq and hairpin support. */
686 /* Verbs/DevX Rx queue elements. */
687 struct mlx5_rxq_obj {
688 LIST_ENTRY(mlx5_rxq_obj) next; /* Pointer to the next element. */
689 struct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */
690 enum mlx5_rxq_obj_type type;
691 int fd; /* File descriptor for event channel */
695 void *wq; /* Work Queue. */
696 void *ibv_cq; /* Completion Queue. */
700 struct mlx5_devx_obj *rq; /* DevX Rx Queue object. */
701 struct mlx5_devx_obj *devx_cq; /* DevX CQ object. */
707 /* Indirection table. */
708 struct mlx5_ind_table_obj {
709 LIST_ENTRY(mlx5_ind_table_obj) next; /* Pointer to the next element. */
710 rte_atomic32_t refcnt; /* Reference counter. */
713 void *ind_table; /**< Indirection table. */
714 struct mlx5_devx_obj *rqt; /* DevX RQT object. */
716 uint32_t queues_n; /**< Number of queues in the list. */
717 uint16_t queues[]; /**< Queue list. */
722 ILIST_ENTRY(uint32_t)next; /* Index to the next element. */
723 rte_atomic32_t refcnt; /* Reference counter. */
724 struct mlx5_ind_table_obj *ind_table; /* Indirection table. */
727 void *qp; /* Verbs queue pair. */
728 struct mlx5_devx_obj *tir; /* DevX TIR object. */
730 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
731 void *action; /* DV QP action pointer. */
733 uint64_t hash_fields; /* Verbs Hash fields. */
734 uint32_t rss_key_len; /* Hash key length in bytes. */
735 uint8_t rss_key[]; /* Hash key. */
738 /* HW objects operations structure. */
739 struct mlx5_obj_ops {
740 int (*rxq_obj_modify_vlan_strip)(struct mlx5_rxq_obj *rxq_obj, int on);
741 int (*rxq_obj_new)(struct rte_eth_dev *dev, uint16_t idx);
742 int (*rxq_event_get)(struct mlx5_rxq_obj *rxq_obj);
743 int (*rxq_obj_modify)(struct mlx5_rxq_obj *rxq_obj, bool is_start);
744 void (*rxq_obj_release)(struct mlx5_rxq_obj *rxq_obj);
745 int (*ind_table_new)(struct rte_eth_dev *dev, const unsigned int log_n,
746 struct mlx5_ind_table_obj *ind_tbl);
747 void (*ind_table_destroy)(struct mlx5_ind_table_obj *ind_tbl);
748 int (*hrxq_new)(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq,
749 int tunnel __rte_unused);
750 void (*hrxq_destroy)(struct mlx5_hrxq *hrxq);
751 int (*drop_action_create)(struct rte_eth_dev *dev);
752 void (*drop_action_destroy)(struct rte_eth_dev *dev);
756 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */
757 struct mlx5_dev_ctx_shared *sh; /* Shared device context. */
758 uint32_t dev_port; /* Device port number. */
759 struct rte_pci_device *pci_dev; /* Backend PCI device. */
760 struct rte_ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */
761 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES);
762 /* Bit-field of MAC addresses owned by the PMD. */
763 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */
764 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */
765 /* Device properties. */
766 uint16_t mtu; /* Configured MTU. */
767 unsigned int isolated:1; /* Whether isolated mode is enabled. */
768 unsigned int representor:1; /* Device is a port representor. */
769 unsigned int master:1; /* Device is a E-Switch master. */
770 unsigned int dr_shared:1; /* DV/DR data is shared. */
771 unsigned int txpp_en:1; /* Tx packet pacing enabled. */
772 unsigned int counter_fallback:1; /* Use counter fallback management. */
773 unsigned int mtr_en:1; /* Whether support meter. */
774 unsigned int mtr_reg_share:1; /* Whether support meter REG_C share. */
775 uint16_t domain_id; /* Switch domain identifier. */
776 uint16_t vport_id; /* Associated VF vport index (if any). */
777 uint32_t vport_meta_tag; /* Used for vport index match ove VF LAG. */
778 uint32_t vport_meta_mask; /* Used for vport index field match mask. */
779 int32_t representor_id; /* Port representor identifier. */
780 int32_t pf_bond; /* >=0 means PF index in bonding configuration. */
781 unsigned int if_index; /* Associated kernel network device index. */
783 unsigned int rxqs_n; /* RX queues array size. */
784 unsigned int txqs_n; /* TX queues array size. */
785 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */
786 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */
787 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
788 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */
789 unsigned int (*reta_idx)[]; /* RETA index table. */
790 unsigned int reta_idx_n; /* RETA index size. */
791 struct mlx5_drop drop_queue; /* Flow drop queues. */
792 uint32_t flows; /* RTE Flow rules. */
793 uint32_t ctrl_flows; /* Control flow rules. */
794 void *inter_flows; /* Intermediate resources for flow creation. */
795 void *rss_desc; /* Intermediate rss description resources. */
796 int flow_idx; /* Intermediate device flow index. */
797 int flow_nested_idx; /* Intermediate device flow index, nested. */
798 struct mlx5_obj_ops obj_ops; /* HW objects operations. */
799 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */
800 LIST_HEAD(rxqobj, mlx5_rxq_obj) rxqsobj; /* Verbs/DevX Rx queues. */
801 uint32_t hrxqs; /* Verbs Hash Rx queues. */
802 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */
803 LIST_HEAD(txqobj, mlx5_txq_obj) txqsobj; /* Verbs/DevX Tx queues. */
804 /* Indirection tables. */
805 LIST_HEAD(ind_tables, mlx5_ind_table_obj) ind_tbls;
806 /* Pointer to next element. */
807 rte_atomic32_t refcnt; /**< Reference counter. */
808 /**< Verbs modify header action object. */
809 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
810 uint8_t max_lro_msg_size;
811 /* Tags resources cache. */
812 uint32_t link_speed_capa; /* Link speed capabilities. */
813 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */
814 struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */
815 struct mlx5_dev_config config; /* Device configuration. */
816 struct mlx5_verbs_alloc_ctx verbs_alloc_ctx;
817 /* Context for Verbs allocator. */
818 int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */
819 int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */
820 struct mlx5_dbr_page_list dbrpgs; /* Door-bell pages. */
821 struct mlx5_nl_vlan_vmwa_context *vmwa_context; /* VLAN WA context. */
822 struct mlx5_flow_id_pool *qrss_id_pool;
823 struct mlx5_hlist *mreg_cp_tbl;
824 /* Hash table of Rx metadata register copy table. */
825 uint8_t mtr_sfx_reg; /* Meter prefix-suffix flow match REG_C. */
826 uint8_t mtr_color_reg; /* Meter color match REG_C. */
827 struct mlx5_mtr_profiles flow_meter_profiles; /* MTR profile list. */
828 struct mlx5_flow_meters flow_meters; /* MTR list. */
829 uint8_t skip_default_rss_reta; /* Skip configuration of default reta. */
830 uint8_t fdb_def_rule; /* Whether fdb jump to table 1 is configured. */
831 struct mlx5_mp_id mp_id; /* ID of a multi-process process */
832 LIST_HEAD(fdir, mlx5_fdir_flow) fdir_flows; /* fdir flows. */
835 #define PORT_ID(priv) ((priv)->dev_data->port_id)
836 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)])
840 int mlx5_getenv_int(const char *);
841 int mlx5_proc_priv_init(struct rte_eth_dev *dev);
842 int mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev,
843 struct rte_eth_udp_tunnel *udp_tunnel);
844 uint16_t mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev);
845 void mlx5_dev_close(struct rte_eth_dev *dev);
847 /* Macro to iterate over all valid ports for mlx5 driver. */
848 #define MLX5_ETH_FOREACH_DEV(port_id, pci_dev) \
849 for (port_id = mlx5_eth_find_next(0, pci_dev); \
850 port_id < RTE_MAX_ETHPORTS; \
851 port_id = mlx5_eth_find_next(port_id + 1, pci_dev))
852 int mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs);
853 struct mlx5_dev_ctx_shared *
854 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
855 const struct mlx5_dev_config *config);
856 void mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh);
857 void mlx5_free_table_hash_list(struct mlx5_priv *priv);
858 int mlx5_alloc_table_hash_list(struct mlx5_priv *priv);
859 void mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
860 struct mlx5_dev_config *config);
861 void mlx5_set_metadata_mask(struct rte_eth_dev *dev);
862 int mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
863 struct mlx5_dev_config *config);
864 int mlx5_dev_configure(struct rte_eth_dev *dev);
865 int mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info);
866 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size);
867 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
868 int mlx5_hairpin_cap_get(struct rte_eth_dev *dev,
869 struct rte_eth_hairpin_cap *cap);
870 bool mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev);
871 int mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev);
875 int mlx5_dev_configure(struct rte_eth_dev *dev);
876 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver,
878 int mlx5_dev_infos_get(struct rte_eth_dev *dev,
879 struct rte_eth_dev_info *info);
880 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev);
881 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
882 int mlx5_hairpin_cap_get(struct rte_eth_dev *dev,
883 struct rte_eth_hairpin_cap *cap);
884 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev);
885 struct mlx5_priv *mlx5_port_to_eswitch_info(uint16_t port, bool valid);
886 struct mlx5_priv *mlx5_dev_to_eswitch_info(struct rte_eth_dev *dev);
887 int mlx5_dev_configure_rss_reta(struct rte_eth_dev *dev);
889 /* mlx5_ethdev_os.c */
891 unsigned int mlx5_ifindex(const struct rte_eth_dev *dev);
892 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]);
893 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu);
894 int mlx5_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
895 int mlx5_read_clock(struct rte_eth_dev *dev, uint64_t *clock);
896 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete);
897 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev,
898 struct rte_eth_fc_conf *fc_conf);
899 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev,
900 struct rte_eth_fc_conf *fc_conf);
901 void mlx5_dev_interrupt_handler(void *arg);
902 void mlx5_dev_interrupt_handler_devx(void *arg);
903 int mlx5_set_link_down(struct rte_eth_dev *dev);
904 int mlx5_set_link_up(struct rte_eth_dev *dev);
905 int mlx5_is_removed(struct rte_eth_dev *dev);
906 int mlx5_sysfs_switch_info(unsigned int ifindex,
907 struct mlx5_switch_info *info);
908 void mlx5_translate_port_name(const char *port_name_in,
909 struct mlx5_switch_info *port_info_out);
910 void mlx5_intr_callback_unregister(const struct rte_intr_handle *handle,
911 rte_intr_callback_fn cb_fn, void *cb_arg);
912 int mlx5_get_module_info(struct rte_eth_dev *dev,
913 struct rte_eth_dev_module_info *modinfo);
914 int mlx5_get_module_eeprom(struct rte_eth_dev *dev,
915 struct rte_dev_eeprom_info *info);
916 int mlx5_os_read_dev_stat(struct mlx5_priv *priv,
917 const char *ctr_name, uint64_t *stat);
918 int mlx5_os_read_dev_counters(struct rte_eth_dev *dev, uint64_t *stats);
919 int mlx5_os_get_stats_n(struct rte_eth_dev *dev);
920 void mlx5_os_stats_init(struct rte_eth_dev *dev);
924 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
925 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
926 uint32_t index, uint32_t vmdq);
927 int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr);
928 int mlx5_set_mc_addr_list(struct rte_eth_dev *dev,
929 struct rte_ether_addr *mc_addr_set,
930 uint32_t nb_mc_addr);
934 int mlx5_rss_hash_update(struct rte_eth_dev *dev,
935 struct rte_eth_rss_conf *rss_conf);
936 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev,
937 struct rte_eth_rss_conf *rss_conf);
938 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size);
939 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev,
940 struct rte_eth_rss_reta_entry64 *reta_conf,
942 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev,
943 struct rte_eth_rss_reta_entry64 *reta_conf,
948 int mlx5_promiscuous_enable(struct rte_eth_dev *dev);
949 int mlx5_promiscuous_disable(struct rte_eth_dev *dev);
950 int mlx5_allmulticast_enable(struct rte_eth_dev *dev);
951 int mlx5_allmulticast_disable(struct rte_eth_dev *dev);
955 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
956 int mlx5_stats_reset(struct rte_eth_dev *dev);
957 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats,
959 int mlx5_xstats_reset(struct rte_eth_dev *dev);
960 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
961 struct rte_eth_xstat_name *xstats_names,
966 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
967 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on);
968 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask);
972 void mlx5_vlan_vmwa_exit(void *ctx);
973 void mlx5_vlan_vmwa_release(struct rte_eth_dev *dev,
974 struct mlx5_vf_vlan *vf_vlan);
975 void mlx5_vlan_vmwa_acquire(struct rte_eth_dev *dev,
976 struct mlx5_vf_vlan *vf_vlan);
977 void *mlx5_vlan_vmwa_init(struct rte_eth_dev *dev, uint32_t ifindex);
981 int mlx5_dev_start(struct rte_eth_dev *dev);
982 void mlx5_dev_stop(struct rte_eth_dev *dev);
983 int mlx5_traffic_enable(struct rte_eth_dev *dev);
984 void mlx5_traffic_disable(struct rte_eth_dev *dev);
985 int mlx5_traffic_restart(struct rte_eth_dev *dev);
989 int mlx5_flow_discover_mreg_c(struct rte_eth_dev *eth_dev);
990 bool mlx5_flow_ext_mreg_supported(struct rte_eth_dev *dev);
991 void mlx5_flow_print(struct rte_flow *flow);
992 int mlx5_flow_validate(struct rte_eth_dev *dev,
993 const struct rte_flow_attr *attr,
994 const struct rte_flow_item items[],
995 const struct rte_flow_action actions[],
996 struct rte_flow_error *error);
997 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev,
998 const struct rte_flow_attr *attr,
999 const struct rte_flow_item items[],
1000 const struct rte_flow_action actions[],
1001 struct rte_flow_error *error);
1002 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow,
1003 struct rte_flow_error *error);
1004 void mlx5_flow_list_flush(struct rte_eth_dev *dev, uint32_t *list, bool active);
1005 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error);
1006 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow,
1007 const struct rte_flow_action *action, void *data,
1008 struct rte_flow_error *error);
1009 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable,
1010 struct rte_flow_error *error);
1011 int mlx5_dev_filter_ctrl(struct rte_eth_dev *dev,
1012 enum rte_filter_type filter_type,
1013 enum rte_filter_op filter_op,
1015 int mlx5_flow_start(struct rte_eth_dev *dev, uint32_t *list);
1016 void mlx5_flow_stop(struct rte_eth_dev *dev, uint32_t *list);
1017 int mlx5_flow_start_default(struct rte_eth_dev *dev);
1018 void mlx5_flow_stop_default(struct rte_eth_dev *dev);
1019 void mlx5_flow_alloc_intermediate(struct rte_eth_dev *dev);
1020 void mlx5_flow_free_intermediate(struct rte_eth_dev *dev);
1021 int mlx5_flow_verify(struct rte_eth_dev *dev);
1022 int mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, uint32_t queue);
1023 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev,
1024 struct rte_flow_item_eth *eth_spec,
1025 struct rte_flow_item_eth *eth_mask,
1026 struct rte_flow_item_vlan *vlan_spec,
1027 struct rte_flow_item_vlan *vlan_mask);
1028 int mlx5_ctrl_flow(struct rte_eth_dev *dev,
1029 struct rte_flow_item_eth *eth_spec,
1030 struct rte_flow_item_eth *eth_mask);
1031 int mlx5_flow_lacp_miss(struct rte_eth_dev *dev);
1032 struct rte_flow *mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev);
1033 int mlx5_flow_create_drop_queue(struct rte_eth_dev *dev);
1034 void mlx5_flow_delete_drop_queue(struct rte_eth_dev *dev);
1035 void mlx5_flow_async_pool_query_handle(struct mlx5_dev_ctx_shared *sh,
1036 uint64_t async_id, int status);
1037 void mlx5_set_query_alarm(struct mlx5_dev_ctx_shared *sh);
1038 void mlx5_flow_query_alarm(void *arg);
1039 uint32_t mlx5_counter_alloc(struct rte_eth_dev *dev);
1040 void mlx5_counter_free(struct rte_eth_dev *dev, uint32_t cnt);
1041 int mlx5_counter_query(struct rte_eth_dev *dev, uint32_t cnt,
1042 bool clear, uint64_t *pkts, uint64_t *bytes);
1043 int mlx5_flow_dev_dump(struct rte_eth_dev *dev, FILE *file,
1044 struct rte_flow_error *error);
1045 void mlx5_flow_rxq_dynf_metadata_set(struct rte_eth_dev *dev);
1046 int mlx5_flow_get_aged_flows(struct rte_eth_dev *dev, void **contexts,
1047 uint32_t nb_contexts, struct rte_flow_error *error);
1051 int mlx5_mp_os_primary_handle(const struct rte_mp_msg *mp_msg,
1053 int mlx5_mp_os_secondary_handle(const struct rte_mp_msg *mp_msg,
1055 void mlx5_mp_os_req_start_rxtx(struct rte_eth_dev *dev);
1056 void mlx5_mp_os_req_stop_rxtx(struct rte_eth_dev *dev);
1057 int mlx5_mp_os_req_queue_control(struct rte_eth_dev *dev, uint16_t queue_id,
1058 enum mlx5_mp_req_type req_type);
1062 int mlx5_pmd_socket_init(void);
1064 /* mlx5_flow_meter.c */
1066 int mlx5_flow_meter_ops_get(struct rte_eth_dev *dev, void *arg);
1067 struct mlx5_flow_meter *mlx5_flow_meter_find(struct mlx5_priv *priv,
1069 struct mlx5_flow_meter *mlx5_flow_meter_attach
1070 (struct mlx5_priv *priv,
1072 const struct rte_flow_attr *attr,
1073 struct rte_flow_error *error);
1074 void mlx5_flow_meter_detach(struct mlx5_flow_meter *fm);
1077 struct rte_pci_driver;
1078 int mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *dev_attr);
1079 void mlx5_os_free_shared_dr(struct mlx5_priv *priv);
1080 int mlx5_os_open_device(const struct mlx5_dev_spawn_data *spawn,
1081 const struct mlx5_dev_config *config,
1082 struct mlx5_dev_ctx_shared *sh);
1083 int mlx5_os_get_pdn(void *pd, uint32_t *pdn);
1084 int mlx5_os_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1085 struct rte_pci_device *pci_dev);
1086 void mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh);
1087 void mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh);
1088 void mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb,
1089 mlx5_dereg_mr_t *dereg_mr_cb);
1090 void mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
1091 int mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
1093 int mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv, unsigned int iface_idx,
1094 struct rte_ether_addr *mac_addr,
1096 int mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable);
1097 int mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable);
1098 int mlx5_os_set_nonblock_channel_fd(int fd);
1099 void mlx5_os_mac_addr_flush(struct rte_eth_dev *dev);
1103 int mlx5_txpp_start(struct rte_eth_dev *dev);
1104 void mlx5_txpp_stop(struct rte_eth_dev *dev);
1105 int mlx5_txpp_read_clock(struct rte_eth_dev *dev, uint64_t *timestamp);
1106 int mlx5_txpp_xstats_get(struct rte_eth_dev *dev,
1107 struct rte_eth_xstat *stats,
1108 unsigned int n, unsigned int n_used);
1109 int mlx5_txpp_xstats_reset(struct rte_eth_dev *dev);
1110 int mlx5_txpp_xstats_get_names(struct rte_eth_dev *dev,
1111 struct rte_eth_xstat_name *xstats_names,
1112 unsigned int n, unsigned int n_used);
1113 void mlx5_txpp_interrupt_handler(void *cb_arg);
1117 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev);
1119 #endif /* RTE_PMD_MLX5_H_ */