1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_H_
7 #define RTE_PMD_MLX5_H_
14 #include <netinet/in.h>
15 #include <sys/queue.h>
18 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
20 #pragma GCC diagnostic ignored "-Wpedantic"
22 #include <infiniband/verbs.h>
24 #pragma GCC diagnostic error "-Wpedantic"
28 #include <rte_ether.h>
29 #include <rte_ethdev_driver.h>
30 #include <rte_rwlock.h>
31 #include <rte_interrupts.h>
32 #include <rte_errno.h>
35 #include <mlx5_glue.h>
36 #include <mlx5_devx_cmds.h>
39 #include "mlx5_defs.h"
40 #include "mlx5_utils.h"
42 #include "mlx5_autoconf.h"
45 PCI_VENDOR_ID_MELLANOX = 0x15b3,
49 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013,
50 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014,
51 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015,
52 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016,
53 PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017,
54 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018,
55 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019,
56 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a,
57 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF = 0xa2d2,
58 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF = 0xa2d3,
59 PCI_DEVICE_ID_MELLANOX_CONNECTX6 = 0x101b,
60 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF = 0x101c,
61 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX = 0x101d,
62 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF = 0x101e,
65 /* Request types for IPC. */
66 enum mlx5_mp_req_type {
67 MLX5_MP_REQ_VERBS_CMD_FD = 1,
68 MLX5_MP_REQ_CREATE_MR,
69 MLX5_MP_REQ_START_RXTX,
70 MLX5_MP_REQ_STOP_RXTX,
71 MLX5_MP_REQ_QUEUE_STATE_MODIFY,
74 struct mlx5_mp_arg_queue_state_modify {
75 uint8_t is_wq; /* Set if WQ. */
76 uint16_t queue_id; /* DPDK queue ID. */
77 enum ibv_wq_state state; /* WQ requested state. */
80 /* Pameters for IPC. */
81 struct mlx5_mp_param {
82 enum mlx5_mp_req_type type;
87 uintptr_t addr; /* MLX5_MP_REQ_CREATE_MR */
88 struct mlx5_mp_arg_queue_state_modify state_modify;
89 /* MLX5_MP_REQ_QUEUE_STATE_MODIFY */
93 /** Request timeout for IPC. */
94 #define MLX5_MP_REQ_TIMEOUT_SEC 5
96 /** Key string for IPC. */
97 #define MLX5_MP_NAME "net_mlx5_mp"
99 /* Recognized Infiniband device physical port name types. */
100 enum mlx5_phys_port_name_type {
101 MLX5_PHYS_PORT_NAME_TYPE_NOTSET = 0, /* Not set. */
102 MLX5_PHYS_PORT_NAME_TYPE_LEGACY, /* before kernel ver < 5.0 */
103 MLX5_PHYS_PORT_NAME_TYPE_UPLINK, /* p0, kernel ver >= 5.0 */
104 MLX5_PHYS_PORT_NAME_TYPE_PFVF, /* pf0vf0, kernel ver >= 5.0 */
105 MLX5_PHYS_PORT_NAME_TYPE_UNKNOWN, /* Unrecognized. */
108 /** Switch information returned by mlx5_nl_switch_info(). */
109 struct mlx5_switch_info {
110 uint32_t master:1; /**< Master device. */
111 uint32_t representor:1; /**< Representor device. */
112 enum mlx5_phys_port_name_type name_type; /** < Port name type. */
113 int32_t pf_num; /**< PF number (valid for pfxvfx format only). */
114 int32_t port_name; /**< Representor port name. */
115 uint64_t switch_id; /**< Switch identifier. */
118 LIST_HEAD(mlx5_dev_list, mlx5_ibv_shared);
120 /* Shared data between primary and secondary processes. */
121 struct mlx5_shared_data {
123 /* Global spinlock for primary and secondary processes. */
124 int init_done; /* Whether primary has done initialization. */
125 unsigned int secondary_cnt; /* Number of secondary processes init'd. */
126 struct mlx5_dev_list mem_event_cb_list;
127 rte_rwlock_t mem_event_rwlock;
130 /* Per-process data structure, not visible to other processes. */
131 struct mlx5_local_data {
132 int init_done; /* Whether a secondary has done initialization. */
135 extern struct mlx5_shared_data *mlx5_shared_data;
137 struct mlx5_counter_ctrl {
138 /* Name of the counter. */
139 char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE];
140 /* Name of the counter on the device table. */
141 char ctr_name[RTE_ETH_XSTATS_NAME_SIZE];
142 uint32_t ib:1; /**< Nonzero for IB counters. */
145 struct mlx5_xstats_ctrl {
146 /* Number of device stats. */
148 /* Number of device stats identified by PMD. */
149 uint16_t mlx5_stats_n;
150 /* Index in the device counters table. */
151 uint16_t dev_table_idx[MLX5_MAX_XSTATS];
152 uint64_t base[MLX5_MAX_XSTATS];
153 struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS];
156 struct mlx5_stats_ctrl {
157 /* Base for imissed counter. */
158 uint64_t imissed_base;
162 TAILQ_HEAD(mlx5_flows, rte_flow);
164 /* Default PMD specific parameter value. */
165 #define MLX5_ARG_UNSET (-1)
167 #define MLX5_LRO_SUPPORTED(dev) \
168 (((struct mlx5_priv *)((dev)->data->dev_private))->config.lro.supported)
170 /* Maximal size of coalesced segment for LRO is set in chunks of 256 Bytes. */
171 #define MLX5_LRO_SEG_CHUNK_SIZE 256u
173 /* Maximal size of aggregated LRO packet. */
174 #define MLX5_MAX_LRO_SIZE (UINT8_MAX * MLX5_LRO_SEG_CHUNK_SIZE)
176 /* LRO configurations structure. */
177 struct mlx5_lro_config {
178 uint32_t supported:1; /* Whether LRO is supported. */
179 uint32_t timeout; /* User configuration. */
183 * Device configuration structure.
185 * Merged configuration from:
187 * - Device capabilities,
188 * - User device parameters disabled features.
190 struct mlx5_dev_config {
191 unsigned int hw_csum:1; /* Checksum offload is supported. */
192 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */
193 unsigned int hw_vlan_insert:1; /* VLAN insertion in WQE is supported. */
194 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */
195 unsigned int hw_padding:1; /* End alignment padding is supported. */
196 unsigned int vf:1; /* This is a VF. */
197 unsigned int tunnel_en:1;
198 /* Whether tunnel stateless offloads are supported. */
199 unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */
200 unsigned int cqe_comp:1; /* CQE compression is enabled. */
201 unsigned int cqe_pad:1; /* CQE padding is enabled. */
202 unsigned int tso:1; /* Whether TSO is supported. */
203 unsigned int rx_vec_en:1; /* Rx vector is enabled. */
204 unsigned int mr_ext_memseg_en:1;
205 /* Whether memseg should be extended for MR creation. */
206 unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */
207 unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */
208 unsigned int dv_esw_en:1; /* Enable E-Switch DV flow. */
209 unsigned int dv_flow_en:1; /* Enable DV flow. */
210 unsigned int dv_xmeta_en:2; /* Enable extensive flow metadata. */
211 unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */
212 unsigned int devx:1; /* Whether devx interface is available or not. */
213 unsigned int dest_tir:1; /* Whether advanced DR API is available. */
215 unsigned int enabled:1; /* Whether MPRQ is enabled. */
216 unsigned int stride_num_n; /* Number of strides. */
217 unsigned int min_stride_size_n; /* Min size of a stride. */
218 unsigned int max_stride_size_n; /* Max size of a stride. */
219 unsigned int max_memcpy_len;
220 /* Maximum packet size to memcpy Rx packets. */
221 unsigned int min_rxqs_num;
222 /* Rx queue count threshold to enable MPRQ. */
223 } mprq; /* Configurations for Multi-Packet RQ. */
224 int mps; /* Multi-packet send supported mode. */
225 int dbnc; /* Skip doorbell register write barrier. */
226 unsigned int flow_prio; /* Number of flow priorities. */
227 enum modify_reg flow_mreg_c[MLX5_MREG_C_NUM];
228 /* Availibility of mreg_c's. */
229 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */
230 unsigned int ind_table_max_size; /* Maximum indirection table size. */
231 unsigned int max_dump_files_num; /* Maximum dump files per queue. */
232 int txqs_inline; /* Queue number threshold for inlining. */
233 int txq_inline_min; /* Minimal amount of data bytes to inline. */
234 int txq_inline_max; /* Max packet size for inlining with SEND. */
235 int txq_inline_mpw; /* Max packet size for inlining with eMPW. */
236 struct mlx5_hca_attr hca_attr; /* HCA attributes. */
237 struct mlx5_lro_config lro; /* LRO configuration. */
242 * Type of object being allocated.
244 enum mlx5_verbs_alloc_type {
245 MLX5_VERBS_ALLOC_TYPE_NONE,
246 MLX5_VERBS_ALLOC_TYPE_TX_QUEUE,
247 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE,
250 /* VLAN netdev for VLAN workaround. */
251 struct mlx5_vlan_dev {
253 uint32_t ifindex; /**< Own interface index. */
256 /* Structure for VF VLAN workaround. */
257 struct mlx5_vf_vlan {
263 * Array of VLAN devices created on the base of VF
264 * used for workaround in virtual environments.
266 struct mlx5_vlan_vmwa_context {
270 struct rte_eth_dev *dev;
271 struct mlx5_vlan_dev vlan_dev[4096];
275 * Verbs allocator needs a context to know in the callback which kind of
276 * resources it is allocating.
278 struct mlx5_verbs_alloc_ctx {
279 enum mlx5_verbs_alloc_type type; /* Kind of object being allocated. */
280 const void *obj; /* Pointer to the DPDK object. */
283 LIST_HEAD(mlx5_mr_list, mlx5_mr);
285 /* Flow drop context necessary due to Verbs API. */
287 struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */
288 struct mlx5_rxq_obj *rxq; /* Rx queue object. */
291 #define MLX5_COUNTERS_PER_POOL 512
292 #define MLX5_MAX_PENDING_QUERIES 4
294 struct mlx5_flow_counter_pool;
296 struct flow_counter_stats {
301 /* Counters information. */
302 struct mlx5_flow_counter {
303 TAILQ_ENTRY(mlx5_flow_counter) next;
304 /**< Pointer to the next flow counter structure. */
305 uint32_t shared:1; /**< Share counter ID with other flow rules. */
307 /**< Whether the counter was allocated by batch command. */
308 uint32_t ref_cnt:30; /**< Reference counter. */
309 uint32_t id; /**< Counter ID. */
310 union { /**< Holds the counters for the rule. */
311 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42)
312 struct ibv_counter_set *cs;
313 #elif defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
314 struct ibv_counters *cs;
316 struct mlx5_devx_obj *dcs; /**< Counter Devx object. */
317 struct mlx5_flow_counter_pool *pool; /**< The counter pool. */
320 uint64_t hits; /**< Reset value of hits packets. */
321 int64_t query_gen; /**< Generation of the last release. */
323 uint64_t bytes; /**< Reset value of bytes. */
324 void *action; /**< Pointer to the dv action. */
327 TAILQ_HEAD(mlx5_counters, mlx5_flow_counter);
329 /* Counter pool structure - query is in pool resolution. */
330 struct mlx5_flow_counter_pool {
331 TAILQ_ENTRY(mlx5_flow_counter_pool) next;
332 struct mlx5_counters counters; /* Free counter list. */
334 struct mlx5_devx_obj *min_dcs;
335 rte_atomic64_t a64_dcs;
337 /* The devx object of the minimum counter ID. */
338 rte_atomic64_t query_gen;
339 uint32_t n_counters: 16; /* Number of devx allocated counters. */
340 rte_spinlock_t sl; /* The pool lock. */
341 struct mlx5_counter_stats_raw *raw;
342 struct mlx5_counter_stats_raw *raw_hw; /* The raw on HW working. */
343 struct mlx5_flow_counter counters_raw[]; /* The pool counters memory. */
346 struct mlx5_counter_stats_raw;
348 /* Memory management structure for group of counter statistics raws. */
349 struct mlx5_counter_stats_mem_mng {
350 LIST_ENTRY(mlx5_counter_stats_mem_mng) next;
351 struct mlx5_counter_stats_raw *raws;
352 struct mlx5_devx_obj *dm;
353 struct mlx5dv_devx_umem *umem;
356 /* Raw memory structure for the counter statistics values of a pool. */
357 struct mlx5_counter_stats_raw {
358 LIST_ENTRY(mlx5_counter_stats_raw) next;
360 struct mlx5_counter_stats_mem_mng *mem_mng;
361 volatile struct flow_counter_stats *data;
364 TAILQ_HEAD(mlx5_counter_pools, mlx5_flow_counter_pool);
366 /* Container structure for counter pools. */
367 struct mlx5_pools_container {
368 rte_atomic16_t n_valid; /* Number of valid pools. */
369 uint16_t n; /* Number of pools. */
370 struct mlx5_counter_pools pool_list; /* Counter pool list. */
371 struct mlx5_flow_counter_pool **pools; /* Counter pool array. */
372 struct mlx5_counter_stats_mem_mng *init_mem_mng;
373 /* Hold the memory management for the next allocated pools raws. */
376 /* Counter global management structure. */
377 struct mlx5_flow_counter_mng {
378 uint8_t mhi[2]; /* master \ host container index. */
379 struct mlx5_pools_container ccont[2 * 2];
380 /* 2 containers for single and for batch for double-buffer. */
381 struct mlx5_counters flow_counters; /* Legacy flow counter list. */
382 uint8_t pending_queries;
385 uint8_t query_thread_on;
386 LIST_HEAD(mem_mngs, mlx5_counter_stats_mem_mng) mem_mngs;
387 LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws;
390 /* Per port data of shared IB device. */
391 struct mlx5_ibv_shared_port {
393 uint32_t devx_ih_port_id;
395 * Interrupt handler port_id. Used by shared interrupt
396 * handler to find the corresponding rte_eth device
397 * by IB port index. If value is equal or greater
398 * RTE_MAX_ETHPORTS it means there is no subhandler
399 * installed for specified IB port index.
403 /* Table key of the hash organization. */
404 union mlx5_flow_tbl_key {
406 /* Table ID should be at the lowest address. */
407 uint32_t table_id; /**< ID of the table. */
408 uint16_t reserved; /**< must be zero for comparison. */
409 uint8_t domain; /**< 1 - FDB, 0 - NIC TX/RX. */
410 uint8_t direction; /**< 1 - egress, 0 - ingress. */
412 uint64_t v64; /**< full 64bits value of key */
415 /* Table structure. */
416 struct mlx5_flow_tbl_resource {
417 void *obj; /**< Pointer to DR table object. */
418 rte_atomic32_t refcnt; /**< Reference counter. */
421 #define MLX5_MAX_TABLES UINT16_MAX
422 #define MLX5_FLOW_TABLE_LEVEL_METER (UINT16_MAX - 3)
423 #define MLX5_FLOW_TABLE_LEVEL_SUFFIX (UINT16_MAX - 2)
424 #define MLX5_HAIRPIN_TX_TABLE (UINT16_MAX - 1)
425 /* Reserve the last two tables for metadata register copy. */
426 #define MLX5_FLOW_MREG_ACT_TABLE_GROUP (MLX5_MAX_TABLES - 1)
427 #define MLX5_FLOW_MREG_CP_TABLE_GROUP (MLX5_MAX_TABLES - 2)
428 /* Tables for metering splits should be added here. */
429 #define MLX5_MAX_TABLES_EXTERNAL (MLX5_MAX_TABLES - 3)
430 #define MLX5_MAX_TABLES_FDB UINT16_MAX
432 #define MLX5_DBR_PAGE_SIZE 4096 /* Must be >= 512. */
433 #define MLX5_DBR_SIZE 8
434 #define MLX5_DBR_PER_PAGE (MLX5_DBR_PAGE_SIZE / MLX5_DBR_SIZE)
435 #define MLX5_DBR_BITMAP_SIZE (MLX5_DBR_PER_PAGE / 64)
437 struct mlx5_devx_dbr_page {
438 /* Door-bell records, must be first member in structure. */
439 uint8_t dbrs[MLX5_DBR_PAGE_SIZE];
440 LIST_ENTRY(mlx5_devx_dbr_page) next; /* Pointer to the next element. */
441 struct mlx5dv_devx_umem *umem;
442 uint32_t dbr_count; /* Number of door-bell records in use. */
443 /* 1 bit marks matching door-bell is in use. */
444 uint64_t dbr_bitmap[MLX5_DBR_BITMAP_SIZE];
447 /* ID generation structure. */
448 struct mlx5_flow_id_pool {
449 uint32_t *free_arr; /**< Pointer to the a array of free values. */
451 /**< The next index that can be used without any free elements. */
452 uint32_t *curr; /**< Pointer to the index to pop. */
453 uint32_t *last; /**< Pointer to the last element in the empty arrray. */
454 uint32_t max_id; /**< Maximum id can be allocated from the pool. */
458 * Shared Infiniband device context for Master/Representors
459 * which belong to same IB device with multiple IB ports.
461 struct mlx5_ibv_shared {
462 LIST_ENTRY(mlx5_ibv_shared) next;
464 uint32_t devx:1; /* Opened with DV. */
465 uint32_t max_port; /* Maximal IB device port index. */
466 struct ibv_context *ctx; /* Verbs/DV context. */
467 struct ibv_pd *pd; /* Protection Domain. */
468 uint32_t pdn; /* Protection Domain number. */
469 uint32_t tdn; /* Transport Domain number. */
470 char ibdev_name[IBV_SYSFS_NAME_MAX]; /* IB device name. */
471 char ibdev_path[IBV_SYSFS_PATH_MAX]; /* IB device path for secondary */
472 struct ibv_device_attr_ex device_attr; /* Device properties. */
473 LIST_ENTRY(mlx5_ibv_shared) mem_event_cb;
474 /**< Called by memory event callback. */
476 uint32_t dev_gen; /* Generation number to flush local caches. */
477 rte_rwlock_t rwlock; /* MR Lock. */
478 struct mlx5_mr_btree cache; /* Global MR cache table. */
479 struct mlx5_mr_list mr_list; /* Registered MR list. */
480 struct mlx5_mr_list mr_free_list; /* Freed MR list. */
482 /* Shared DV/DR flow data section. */
483 pthread_mutex_t dv_mutex; /* DV context mutex. */
484 uint32_t dv_meta_mask; /* flow META metadata supported mask. */
485 uint32_t dv_mark_mask; /* flow MARK metadata supported mask. */
486 uint32_t dv_regc0_mask; /* available bits of metatada reg_c[0]. */
487 uint32_t dv_refcnt; /* DV/DR data reference counter. */
488 void *fdb_domain; /* FDB Direct Rules name space handle. */
489 struct mlx5_flow_tbl_resource *fdb_mtr_sfx_tbl;
490 /* FDB meter suffix rules table. */
491 void *rx_domain; /* RX Direct Rules name space handle. */
492 struct mlx5_flow_tbl_resource *rx_mtr_sfx_tbl;
493 /* RX meter suffix rules table. */
494 void *tx_domain; /* TX Direct Rules name space handle. */
495 struct mlx5_flow_tbl_resource *tx_mtr_sfx_tbl;
496 /* TX meter suffix rules table. */
497 struct mlx5_hlist *flow_tbls;
498 /* Direct Rules tables for FDB, NIC TX+RX */
499 void *esw_drop_action; /* Pointer to DR E-Switch drop action. */
500 void *pop_vlan_action; /* Pointer to DR pop VLAN action. */
501 LIST_HEAD(encap_decap, mlx5_flow_dv_encap_decap_resource) encaps_decaps;
502 LIST_HEAD(modify_cmd, mlx5_flow_dv_modify_hdr_resource) modify_cmds;
503 struct mlx5_hlist *tag_table;
504 LIST_HEAD(port_id_action_list, mlx5_flow_dv_port_id_action_resource)
505 port_id_action_list; /* List of port ID actions. */
506 LIST_HEAD(push_vlan_action_list, mlx5_flow_dv_push_vlan_action_resource)
507 push_vlan_action_list; /* List of push VLAN actions. */
508 struct mlx5_flow_counter_mng cmng; /* Counters management structure. */
509 /* Shared interrupt handler section. */
510 pthread_mutex_t intr_mutex; /* Interrupt config mutex. */
511 uint32_t intr_cnt; /* Interrupt handler reference counter. */
512 struct rte_intr_handle intr_handle; /* Interrupt handler for device. */
513 uint32_t devx_intr_cnt; /* Devx interrupt handler reference counter. */
514 struct rte_intr_handle intr_handle_devx; /* DEVX interrupt handler. */
515 struct mlx5dv_devx_cmd_comp *devx_comp; /* DEVX async comp obj. */
516 struct mlx5_devx_obj *tis; /* TIS object. */
517 struct mlx5_devx_obj *td; /* Transport domain. */
518 struct mlx5_flow_id_pool *flow_id_pool; /* Flow ID pool. */
519 struct mlx5_ibv_shared_port port[]; /* per device port data array. */
522 /* Per-process private structure. */
523 struct mlx5_proc_priv {
525 /* Size of UAR register table. */
527 /* Table of UAR registers for each process. */
530 /* MTR profile list. */
531 TAILQ_HEAD(mlx5_mtr_profiles, mlx5_flow_meter_profile);
533 TAILQ_HEAD(mlx5_flow_meters, mlx5_flow_meter);
535 #define MLX5_PROC_PRIV(port_id) \
536 ((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private)
539 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */
540 struct mlx5_ibv_shared *sh; /* Shared IB device context. */
541 uint32_t ibv_port; /* IB device port number. */
542 struct rte_pci_device *pci_dev; /* Backend PCI device. */
543 struct rte_ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */
544 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES);
545 /* Bit-field of MAC addresses owned by the PMD. */
546 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */
547 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */
548 /* Device properties. */
549 uint16_t mtu; /* Configured MTU. */
550 unsigned int isolated:1; /* Whether isolated mode is enabled. */
551 unsigned int representor:1; /* Device is a port representor. */
552 unsigned int master:1; /* Device is a E-Switch master. */
553 unsigned int dr_shared:1; /* DV/DR data is shared. */
554 unsigned int counter_fallback:1; /* Use counter fallback management. */
555 unsigned int mtr_en:1; /* Whether support meter. */
556 unsigned int mtr_reg_share:1; /* Whether support meter REG_C share. */
557 uint16_t domain_id; /* Switch domain identifier. */
558 uint16_t vport_id; /* Associated VF vport index (if any). */
559 uint32_t vport_meta_tag; /* Used for vport index match ove VF LAG. */
560 uint32_t vport_meta_mask; /* Used for vport index field match mask. */
561 int32_t representor_id; /* Port representor identifier. */
562 int32_t pf_bond; /* >=0 means PF index in bonding configuration. */
563 unsigned int if_index; /* Associated kernel network device index. */
565 unsigned int rxqs_n; /* RX queues array size. */
566 unsigned int txqs_n; /* TX queues array size. */
567 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */
568 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */
569 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
570 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */
571 unsigned int (*reta_idx)[]; /* RETA index table. */
572 unsigned int reta_idx_n; /* RETA index size. */
573 struct mlx5_drop drop_queue; /* Flow drop queues. */
574 struct mlx5_flows flows; /* RTE Flow rules. */
575 struct mlx5_flows ctrl_flows; /* Control flow rules. */
576 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */
577 LIST_HEAD(rxqobj, mlx5_rxq_obj) rxqsobj; /* Verbs/DevX Rx queues. */
578 LIST_HEAD(hrxq, mlx5_hrxq) hrxqs; /* Verbs Hash Rx queues. */
579 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */
580 LIST_HEAD(txqobj, mlx5_txq_obj) txqsobj; /* Verbs/DevX Tx queues. */
581 /* Indirection tables. */
582 LIST_HEAD(ind_tables, mlx5_ind_table_obj) ind_tbls;
583 /* Pointer to next element. */
584 rte_atomic32_t refcnt; /**< Reference counter. */
585 struct ibv_flow_action *verbs_action;
586 /**< Verbs modify header action object. */
587 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
588 uint8_t max_lro_msg_size;
589 /* Tags resources cache. */
590 uint32_t link_speed_capa; /* Link speed capabilities. */
591 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */
592 struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */
593 struct mlx5_dev_config config; /* Device configuration. */
594 struct mlx5_verbs_alloc_ctx verbs_alloc_ctx;
595 /* Context for Verbs allocator. */
596 int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */
597 int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */
598 uint32_t nl_sn; /* Netlink message sequence number. */
599 LIST_HEAD(dbrpage, mlx5_devx_dbr_page) dbrpgs; /* Door-bell pages. */
600 struct mlx5_vlan_vmwa_context *vmwa_context; /* VLAN WA context. */
601 struct mlx5_flow_id_pool *qrss_id_pool;
602 struct mlx5_hlist *mreg_cp_tbl;
603 /* Hash table of Rx metadata register copy table. */
604 uint8_t mtr_sfx_reg; /* Meter prefix-suffix flow match REG_C. */
605 uint8_t mtr_color_reg; /* Meter color match REG_C. */
606 struct mlx5_mtr_profiles flow_meter_profiles; /* MTR profile list. */
607 struct mlx5_flow_meters flow_meters; /* MTR list. */
609 rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */
610 rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX];
611 /* UAR same-page access control required in 32bit implementations. */
613 uint8_t skip_default_rss_reta; /* Skip configuration of default reta. */
616 #define PORT_ID(priv) ((priv)->dev_data->port_id)
617 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)])
621 int mlx5_getenv_int(const char *);
622 int mlx5_proc_priv_init(struct rte_eth_dev *dev);
623 int64_t mlx5_get_dbr(struct rte_eth_dev *dev,
624 struct mlx5_devx_dbr_page **dbr_page);
625 int32_t mlx5_release_dbr(struct rte_eth_dev *dev, uint32_t umem_id,
627 int mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev,
628 struct rte_eth_udp_tunnel *udp_tunnel);
629 uint16_t mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev);
631 /* Macro to iterate over all valid ports for mlx5 driver. */
632 #define MLX5_ETH_FOREACH_DEV(port_id, pci_dev) \
633 for (port_id = mlx5_eth_find_next(0, pci_dev); \
634 port_id < RTE_MAX_ETHPORTS; \
635 port_id = mlx5_eth_find_next(port_id + 1, pci_dev))
639 int mlx5_get_ifname(const struct rte_eth_dev *dev, char (*ifname)[IF_NAMESIZE]);
640 int mlx5_get_master_ifname(const char *ibdev_path, char (*ifname)[IF_NAMESIZE]);
641 unsigned int mlx5_ifindex(const struct rte_eth_dev *dev);
642 int mlx5_ifreq(const struct rte_eth_dev *dev, int req, struct ifreq *ifr);
643 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu);
644 int mlx5_set_flags(struct rte_eth_dev *dev, unsigned int keep,
646 int mlx5_dev_configure(struct rte_eth_dev *dev);
647 int mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info);
648 int mlx5_read_clock(struct rte_eth_dev *dev, uint64_t *clock);
649 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size);
650 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev);
651 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete);
652 int mlx5_force_link_status_change(struct rte_eth_dev *dev, int status);
653 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
654 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev,
655 struct rte_eth_fc_conf *fc_conf);
656 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev,
657 struct rte_eth_fc_conf *fc_conf);
658 int mlx5_dev_to_pci_addr(const char *dev_path,
659 struct rte_pci_addr *pci_addr);
660 void mlx5_dev_link_status_handler(void *arg);
661 void mlx5_dev_interrupt_handler(void *arg);
662 void mlx5_dev_interrupt_handler_devx(void *arg);
663 void mlx5_dev_interrupt_handler_uninstall(struct rte_eth_dev *dev);
664 void mlx5_dev_interrupt_handler_install(struct rte_eth_dev *dev);
665 void mlx5_dev_interrupt_handler_devx_uninstall(struct rte_eth_dev *dev);
666 void mlx5_dev_interrupt_handler_devx_install(struct rte_eth_dev *dev);
667 int mlx5_set_link_down(struct rte_eth_dev *dev);
668 int mlx5_set_link_up(struct rte_eth_dev *dev);
669 int mlx5_is_removed(struct rte_eth_dev *dev);
670 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev);
671 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev);
672 struct mlx5_priv *mlx5_port_to_eswitch_info(uint16_t port, bool valid);
673 struct mlx5_priv *mlx5_dev_to_eswitch_info(struct rte_eth_dev *dev);
674 int mlx5_sysfs_switch_info(unsigned int ifindex,
675 struct mlx5_switch_info *info);
676 void mlx5_sysfs_check_switch_info(bool device_dir,
677 struct mlx5_switch_info *switch_info);
678 void mlx5_nl_check_switch_info(bool nun_vf_set,
679 struct mlx5_switch_info *switch_info);
680 void mlx5_translate_port_name(const char *port_name_in,
681 struct mlx5_switch_info *port_info_out);
682 void mlx5_intr_callback_unregister(const struct rte_intr_handle *handle,
683 rte_intr_callback_fn cb_fn, void *cb_arg);
684 int mlx5_get_module_info(struct rte_eth_dev *dev,
685 struct rte_eth_dev_module_info *modinfo);
686 int mlx5_get_module_eeprom(struct rte_eth_dev *dev,
687 struct rte_dev_eeprom_info *info);
688 int mlx5_hairpin_cap_get(struct rte_eth_dev *dev,
689 struct rte_eth_hairpin_cap *cap);
690 int mlx5_dev_configure_rss_reta(struct rte_eth_dev *dev);
694 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]);
695 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
696 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
697 uint32_t index, uint32_t vmdq);
698 int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr);
699 int mlx5_set_mc_addr_list(struct rte_eth_dev *dev,
700 struct rte_ether_addr *mc_addr_set,
701 uint32_t nb_mc_addr);
705 int mlx5_rss_hash_update(struct rte_eth_dev *dev,
706 struct rte_eth_rss_conf *rss_conf);
707 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev,
708 struct rte_eth_rss_conf *rss_conf);
709 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size);
710 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev,
711 struct rte_eth_rss_reta_entry64 *reta_conf,
713 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev,
714 struct rte_eth_rss_reta_entry64 *reta_conf,
719 int mlx5_promiscuous_enable(struct rte_eth_dev *dev);
720 int mlx5_promiscuous_disable(struct rte_eth_dev *dev);
721 int mlx5_allmulticast_enable(struct rte_eth_dev *dev);
722 int mlx5_allmulticast_disable(struct rte_eth_dev *dev);
726 void mlx5_stats_init(struct rte_eth_dev *dev);
727 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
728 int mlx5_stats_reset(struct rte_eth_dev *dev);
729 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats,
731 int mlx5_xstats_reset(struct rte_eth_dev *dev);
732 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
733 struct rte_eth_xstat_name *xstats_names,
738 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
739 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on);
740 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask);
744 int mlx5_dev_start(struct rte_eth_dev *dev);
745 void mlx5_dev_stop(struct rte_eth_dev *dev);
746 int mlx5_traffic_enable(struct rte_eth_dev *dev);
747 void mlx5_traffic_disable(struct rte_eth_dev *dev);
748 int mlx5_traffic_restart(struct rte_eth_dev *dev);
752 int mlx5_flow_discover_mreg_c(struct rte_eth_dev *eth_dev);
753 bool mlx5_flow_ext_mreg_supported(struct rte_eth_dev *dev);
754 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
755 void mlx5_flow_print(struct rte_flow *flow);
756 int mlx5_flow_validate(struct rte_eth_dev *dev,
757 const struct rte_flow_attr *attr,
758 const struct rte_flow_item items[],
759 const struct rte_flow_action actions[],
760 struct rte_flow_error *error);
761 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev,
762 const struct rte_flow_attr *attr,
763 const struct rte_flow_item items[],
764 const struct rte_flow_action actions[],
765 struct rte_flow_error *error);
766 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow,
767 struct rte_flow_error *error);
768 void mlx5_flow_list_flush(struct rte_eth_dev *dev, struct mlx5_flows *list);
769 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error);
770 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow,
771 const struct rte_flow_action *action, void *data,
772 struct rte_flow_error *error);
773 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable,
774 struct rte_flow_error *error);
775 int mlx5_dev_filter_ctrl(struct rte_eth_dev *dev,
776 enum rte_filter_type filter_type,
777 enum rte_filter_op filter_op,
779 int mlx5_flow_start(struct rte_eth_dev *dev, struct mlx5_flows *list);
780 void mlx5_flow_stop(struct rte_eth_dev *dev, struct mlx5_flows *list);
781 int mlx5_flow_verify(struct rte_eth_dev *dev);
782 int mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, uint32_t queue);
783 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev,
784 struct rte_flow_item_eth *eth_spec,
785 struct rte_flow_item_eth *eth_mask,
786 struct rte_flow_item_vlan *vlan_spec,
787 struct rte_flow_item_vlan *vlan_mask);
788 int mlx5_ctrl_flow(struct rte_eth_dev *dev,
789 struct rte_flow_item_eth *eth_spec,
790 struct rte_flow_item_eth *eth_mask);
791 struct rte_flow *mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev);
792 int mlx5_flow_create_drop_queue(struct rte_eth_dev *dev);
793 void mlx5_flow_delete_drop_queue(struct rte_eth_dev *dev);
794 void mlx5_flow_async_pool_query_handle(struct mlx5_ibv_shared *sh,
795 uint64_t async_id, int status);
796 void mlx5_set_query_alarm(struct mlx5_ibv_shared *sh);
797 void mlx5_flow_query_alarm(void *arg);
798 struct mlx5_flow_counter *mlx5_counter_alloc(struct rte_eth_dev *dev);
799 void mlx5_counter_free(struct rte_eth_dev *dev, struct mlx5_flow_counter *cnt);
800 int mlx5_counter_query(struct rte_eth_dev *dev, struct mlx5_flow_counter *cnt,
801 bool clear, uint64_t *pkts, uint64_t *bytes);
802 int mlx5_flow_dev_dump(struct rte_eth_dev *dev, FILE *file,
803 struct rte_flow_error *error);
806 void mlx5_mp_req_start_rxtx(struct rte_eth_dev *dev);
807 void mlx5_mp_req_stop_rxtx(struct rte_eth_dev *dev);
808 int mlx5_mp_req_mr_create(struct rte_eth_dev *dev, uintptr_t addr);
809 int mlx5_mp_req_verbs_cmd_fd(struct rte_eth_dev *dev);
810 int mlx5_mp_req_queue_state_modify(struct rte_eth_dev *dev,
811 struct mlx5_mp_arg_queue_state_modify *sm);
812 int mlx5_mp_init_primary(void);
813 void mlx5_mp_uninit_primary(void);
814 int mlx5_mp_init_secondary(void);
815 void mlx5_mp_uninit_secondary(void);
819 int mlx5_pmd_socket_init(void);
820 void mlx5_pmd_socket_uninit(void);
824 int mlx5_nl_init(int protocol);
825 int mlx5_nl_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
827 int mlx5_nl_mac_addr_remove(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
829 void mlx5_nl_mac_addr_sync(struct rte_eth_dev *dev);
830 void mlx5_nl_mac_addr_flush(struct rte_eth_dev *dev);
831 int mlx5_nl_promisc(struct rte_eth_dev *dev, int enable);
832 int mlx5_nl_allmulti(struct rte_eth_dev *dev, int enable);
833 unsigned int mlx5_nl_portnum(int nl, const char *name);
834 unsigned int mlx5_nl_ifindex(int nl, const char *name, uint32_t pindex);
835 int mlx5_nl_vf_mac_addr_modify(struct rte_eth_dev *dev,
836 struct rte_ether_addr *mac, int vf_index);
837 int mlx5_nl_switch_info(int nl, unsigned int ifindex,
838 struct mlx5_switch_info *info);
840 struct mlx5_vlan_vmwa_context *mlx5_vlan_vmwa_init(struct rte_eth_dev *dev,
842 void mlx5_vlan_vmwa_exit(struct mlx5_vlan_vmwa_context *ctx);
843 void mlx5_vlan_vmwa_release(struct rte_eth_dev *dev,
844 struct mlx5_vf_vlan *vf_vlan);
845 void mlx5_vlan_vmwa_acquire(struct rte_eth_dev *dev,
846 struct mlx5_vf_vlan *vf_vlan);
848 /* mlx5_flow_meter.c */
850 int mlx5_flow_meter_ops_get(struct rte_eth_dev *dev, void *arg);
851 struct mlx5_flow_meter *mlx5_flow_meter_find(struct mlx5_priv *priv,
853 struct mlx5_flow_meter *mlx5_flow_meter_attach
854 (struct mlx5_priv *priv,
856 const struct rte_flow_attr *attr,
857 struct rte_flow_error *error);
858 void mlx5_flow_meter_detach(struct mlx5_flow_meter *fm);
860 #endif /* RTE_PMD_MLX5_H_ */