1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_H_
7 #define RTE_PMD_MLX5_H_
13 #include <netinet/in.h>
14 #include <sys/queue.h>
17 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
19 #pragma GCC diagnostic ignored "-Wpedantic"
21 #include <infiniband/verbs.h>
23 #pragma GCC diagnostic error "-Wpedantic"
27 #include <rte_ether.h>
28 #include <rte_ethdev_driver.h>
29 #include <rte_rwlock.h>
30 #include <rte_interrupts.h>
31 #include <rte_errno.h>
34 #include "mlx5_utils.h"
36 #include "mlx5_rxtx.h"
37 #include "mlx5_autoconf.h"
38 #include "mlx5_defs.h"
41 PCI_VENDOR_ID_MELLANOX = 0x15b3,
45 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013,
46 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014,
47 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015,
48 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016,
49 PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017,
50 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018,
51 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019,
52 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a,
53 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF = 0xa2d2,
56 /** Switch information returned by mlx5_nl_switch_info(). */
57 struct mlx5_switch_info {
58 uint32_t master:1; /**< Master device. */
59 uint32_t representor:1; /**< Representor device. */
60 int32_t port_name; /**< Representor port name. */
61 uint64_t switch_id; /**< Switch identifier. */
64 LIST_HEAD(mlx5_dev_list, priv);
66 /* Shared memory between primary and secondary processes. */
67 struct mlx5_shared_data {
68 struct mlx5_dev_list mem_event_cb_list;
69 rte_rwlock_t mem_event_rwlock;
72 extern struct mlx5_shared_data *mlx5_shared_data;
74 struct mlx5_xstats_ctrl {
75 /* Number of device stats. */
77 /* Index in the device counters table. */
78 uint16_t dev_table_idx[MLX5_MAX_XSTATS];
79 uint64_t base[MLX5_MAX_XSTATS];
83 TAILQ_HEAD(mlx5_flows, rte_flow);
85 /* Default PMD specific parameter value. */
86 #define MLX5_ARG_UNSET (-1)
89 * Device configuration structure.
91 * Merged configuration from:
93 * - Device capabilities,
94 * - User device parameters disabled features.
96 struct mlx5_dev_config {
97 unsigned int hw_csum:1; /* Checksum offload is supported. */
98 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */
99 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */
100 unsigned int hw_padding:1; /* End alignment padding is supported. */
101 unsigned int vf:1; /* This is a VF. */
102 unsigned int mps:2; /* Multi-packet send supported mode. */
103 unsigned int tunnel_en:1;
104 /* Whether tunnel stateless offloads are supported. */
105 unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */
106 unsigned int flow_counter_en:1; /* Whether flow counter is supported. */
107 unsigned int cqe_comp:1; /* CQE compression is enabled. */
108 unsigned int tso:1; /* Whether TSO is supported. */
109 unsigned int tx_vec_en:1; /* Tx vector is enabled. */
110 unsigned int rx_vec_en:1; /* Rx vector is enabled. */
111 unsigned int mpw_hdr_dseg:1; /* Enable DSEGs in the title WQEBB. */
112 unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */
113 unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */
114 unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */
116 unsigned int enabled:1; /* Whether MPRQ is enabled. */
117 unsigned int stride_num_n; /* Number of strides. */
118 unsigned int min_stride_size_n; /* Min size of a stride. */
119 unsigned int max_stride_size_n; /* Max size of a stride. */
120 unsigned int max_memcpy_len;
121 /* Maximum packet size to memcpy Rx packets. */
122 unsigned int min_rxqs_num;
123 /* Rx queue count threshold to enable MPRQ. */
124 } mprq; /* Configurations for Multi-Packet RQ. */
125 unsigned int flow_prio; /* Number of flow priorities. */
126 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */
127 unsigned int ind_table_max_size; /* Maximum indirection table size. */
128 int txq_inline; /* Maximum packet size for inlining. */
129 int txqs_inline; /* Queue number threshold for inlining. */
130 int inline_max_packet_sz; /* Max packet size for inlining. */
134 * Type of objet being allocated.
136 enum mlx5_verbs_alloc_type {
137 MLX5_VERBS_ALLOC_TYPE_NONE,
138 MLX5_VERBS_ALLOC_TYPE_TX_QUEUE,
139 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE,
143 * Verbs allocator needs a context to know in the callback which kind of
144 * resources it is allocating.
146 struct mlx5_verbs_alloc_ctx {
147 enum mlx5_verbs_alloc_type type; /* Kind of object being allocated. */
148 const void *obj; /* Pointer to the DPDK object. */
151 LIST_HEAD(mlx5_mr_list, mlx5_mr);
153 /* Flow drop context necessary due to Verbs API. */
155 struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */
156 struct mlx5_rxq_ibv *rxq; /* Verbs Rx queue. */
160 LIST_ENTRY(priv) mem_event_cb; /* Called by memory event callback. */
161 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */
162 struct ibv_context *ctx; /* Verbs context. */
163 struct ibv_device_attr_ex device_attr; /* Device properties. */
164 struct ibv_pd *pd; /* Protection Domain. */
165 char ibdev_name[IBV_SYSFS_NAME_MAX]; /* IB device name. */
166 char ibdev_path[IBV_SYSFS_PATH_MAX]; /* IB device path for secondary */
167 struct ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */
168 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES);
169 /* Bit-field of MAC addresses owned by the PMD. */
170 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */
171 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */
172 /* Device properties. */
173 uint16_t mtu; /* Configured MTU. */
174 unsigned int isolated:1; /* Whether isolated mode is enabled. */
175 unsigned int representor:1; /* Device is a port representor. */
176 uint16_t domain_id; /* Switch domain identifier. */
177 int32_t representor_id; /* Port representor identifier. */
179 unsigned int rxqs_n; /* RX queues array size. */
180 unsigned int txqs_n; /* TX queues array size. */
181 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */
182 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */
183 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
184 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */
185 struct rte_intr_handle intr_handle; /* Interrupt handler. */
186 unsigned int (*reta_idx)[]; /* RETA index table. */
187 unsigned int reta_idx_n; /* RETA index size. */
188 struct mlx5_drop drop_queue; /* Flow drop queues. */
189 struct mlx5_flows flows; /* RTE Flow rules. */
190 struct mlx5_flows ctrl_flows; /* Control flow rules. */
191 LIST_HEAD(counters, mlx5_flow_counter) flow_counters;
194 uint32_t dev_gen; /* Generation number to flush local caches. */
195 rte_rwlock_t rwlock; /* MR Lock. */
196 struct mlx5_mr_btree cache; /* Global MR cache table. */
197 struct mlx5_mr_list mr_list; /* Registered MR list. */
198 struct mlx5_mr_list mr_free_list; /* Freed MR list. */
200 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */
201 LIST_HEAD(rxqibv, mlx5_rxq_ibv) rxqsibv; /* Verbs Rx queues. */
202 LIST_HEAD(hrxq, mlx5_hrxq) hrxqs; /* Verbs Hash Rx queues. */
203 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */
204 LIST_HEAD(txqibv, mlx5_txq_ibv) txqsibv; /* Verbs Tx queues. */
205 /* Verbs Indirection tables. */
206 LIST_HEAD(ind_tables, mlx5_ind_table_ibv) ind_tbls;
207 uint32_t link_speed_capa; /* Link speed capabilities. */
208 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */
209 int primary_socket; /* Unix socket for primary process. */
210 void *uar_base; /* Reserved address space for UAR mapping */
211 struct rte_intr_handle intr_handle_socket; /* Interrupt handler. */
212 struct mlx5_dev_config config; /* Device configuration. */
213 struct mlx5_verbs_alloc_ctx verbs_alloc_ctx;
214 /* Context for Verbs allocator. */
215 int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */
216 int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */
217 uint32_t nl_sn; /* Netlink message sequence number. */
219 rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */
220 rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX];
221 /* UAR same-page access control required in 32bit implementations. */
225 #define PORT_ID(priv) ((priv)->dev_data->port_id)
226 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)])
230 int mlx5_getenv_int(const char *);
234 int mlx5_get_master_ifname(const struct rte_eth_dev *dev,
235 char (*ifname)[IF_NAMESIZE]);
236 int mlx5_get_ifname(const struct rte_eth_dev *dev, char (*ifname)[IF_NAMESIZE]);
237 int mlx5_ifindex(const struct rte_eth_dev *dev);
238 int mlx5_ifreq(const struct rte_eth_dev *dev, int req, struct ifreq *ifr,
240 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu);
241 int mlx5_set_flags(struct rte_eth_dev *dev, unsigned int keep,
243 int mlx5_dev_configure(struct rte_eth_dev *dev);
244 void mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info);
245 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev);
246 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete);
247 int mlx5_force_link_status_change(struct rte_eth_dev *dev, int status);
248 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
249 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev,
250 struct rte_eth_fc_conf *fc_conf);
251 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev,
252 struct rte_eth_fc_conf *fc_conf);
253 int mlx5_ibv_device_to_pci_addr(const struct ibv_device *device,
254 struct rte_pci_addr *pci_addr);
255 void mlx5_dev_link_status_handler(void *arg);
256 void mlx5_dev_interrupt_handler(void *arg);
257 void mlx5_dev_interrupt_handler_uninstall(struct rte_eth_dev *dev);
258 void mlx5_dev_interrupt_handler_install(struct rte_eth_dev *dev);
259 int mlx5_set_link_down(struct rte_eth_dev *dev);
260 int mlx5_set_link_up(struct rte_eth_dev *dev);
261 int mlx5_is_removed(struct rte_eth_dev *dev);
262 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev);
263 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev);
264 unsigned int mlx5_dev_to_port_id(const struct rte_device *dev,
266 unsigned int port_list_n);
270 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[ETHER_ADDR_LEN]);
271 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
272 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac,
273 uint32_t index, uint32_t vmdq);
274 int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr);
275 int mlx5_set_mc_addr_list(struct rte_eth_dev *dev,
276 struct ether_addr *mc_addr_set, uint32_t nb_mc_addr);
280 int mlx5_rss_hash_update(struct rte_eth_dev *dev,
281 struct rte_eth_rss_conf *rss_conf);
282 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev,
283 struct rte_eth_rss_conf *rss_conf);
284 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size);
285 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev,
286 struct rte_eth_rss_reta_entry64 *reta_conf,
288 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev,
289 struct rte_eth_rss_reta_entry64 *reta_conf,
294 void mlx5_promiscuous_enable(struct rte_eth_dev *dev);
295 void mlx5_promiscuous_disable(struct rte_eth_dev *dev);
296 void mlx5_allmulticast_enable(struct rte_eth_dev *dev);
297 void mlx5_allmulticast_disable(struct rte_eth_dev *dev);
301 void mlx5_xstats_init(struct rte_eth_dev *dev);
302 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
303 void mlx5_stats_reset(struct rte_eth_dev *dev);
304 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats,
306 void mlx5_xstats_reset(struct rte_eth_dev *dev);
307 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
308 struct rte_eth_xstat_name *xstats_names,
313 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
314 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on);
315 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask);
319 int mlx5_dev_start(struct rte_eth_dev *dev);
320 void mlx5_dev_stop(struct rte_eth_dev *dev);
321 int mlx5_traffic_enable(struct rte_eth_dev *dev);
322 void mlx5_traffic_disable(struct rte_eth_dev *dev);
323 int mlx5_traffic_restart(struct rte_eth_dev *dev);
327 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
328 void mlx5_flow_print(struct rte_flow *flow);
329 int mlx5_flow_validate(struct rte_eth_dev *dev,
330 const struct rte_flow_attr *attr,
331 const struct rte_flow_item items[],
332 const struct rte_flow_action actions[],
333 struct rte_flow_error *error);
334 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev,
335 const struct rte_flow_attr *attr,
336 const struct rte_flow_item items[],
337 const struct rte_flow_action actions[],
338 struct rte_flow_error *error);
339 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow,
340 struct rte_flow_error *error);
341 void mlx5_flow_list_flush(struct rte_eth_dev *dev, struct mlx5_flows *list);
342 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error);
343 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow,
344 const struct rte_flow_action *action, void *data,
345 struct rte_flow_error *error);
346 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable,
347 struct rte_flow_error *error);
348 int mlx5_dev_filter_ctrl(struct rte_eth_dev *dev,
349 enum rte_filter_type filter_type,
350 enum rte_filter_op filter_op,
352 int mlx5_flow_start(struct rte_eth_dev *dev, struct mlx5_flows *list);
353 void mlx5_flow_stop(struct rte_eth_dev *dev, struct mlx5_flows *list);
354 int mlx5_flow_verify(struct rte_eth_dev *dev);
355 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev,
356 struct rte_flow_item_eth *eth_spec,
357 struct rte_flow_item_eth *eth_mask,
358 struct rte_flow_item_vlan *vlan_spec,
359 struct rte_flow_item_vlan *vlan_mask);
360 int mlx5_ctrl_flow(struct rte_eth_dev *dev,
361 struct rte_flow_item_eth *eth_spec,
362 struct rte_flow_item_eth *eth_mask);
363 int mlx5_flow_create_drop_queue(struct rte_eth_dev *dev);
364 void mlx5_flow_delete_drop_queue(struct rte_eth_dev *dev);
368 int mlx5_socket_init(struct rte_eth_dev *priv);
369 void mlx5_socket_uninit(struct rte_eth_dev *priv);
370 void mlx5_socket_handle(struct rte_eth_dev *priv);
371 int mlx5_socket_connect(struct rte_eth_dev *priv);
375 int mlx5_nl_init(uint32_t nlgroups, int protocol);
376 int mlx5_nl_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac,
378 int mlx5_nl_mac_addr_remove(struct rte_eth_dev *dev, struct ether_addr *mac,
380 void mlx5_nl_mac_addr_sync(struct rte_eth_dev *dev);
381 void mlx5_nl_mac_addr_flush(struct rte_eth_dev *dev);
382 int mlx5_nl_promisc(struct rte_eth_dev *dev, int enable);
383 int mlx5_nl_allmulti(struct rte_eth_dev *dev, int enable);
384 unsigned int mlx5_nl_ifindex(int nl, const char *name);
385 int mlx5_nl_switch_info(int nl, unsigned int ifindex,
386 struct mlx5_switch_info *info);
388 #endif /* RTE_PMD_MLX5_H_ */