4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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34 #ifndef RTE_PMD_MLX5_H_
35 #define RTE_PMD_MLX5_H_
41 #include <netinet/in.h>
42 #include <sys/queue.h>
45 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
47 #pragma GCC diagnostic ignored "-Wpedantic"
49 #include <infiniband/verbs.h>
51 #pragma GCC diagnostic error "-Wpedantic"
55 #include <rte_ether.h>
56 #include <rte_ethdev.h>
57 #include <rte_spinlock.h>
58 #include <rte_interrupts.h>
59 #include <rte_errno.h>
62 #include "mlx5_utils.h"
63 #include "mlx5_rxtx.h"
64 #include "mlx5_autoconf.h"
65 #include "mlx5_defs.h"
68 PCI_VENDOR_ID_MELLANOX = 0x15b3,
72 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013,
73 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014,
74 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015,
75 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016,
76 PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017,
77 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018,
78 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019,
79 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a,
82 struct mlx5_xstats_ctrl {
83 /* Number of device stats. */
85 /* Index in the device counters table. */
86 uint16_t dev_table_idx[MLX5_MAX_XSTATS];
87 uint64_t base[MLX5_MAX_XSTATS];
91 TAILQ_HEAD(mlx5_flows, rte_flow);
93 /* Default PMD specific parameter value. */
94 #define MLX5_ARG_UNSET (-1)
97 * Device configuration structure.
99 * Merged configuration from:
101 * - Device capabilities,
102 * - User device parameters disabled features.
104 struct mlx5_dev_config {
105 unsigned int hw_csum:1; /* Checksum offload is supported. */
106 unsigned int hw_csum_l2tun:1; /* Same for L2 tunnels. */
107 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */
108 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */
109 unsigned int hw_padding:1; /* End alignment padding is supported. */
110 unsigned int sriov:1; /* This is a VF or PF with VF devices. */
111 unsigned int mps:2; /* Multi-packet send supported mode. */
112 unsigned int tunnel_en:1; /* Whether tunnel is supported. */
113 unsigned int flow_counter_en:1; /* Whether flow counter is supported. */
114 unsigned int cqe_comp:1; /* CQE compression is enabled. */
115 unsigned int tso:1; /* Whether TSO is supported. */
116 unsigned int tx_vec_en:1; /* Tx vector is enabled. */
117 unsigned int rx_vec_en:1; /* Rx vector is enabled. */
118 unsigned int mpw_hdr_dseg:1; /* Enable DSEGs in the title WQEBB. */
119 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */
120 unsigned int ind_table_max_size; /* Maximum indirection table size. */
121 int txq_inline; /* Maximum packet size for inlining. */
122 int txqs_inline; /* Queue number threshold for inlining. */
123 int inline_max_packet_sz; /* Max packet size for inlining. */
127 struct rte_eth_dev *dev; /* Ethernet device of master process. */
128 struct ibv_context *ctx; /* Verbs context. */
129 struct ibv_device_attr_ex device_attr; /* Device properties. */
130 struct ibv_pd *pd; /* Protection Domain. */
131 char ibdev_path[IBV_SYSFS_PATH_MAX]; /* IB device path for secondary */
132 struct ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */
133 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */
134 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */
135 /* Device properties. */
136 uint16_t mtu; /* Configured MTU. */
137 uint8_t port; /* Physical port number. */
138 unsigned int pending_alarm:1; /* An alarm is pending. */
139 unsigned int isolated:1; /* Whether isolated mode is enabled. */
141 unsigned int rxqs_n; /* RX queues array size. */
142 unsigned int txqs_n; /* TX queues array size. */
143 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */
144 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */
145 unsigned int ind_table_max_size; /* Maximum indirection table size. */
146 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */
147 struct rte_intr_handle intr_handle; /* Interrupt handler. */
148 unsigned int (*reta_idx)[]; /* RETA index table. */
149 unsigned int reta_idx_n; /* RETA index size. */
150 struct mlx5_hrxq_drop *flow_drop_queue; /* Flow drop queue. */
151 struct mlx5_flows flows; /* RTE Flow rules. */
152 struct mlx5_flows ctrl_flows; /* Control flow rules. */
153 LIST_HEAD(mr, mlx5_mr) mr; /* Memory region. */
154 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */
155 LIST_HEAD(rxqibv, mlx5_rxq_ibv) rxqsibv; /* Verbs Rx queues. */
156 LIST_HEAD(hrxq, mlx5_hrxq) hrxqs; /* Verbs Hash Rx queues. */
157 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */
158 LIST_HEAD(txqibv, mlx5_txq_ibv) txqsibv; /* Verbs Tx queues. */
159 /* Verbs Indirection tables. */
160 LIST_HEAD(ind_tables, mlx5_ind_table_ibv) ind_tbls;
161 uint32_t link_speed_capa; /* Link speed capabilities. */
162 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */
163 rte_spinlock_t lock; /* Lock for control functions. */
164 int primary_socket; /* Unix socket for primary process. */
165 struct rte_intr_handle intr_handle_socket; /* Interrupt handler. */
166 struct mlx5_dev_config config; /* Device configuration. */
170 * Lock private structure to protect it from concurrent access in the
174 * Pointer to private structure.
177 priv_lock(struct priv *priv)
179 rte_spinlock_lock(&priv->lock);
183 * Unlock private structure.
186 * Pointer to private structure.
189 priv_unlock(struct priv *priv)
191 rte_spinlock_unlock(&priv->lock);
196 int mlx5_getenv_int(const char *);
200 struct priv *mlx5_get_priv(struct rte_eth_dev *dev);
201 int mlx5_is_secondary(void);
202 int priv_get_ifname(const struct priv *, char (*)[IF_NAMESIZE]);
203 int priv_ifreq(const struct priv *, int req, struct ifreq *);
204 int priv_is_ib_cntr(const char *);
205 int priv_get_cntr_sysfs(struct priv *, const char *, uint64_t *);
206 int priv_get_num_vfs(struct priv *, uint16_t *);
207 int priv_get_mtu(struct priv *, uint16_t *);
208 int priv_set_flags(struct priv *, unsigned int, unsigned int);
209 int mlx5_dev_configure(struct rte_eth_dev *);
210 void mlx5_dev_infos_get(struct rte_eth_dev *, struct rte_eth_dev_info *);
211 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev);
212 int mlx5_link_update(struct rte_eth_dev *, int);
213 int mlx5_dev_set_mtu(struct rte_eth_dev *, uint16_t);
214 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *, struct rte_eth_fc_conf *);
215 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *, struct rte_eth_fc_conf *);
216 int mlx5_ibv_device_to_pci_addr(const struct ibv_device *,
217 struct rte_pci_addr *);
218 void mlx5_dev_link_status_handler(void *);
219 void mlx5_dev_interrupt_handler(void *);
220 void priv_dev_interrupt_handler_uninstall(struct priv *, struct rte_eth_dev *);
221 void priv_dev_interrupt_handler_install(struct priv *, struct rte_eth_dev *);
222 int mlx5_set_link_down(struct rte_eth_dev *dev);
223 int mlx5_set_link_up(struct rte_eth_dev *dev);
224 eth_tx_burst_t priv_select_tx_function(struct priv *, struct rte_eth_dev *);
225 eth_rx_burst_t priv_select_rx_function(struct priv *, struct rte_eth_dev *);
229 int priv_get_mac(struct priv *, uint8_t (*)[ETHER_ADDR_LEN]);
230 void mlx5_mac_addr_remove(struct rte_eth_dev *, uint32_t);
231 int mlx5_mac_addr_add(struct rte_eth_dev *, struct ether_addr *, uint32_t,
233 void mlx5_mac_addr_set(struct rte_eth_dev *, struct ether_addr *);
237 int mlx5_rss_hash_update(struct rte_eth_dev *, struct rte_eth_rss_conf *);
238 int mlx5_rss_hash_conf_get(struct rte_eth_dev *, struct rte_eth_rss_conf *);
239 int priv_rss_reta_index_resize(struct priv *, unsigned int);
240 int mlx5_dev_rss_reta_query(struct rte_eth_dev *,
241 struct rte_eth_rss_reta_entry64 *, uint16_t);
242 int mlx5_dev_rss_reta_update(struct rte_eth_dev *,
243 struct rte_eth_rss_reta_entry64 *, uint16_t);
247 void mlx5_promiscuous_enable(struct rte_eth_dev *);
248 void mlx5_promiscuous_disable(struct rte_eth_dev *);
249 void mlx5_allmulticast_enable(struct rte_eth_dev *);
250 void mlx5_allmulticast_disable(struct rte_eth_dev *);
254 void priv_xstats_init(struct priv *);
255 int mlx5_stats_get(struct rte_eth_dev *, struct rte_eth_stats *);
256 void mlx5_stats_reset(struct rte_eth_dev *);
257 int mlx5_xstats_get(struct rte_eth_dev *,
258 struct rte_eth_xstat *, unsigned int);
259 void mlx5_xstats_reset(struct rte_eth_dev *);
260 int mlx5_xstats_get_names(struct rte_eth_dev *,
261 struct rte_eth_xstat_name *, unsigned int);
265 int mlx5_vlan_filter_set(struct rte_eth_dev *, uint16_t, int);
266 int mlx5_vlan_offload_set(struct rte_eth_dev *, int);
267 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *, uint16_t, int);
271 int mlx5_dev_start(struct rte_eth_dev *);
272 void mlx5_dev_stop(struct rte_eth_dev *);
273 int priv_dev_traffic_enable(struct priv *, struct rte_eth_dev *);
274 int priv_dev_traffic_disable(struct priv *, struct rte_eth_dev *);
275 int priv_dev_traffic_restart(struct priv *, struct rte_eth_dev *);
276 int mlx5_traffic_restart(struct rte_eth_dev *);
280 int mlx5_dev_filter_ctrl(struct rte_eth_dev *, enum rte_filter_type,
281 enum rte_filter_op, void *);
282 int mlx5_flow_validate(struct rte_eth_dev *, const struct rte_flow_attr *,
283 const struct rte_flow_item [],
284 const struct rte_flow_action [],
285 struct rte_flow_error *);
286 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *,
287 const struct rte_flow_attr *,
288 const struct rte_flow_item [],
289 const struct rte_flow_action [],
290 struct rte_flow_error *);
291 int mlx5_flow_destroy(struct rte_eth_dev *, struct rte_flow *,
292 struct rte_flow_error *);
293 void priv_flow_flush(struct priv *, struct mlx5_flows *);
294 int mlx5_flow_flush(struct rte_eth_dev *, struct rte_flow_error *);
295 int mlx5_flow_query(struct rte_eth_dev *, struct rte_flow *,
296 enum rte_flow_action_type, void *,
297 struct rte_flow_error *);
298 int mlx5_flow_isolate(struct rte_eth_dev *, int, struct rte_flow_error *);
299 int priv_flow_start(struct priv *, struct mlx5_flows *);
300 void priv_flow_stop(struct priv *, struct mlx5_flows *);
301 int priv_flow_verify(struct priv *);
302 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *, struct rte_flow_item_eth *,
303 struct rte_flow_item_eth *, struct rte_flow_item_vlan *,
304 struct rte_flow_item_vlan *);
305 int mlx5_ctrl_flow(struct rte_eth_dev *, struct rte_flow_item_eth *,
306 struct rte_flow_item_eth *);
307 int priv_flow_create_drop_queue(struct priv *);
308 void priv_flow_delete_drop_queue(struct priv *);
312 int priv_socket_init(struct priv *priv);
313 int priv_socket_uninit(struct priv *priv);
314 void priv_socket_handle(struct priv *priv);
315 int priv_socket_connect(struct priv *priv);
319 struct mlx5_mr *priv_mr_new(struct priv *, struct rte_mempool *);
320 struct mlx5_mr *priv_mr_get(struct priv *, struct rte_mempool *);
321 int priv_mr_release(struct priv *, struct mlx5_mr *);
322 int priv_mr_verify(struct priv *);
324 #endif /* RTE_PMD_MLX5_H_ */