1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox.
6 #ifndef RTE_PMD_MLX5_H_
7 #define RTE_PMD_MLX5_H_
13 #include <netinet/in.h>
14 #include <sys/queue.h>
17 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
19 #pragma GCC diagnostic ignored "-Wpedantic"
21 #include <infiniband/verbs.h>
23 #pragma GCC diagnostic error "-Wpedantic"
27 #include <rte_ether.h>
28 #include <rte_ethdev_driver.h>
29 #include <rte_spinlock.h>
30 #include <rte_interrupts.h>
31 #include <rte_errno.h>
34 #include "mlx5_utils.h"
35 #include "mlx5_rxtx.h"
36 #include "mlx5_autoconf.h"
37 #include "mlx5_defs.h"
40 PCI_VENDOR_ID_MELLANOX = 0x15b3,
44 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013,
45 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014,
46 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015,
47 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016,
48 PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017,
49 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018,
50 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019,
51 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a,
54 struct mlx5_xstats_ctrl {
55 /* Number of device stats. */
57 /* Index in the device counters table. */
58 uint16_t dev_table_idx[MLX5_MAX_XSTATS];
59 uint64_t base[MLX5_MAX_XSTATS];
63 TAILQ_HEAD(mlx5_flows, rte_flow);
65 /* Default PMD specific parameter value. */
66 #define MLX5_ARG_UNSET (-1)
69 * Device configuration structure.
71 * Merged configuration from:
73 * - Device capabilities,
74 * - User device parameters disabled features.
76 struct mlx5_dev_config {
77 unsigned int hw_csum:1; /* Checksum offload is supported. */
78 unsigned int hw_csum_l2tun:1; /* Same for L2 tunnels. */
79 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */
80 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */
81 unsigned int hw_padding:1; /* End alignment padding is supported. */
82 unsigned int sriov:1; /* This is a VF or PF with VF devices. */
83 unsigned int mps:2; /* Multi-packet send supported mode. */
84 unsigned int tunnel_en:1; /* Whether tunnel is supported. */
85 unsigned int flow_counter_en:1; /* Whether flow counter is supported. */
86 unsigned int cqe_comp:1; /* CQE compression is enabled. */
87 unsigned int tso:1; /* Whether TSO is supported. */
88 unsigned int tx_vec_en:1; /* Tx vector is enabled. */
89 unsigned int rx_vec_en:1; /* Rx vector is enabled. */
90 unsigned int mpw_hdr_dseg:1; /* Enable DSEGs in the title WQEBB. */
91 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */
92 unsigned int ind_table_max_size; /* Maximum indirection table size. */
93 int txq_inline; /* Maximum packet size for inlining. */
94 int txqs_inline; /* Queue number threshold for inlining. */
95 int inline_max_packet_sz; /* Max packet size for inlining. */
99 * Type of objet being allocated.
101 enum mlx5_verbs_alloc_type {
102 MLX5_VERBS_ALLOC_TYPE_NONE,
103 MLX5_VERBS_ALLOC_TYPE_TX_QUEUE,
104 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE,
108 * Verbs allocator needs a context to know in the callback which kind of
109 * resources it is allocating.
111 struct mlx5_verbs_alloc_ctx {
112 enum mlx5_verbs_alloc_type type; /* Kind of object being allocated. */
113 const void *obj; /* Pointer to the DPDK object. */
117 struct rte_eth_dev *dev; /* Ethernet device of master process. */
118 struct ibv_context *ctx; /* Verbs context. */
119 struct ibv_device_attr_ex device_attr; /* Device properties. */
120 struct ibv_pd *pd; /* Protection Domain. */
121 char ibdev_path[IBV_SYSFS_PATH_MAX]; /* IB device path for secondary */
122 struct ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */
123 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */
124 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */
125 /* Device properties. */
126 uint16_t mtu; /* Configured MTU. */
127 uint8_t port; /* Physical port number. */
128 unsigned int pending_alarm:1; /* An alarm is pending. */
129 unsigned int isolated:1; /* Whether isolated mode is enabled. */
131 unsigned int rxqs_n; /* RX queues array size. */
132 unsigned int txqs_n; /* TX queues array size. */
133 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */
134 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */
135 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */
136 struct rte_intr_handle intr_handle; /* Interrupt handler. */
137 unsigned int (*reta_idx)[]; /* RETA index table. */
138 unsigned int reta_idx_n; /* RETA index size. */
139 struct mlx5_hrxq_drop *flow_drop_queue; /* Flow drop queue. */
140 struct mlx5_flows flows; /* RTE Flow rules. */
141 struct mlx5_flows ctrl_flows; /* Control flow rules. */
142 LIST_HEAD(mr, mlx5_mr) mr; /* Memory region. */
143 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */
144 LIST_HEAD(rxqibv, mlx5_rxq_ibv) rxqsibv; /* Verbs Rx queues. */
145 LIST_HEAD(hrxq, mlx5_hrxq) hrxqs; /* Verbs Hash Rx queues. */
146 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */
147 LIST_HEAD(txqibv, mlx5_txq_ibv) txqsibv; /* Verbs Tx queues. */
148 /* Verbs Indirection tables. */
149 LIST_HEAD(ind_tables, mlx5_ind_table_ibv) ind_tbls;
150 uint32_t link_speed_capa; /* Link speed capabilities. */
151 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */
152 rte_spinlock_t lock; /* Lock for control functions. */
153 int primary_socket; /* Unix socket for primary process. */
154 void *uar_base; /* Reserved address space for UAR mapping */
155 struct rte_intr_handle intr_handle_socket; /* Interrupt handler. */
156 struct mlx5_dev_config config; /* Device configuration. */
157 struct mlx5_verbs_alloc_ctx verbs_alloc_ctx;
158 /* Context for Verbs allocator. */
162 * Lock private structure to protect it from concurrent access in the
166 * Pointer to private structure.
169 priv_lock(struct priv *priv)
171 rte_spinlock_lock(&priv->lock);
175 * Try to lock private structure to protect it from concurrent access in the
179 * Pointer to private structure.
182 * 1 if the lock is successfully taken; 0 otherwise.
185 priv_trylock(struct priv *priv)
187 return rte_spinlock_trylock(&priv->lock);
191 * Unlock private structure.
194 * Pointer to private structure.
197 priv_unlock(struct priv *priv)
199 rte_spinlock_unlock(&priv->lock);
204 int mlx5_getenv_int(const char *);
208 struct priv *mlx5_get_priv(struct rte_eth_dev *dev);
209 int mlx5_is_secondary(void);
210 int priv_get_ifname(const struct priv *, char (*)[IF_NAMESIZE]);
211 int priv_ifreq(const struct priv *, int req, struct ifreq *);
212 int priv_is_ib_cntr(const char *);
213 int priv_get_cntr_sysfs(struct priv *, const char *, uint64_t *);
214 int priv_get_num_vfs(struct priv *, uint16_t *);
215 int priv_get_mtu(struct priv *, uint16_t *);
216 int priv_set_flags(struct priv *, unsigned int, unsigned int);
217 int mlx5_dev_configure(struct rte_eth_dev *);
218 void mlx5_dev_infos_get(struct rte_eth_dev *, struct rte_eth_dev_info *);
219 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev);
220 int priv_link_update(struct priv *, int);
221 int priv_force_link_status_change(struct priv *, int);
222 int mlx5_link_update(struct rte_eth_dev *, int);
223 int mlx5_dev_set_mtu(struct rte_eth_dev *, uint16_t);
224 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *, struct rte_eth_fc_conf *);
225 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *, struct rte_eth_fc_conf *);
226 int mlx5_ibv_device_to_pci_addr(const struct ibv_device *,
227 struct rte_pci_addr *);
228 void mlx5_dev_link_status_handler(void *);
229 void mlx5_dev_interrupt_handler(void *);
230 void priv_dev_interrupt_handler_uninstall(struct priv *, struct rte_eth_dev *);
231 void priv_dev_interrupt_handler_install(struct priv *, struct rte_eth_dev *);
232 int mlx5_set_link_down(struct rte_eth_dev *dev);
233 int mlx5_set_link_up(struct rte_eth_dev *dev);
234 int mlx5_is_removed(struct rte_eth_dev *dev);
235 eth_tx_burst_t priv_select_tx_function(struct priv *, struct rte_eth_dev *);
236 eth_rx_burst_t priv_select_rx_function(struct priv *, struct rte_eth_dev *);
240 int priv_get_mac(struct priv *, uint8_t (*)[ETHER_ADDR_LEN]);
241 void mlx5_mac_addr_remove(struct rte_eth_dev *, uint32_t);
242 int mlx5_mac_addr_add(struct rte_eth_dev *, struct ether_addr *, uint32_t,
244 void mlx5_mac_addr_set(struct rte_eth_dev *, struct ether_addr *);
248 int mlx5_rss_hash_update(struct rte_eth_dev *, struct rte_eth_rss_conf *);
249 int mlx5_rss_hash_conf_get(struct rte_eth_dev *, struct rte_eth_rss_conf *);
250 int priv_rss_reta_index_resize(struct priv *, unsigned int);
251 int mlx5_dev_rss_reta_query(struct rte_eth_dev *,
252 struct rte_eth_rss_reta_entry64 *, uint16_t);
253 int mlx5_dev_rss_reta_update(struct rte_eth_dev *,
254 struct rte_eth_rss_reta_entry64 *, uint16_t);
258 void mlx5_promiscuous_enable(struct rte_eth_dev *);
259 void mlx5_promiscuous_disable(struct rte_eth_dev *);
260 void mlx5_allmulticast_enable(struct rte_eth_dev *);
261 void mlx5_allmulticast_disable(struct rte_eth_dev *);
265 void priv_xstats_init(struct priv *);
266 int mlx5_stats_get(struct rte_eth_dev *, struct rte_eth_stats *);
267 void mlx5_stats_reset(struct rte_eth_dev *);
268 int mlx5_xstats_get(struct rte_eth_dev *,
269 struct rte_eth_xstat *, unsigned int);
270 void mlx5_xstats_reset(struct rte_eth_dev *);
271 int mlx5_xstats_get_names(struct rte_eth_dev *,
272 struct rte_eth_xstat_name *, unsigned int);
276 int mlx5_vlan_filter_set(struct rte_eth_dev *, uint16_t, int);
277 int mlx5_vlan_offload_set(struct rte_eth_dev *, int);
278 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *, uint16_t, int);
282 int mlx5_dev_start(struct rte_eth_dev *);
283 void mlx5_dev_stop(struct rte_eth_dev *);
284 int priv_dev_traffic_enable(struct priv *, struct rte_eth_dev *);
285 int priv_dev_traffic_disable(struct priv *, struct rte_eth_dev *);
286 int priv_dev_traffic_restart(struct priv *, struct rte_eth_dev *);
287 int mlx5_traffic_restart(struct rte_eth_dev *);
291 int mlx5_dev_filter_ctrl(struct rte_eth_dev *, enum rte_filter_type,
292 enum rte_filter_op, void *);
293 int mlx5_flow_validate(struct rte_eth_dev *, const struct rte_flow_attr *,
294 const struct rte_flow_item [],
295 const struct rte_flow_action [],
296 struct rte_flow_error *);
297 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *,
298 const struct rte_flow_attr *,
299 const struct rte_flow_item [],
300 const struct rte_flow_action [],
301 struct rte_flow_error *);
302 int mlx5_flow_destroy(struct rte_eth_dev *, struct rte_flow *,
303 struct rte_flow_error *);
304 void priv_flow_flush(struct priv *, struct mlx5_flows *);
305 int mlx5_flow_flush(struct rte_eth_dev *, struct rte_flow_error *);
306 int mlx5_flow_query(struct rte_eth_dev *, struct rte_flow *,
307 enum rte_flow_action_type, void *,
308 struct rte_flow_error *);
309 int mlx5_flow_isolate(struct rte_eth_dev *, int, struct rte_flow_error *);
310 int priv_flow_start(struct priv *, struct mlx5_flows *);
311 void priv_flow_stop(struct priv *, struct mlx5_flows *);
312 int priv_flow_verify(struct priv *);
313 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *, struct rte_flow_item_eth *,
314 struct rte_flow_item_eth *, struct rte_flow_item_vlan *,
315 struct rte_flow_item_vlan *);
316 int mlx5_ctrl_flow(struct rte_eth_dev *, struct rte_flow_item_eth *,
317 struct rte_flow_item_eth *);
318 int priv_flow_create_drop_queue(struct priv *);
319 void priv_flow_delete_drop_queue(struct priv *);
323 int priv_socket_init(struct priv *priv);
324 int priv_socket_uninit(struct priv *priv);
325 void priv_socket_handle(struct priv *priv);
326 int priv_socket_connect(struct priv *priv);
330 struct mlx5_mr *priv_mr_new(struct priv *, struct rte_mempool *);
331 struct mlx5_mr *priv_mr_get(struct priv *, struct rte_mempool *);
332 int priv_mr_release(struct priv *, struct mlx5_mr *);
333 int priv_mr_verify(struct priv *);
335 #endif /* RTE_PMD_MLX5_H_ */