1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_H_
7 #define RTE_PMD_MLX5_H_
13 #include <netinet/in.h>
14 #include <sys/queue.h>
17 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
19 #pragma GCC diagnostic ignored "-Wpedantic"
21 #include <infiniband/verbs.h>
23 #pragma GCC diagnostic error "-Wpedantic"
27 #include <rte_ether.h>
28 #include <rte_ethdev_driver.h>
29 #include <rte_spinlock.h>
30 #include <rte_interrupts.h>
31 #include <rte_errno.h>
34 #include "mlx5_utils.h"
35 #include "mlx5_rxtx.h"
36 #include "mlx5_autoconf.h"
37 #include "mlx5_defs.h"
40 PCI_VENDOR_ID_MELLANOX = 0x15b3,
44 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013,
45 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014,
46 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015,
47 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016,
48 PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017,
49 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018,
50 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019,
51 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a,
54 struct mlx5_xstats_ctrl {
55 /* Number of device stats. */
57 /* Index in the device counters table. */
58 uint16_t dev_table_idx[MLX5_MAX_XSTATS];
59 uint64_t base[MLX5_MAX_XSTATS];
63 TAILQ_HEAD(mlx5_flows, rte_flow);
65 /* Default PMD specific parameter value. */
66 #define MLX5_ARG_UNSET (-1)
69 * Device configuration structure.
71 * Merged configuration from:
73 * - Device capabilities,
74 * - User device parameters disabled features.
76 struct mlx5_dev_config {
77 unsigned int hw_csum:1; /* Checksum offload is supported. */
78 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */
79 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */
80 unsigned int hw_padding:1; /* End alignment padding is supported. */
81 unsigned int vf:1; /* This is a VF. */
82 unsigned int mps:2; /* Multi-packet send supported mode. */
83 unsigned int tunnel_en:1;
84 /* Whether tunnel stateless offloads are supported. */
85 unsigned int flow_counter_en:1; /* Whether flow counter is supported. */
86 unsigned int cqe_comp:1; /* CQE compression is enabled. */
87 unsigned int tso:1; /* Whether TSO is supported. */
88 unsigned int tx_vec_en:1; /* Tx vector is enabled. */
89 unsigned int rx_vec_en:1; /* Rx vector is enabled. */
90 unsigned int mpw_hdr_dseg:1; /* Enable DSEGs in the title WQEBB. */
91 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */
92 unsigned int ind_table_max_size; /* Maximum indirection table size. */
93 int txq_inline; /* Maximum packet size for inlining. */
94 int txqs_inline; /* Queue number threshold for inlining. */
95 int inline_max_packet_sz; /* Max packet size for inlining. */
99 * Type of objet being allocated.
101 enum mlx5_verbs_alloc_type {
102 MLX5_VERBS_ALLOC_TYPE_NONE,
103 MLX5_VERBS_ALLOC_TYPE_TX_QUEUE,
104 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE,
108 * Verbs allocator needs a context to know in the callback which kind of
109 * resources it is allocating.
111 struct mlx5_verbs_alloc_ctx {
112 enum mlx5_verbs_alloc_type type; /* Kind of object being allocated. */
113 const void *obj; /* Pointer to the DPDK object. */
117 struct rte_eth_dev *dev; /* Ethernet device of master process. */
118 struct ibv_context *ctx; /* Verbs context. */
119 struct ibv_device_attr_ex device_attr; /* Device properties. */
120 struct ibv_pd *pd; /* Protection Domain. */
121 char ibdev_path[IBV_SYSFS_PATH_MAX]; /* IB device path for secondary */
122 struct ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */
123 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES);
124 /* Bit-field of MAC addresses owned by the PMD. */
125 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */
126 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */
127 /* Device properties. */
128 uint16_t mtu; /* Configured MTU. */
129 uint8_t port; /* Physical port number. */
130 unsigned int isolated:1; /* Whether isolated mode is enabled. */
132 unsigned int rxqs_n; /* RX queues array size. */
133 unsigned int txqs_n; /* TX queues array size. */
134 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */
135 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */
136 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */
137 struct rte_intr_handle intr_handle; /* Interrupt handler. */
138 unsigned int (*reta_idx)[]; /* RETA index table. */
139 unsigned int reta_idx_n; /* RETA index size. */
140 struct mlx5_hrxq_drop *flow_drop_queue; /* Flow drop queue. */
141 struct mlx5_flows flows; /* RTE Flow rules. */
142 struct mlx5_flows ctrl_flows; /* Control flow rules. */
143 LIST_HEAD(mr, mlx5_mr) mr; /* Memory region. */
144 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */
145 LIST_HEAD(rxqibv, mlx5_rxq_ibv) rxqsibv; /* Verbs Rx queues. */
146 LIST_HEAD(hrxq, mlx5_hrxq) hrxqs; /* Verbs Hash Rx queues. */
147 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */
148 LIST_HEAD(txqibv, mlx5_txq_ibv) txqsibv; /* Verbs Tx queues. */
149 /* Verbs Indirection tables. */
150 LIST_HEAD(ind_tables, mlx5_ind_table_ibv) ind_tbls;
151 uint32_t link_speed_capa; /* Link speed capabilities. */
152 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */
153 rte_spinlock_t mr_lock; /* MR Lock. */
154 int primary_socket; /* Unix socket for primary process. */
155 void *uar_base; /* Reserved address space for UAR mapping */
156 struct rte_intr_handle intr_handle_socket; /* Interrupt handler. */
157 struct mlx5_dev_config config; /* Device configuration. */
158 struct mlx5_verbs_alloc_ctx verbs_alloc_ctx;
159 /* Context for Verbs allocator. */
160 int nl_socket; /* Netlink socket. */
161 uint32_t nl_sn; /* Netlink message sequence number. */
166 int mlx5_getenv_int(const char *);
170 int mlx5_get_ifname(const struct rte_eth_dev *dev, char (*ifname)[IF_NAMESIZE]);
171 int mlx5_ifindex(const struct rte_eth_dev *dev);
172 int mlx5_ifreq(const struct rte_eth_dev *dev, int req, struct ifreq *ifr);
173 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu);
174 int mlx5_set_flags(struct rte_eth_dev *dev, unsigned int keep,
176 int mlx5_dev_configure(struct rte_eth_dev *dev);
177 void mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info);
178 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev);
179 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete);
180 int mlx5_force_link_status_change(struct rte_eth_dev *dev, int status);
181 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
182 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev,
183 struct rte_eth_fc_conf *fc_conf);
184 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev,
185 struct rte_eth_fc_conf *fc_conf);
186 int mlx5_ibv_device_to_pci_addr(const struct ibv_device *device,
187 struct rte_pci_addr *pci_addr);
188 void mlx5_dev_link_status_handler(void *arg);
189 void mlx5_dev_interrupt_handler(void *arg);
190 void mlx5_dev_interrupt_handler_uninstall(struct rte_eth_dev *dev);
191 void mlx5_dev_interrupt_handler_install(struct rte_eth_dev *dev);
192 int mlx5_set_link_down(struct rte_eth_dev *dev);
193 int mlx5_set_link_up(struct rte_eth_dev *dev);
194 int mlx5_is_removed(struct rte_eth_dev *dev);
195 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev);
196 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev);
200 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[ETHER_ADDR_LEN]);
201 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
202 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac,
203 uint32_t index, uint32_t vmdq);
204 void mlx5_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr);
208 int mlx5_rss_hash_update(struct rte_eth_dev *dev,
209 struct rte_eth_rss_conf *rss_conf);
210 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev,
211 struct rte_eth_rss_conf *rss_conf);
212 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size);
213 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev,
214 struct rte_eth_rss_reta_entry64 *reta_conf,
216 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev,
217 struct rte_eth_rss_reta_entry64 *reta_conf,
222 void mlx5_promiscuous_enable(struct rte_eth_dev *dev);
223 void mlx5_promiscuous_disable(struct rte_eth_dev *dev);
224 void mlx5_allmulticast_enable(struct rte_eth_dev *dev);
225 void mlx5_allmulticast_disable(struct rte_eth_dev *dev);
229 void mlx5_xstats_init(struct rte_eth_dev *dev);
230 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
231 void mlx5_stats_reset(struct rte_eth_dev *dev);
232 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats,
234 void mlx5_xstats_reset(struct rte_eth_dev *dev);
235 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
236 struct rte_eth_xstat_name *xstats_names,
241 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
242 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on);
243 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask);
247 int mlx5_dev_start(struct rte_eth_dev *dev);
248 void mlx5_dev_stop(struct rte_eth_dev *dev);
249 int mlx5_traffic_enable(struct rte_eth_dev *dev);
250 void mlx5_traffic_disable(struct rte_eth_dev *dev);
251 int mlx5_traffic_restart(struct rte_eth_dev *dev);
255 int mlx5_flow_validate(struct rte_eth_dev *dev,
256 const struct rte_flow_attr *attr,
257 const struct rte_flow_item items[],
258 const struct rte_flow_action actions[],
259 struct rte_flow_error *error);
260 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev,
261 const struct rte_flow_attr *attr,
262 const struct rte_flow_item items[],
263 const struct rte_flow_action actions[],
264 struct rte_flow_error *error);
265 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow,
266 struct rte_flow_error *error);
267 void mlx5_flow_list_flush(struct rte_eth_dev *dev, struct mlx5_flows *list);
268 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error);
269 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow,
270 enum rte_flow_action_type action, void *data,
271 struct rte_flow_error *error);
272 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable,
273 struct rte_flow_error *error);
274 int mlx5_dev_filter_ctrl(struct rte_eth_dev *dev,
275 enum rte_filter_type filter_type,
276 enum rte_filter_op filter_op,
278 int mlx5_flow_start(struct rte_eth_dev *dev, struct mlx5_flows *list);
279 void mlx5_flow_stop(struct rte_eth_dev *dev, struct mlx5_flows *list);
280 int mlx5_flow_verify(struct rte_eth_dev *dev);
281 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev,
282 struct rte_flow_item_eth *eth_spec,
283 struct rte_flow_item_eth *eth_mask,
284 struct rte_flow_item_vlan *vlan_spec,
285 struct rte_flow_item_vlan *vlan_mask);
286 int mlx5_ctrl_flow(struct rte_eth_dev *dev,
287 struct rte_flow_item_eth *eth_spec,
288 struct rte_flow_item_eth *eth_mask);
289 int mlx5_flow_create_drop_queue(struct rte_eth_dev *dev);
290 void mlx5_flow_delete_drop_queue(struct rte_eth_dev *dev);
294 int mlx5_socket_init(struct rte_eth_dev *priv);
295 void mlx5_socket_uninit(struct rte_eth_dev *priv);
296 void mlx5_socket_handle(struct rte_eth_dev *priv);
297 int mlx5_socket_connect(struct rte_eth_dev *priv);
301 struct mlx5_mr *mlx5_mr_new(struct rte_eth_dev *dev, struct rte_mempool *mp);
302 struct mlx5_mr *mlx5_mr_get(struct rte_eth_dev *dev, struct rte_mempool *mp);
303 int mlx5_mr_release(struct mlx5_mr *mr);
304 int mlx5_mr_verify(struct rte_eth_dev *dev);
308 int mlx5_nl_init(uint32_t nlgroups);
309 int mlx5_nl_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac,
311 int mlx5_nl_mac_addr_remove(struct rte_eth_dev *dev, struct ether_addr *mac,
313 void mlx5_nl_mac_addr_sync(struct rte_eth_dev *dev);
314 void mlx5_nl_mac_addr_flush(struct rte_eth_dev *dev);
315 int mlx5_nl_promisc(struct rte_eth_dev *dev, int enable);
316 int mlx5_nl_allmulti(struct rte_eth_dev *dev, int enable);
318 #endif /* RTE_PMD_MLX5_H_ */