1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_H_
7 #define RTE_PMD_MLX5_H_
14 #include <netinet/in.h>
15 #include <sys/queue.h>
18 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
20 #pragma GCC diagnostic ignored "-Wpedantic"
22 #include <infiniband/verbs.h>
24 #pragma GCC diagnostic error "-Wpedantic"
28 #include <rte_ether.h>
29 #include <rte_ethdev_driver.h>
30 #include <rte_rwlock.h>
31 #include <rte_interrupts.h>
32 #include <rte_errno.h>
35 #include <mlx5_glue.h>
36 #include <mlx5_devx_cmds.h>
39 #include <mlx5_common_mp.h>
40 #include <mlx5_common_mr.h>
42 #include "mlx5_defs.h"
43 #include "mlx5_utils.h"
45 #include "mlx5_autoconf.h"
47 enum mlx5_ipool_index {
48 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
49 MLX5_IPOOL_DECAP_ENCAP = 0, /* Pool for encap/decap resource. */
50 MLX5_IPOOL_PUSH_VLAN, /* Pool for push vlan resource. */
51 MLX5_IPOOL_TAG, /* Pool for tag resource. */
52 MLX5_IPOOL_PORT_ID, /* Pool for port id resource. */
53 MLX5_IPOOL_JUMP, /* Pool for jump resource. */
55 MLX5_IPOOL_MTR, /* Pool for meter resource. */
56 MLX5_IPOOL_MCP, /* Pool for metadata resource. */
57 MLX5_IPOOL_HRXQ, /* Pool for hrxq resource. */
58 MLX5_IPOOL_MLX5_FLOW, /* Pool for mlx5 flow handle. */
59 MLX5_IPOOL_RTE_FLOW, /* Pool for rte_flow. */
64 * There are three reclaim memory mode supported.
65 * 0(none) means no memory reclaim.
66 * 1(light) means only PMD level reclaim.
67 * 2(aggressive) means both PMD and rdma-core level reclaim.
69 enum mlx5_reclaim_mem_mode {
70 MLX5_RCM_NONE, /* Don't reclaim memory. */
71 MLX5_RCM_LIGHT, /* Reclaim PMD level. */
72 MLX5_RCM_AGGR, /* Reclaim PMD and rdma-core level. */
75 /* Device attributes used in mlx5 PMD */
76 struct mlx5_dev_attr {
77 uint64_t device_cap_flags_ex;
82 uint32_t raw_packet_caps;
83 uint32_t max_rwq_indirection_table_size;
85 uint32_t tso_supported_qpts;
88 uint32_t sw_parsing_offloads;
89 uint32_t min_single_stride_log_num_of_bytes;
90 uint32_t max_single_stride_log_num_of_bytes;
91 uint32_t min_single_wqe_log_num_of_strides;
92 uint32_t max_single_wqe_log_num_of_strides;
93 uint32_t stride_supported_qpts;
94 uint32_t tunnel_offloads_caps;
98 /** Data associated with devices to spawn. */
99 struct mlx5_dev_spawn_data {
100 uint32_t ifindex; /**< Network interface index. */
101 uint32_t max_port; /**< Device maximal port index. */
102 uint32_t phys_port; /**< Device physical port index. */
103 int pf_bond; /**< bonding device PF index. < 0 - no bonding */
104 struct mlx5_switch_info info; /**< Switch information. */
105 void *phys_dev; /**< Associated physical device. */
106 struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */
107 struct rte_pci_device *pci_dev; /**< Backend PCI device. */
110 /** Key string for IPC. */
111 #define MLX5_MP_NAME "net_mlx5_mp"
114 LIST_HEAD(mlx5_dev_list, mlx5_dev_ctx_shared);
116 /* Shared data between primary and secondary processes. */
117 struct mlx5_shared_data {
119 /* Global spinlock for primary and secondary processes. */
120 int init_done; /* Whether primary has done initialization. */
121 unsigned int secondary_cnt; /* Number of secondary processes init'd. */
122 struct mlx5_dev_list mem_event_cb_list;
123 rte_rwlock_t mem_event_rwlock;
126 /* Per-process data structure, not visible to other processes. */
127 struct mlx5_local_data {
128 int init_done; /* Whether a secondary has done initialization. */
131 extern struct mlx5_shared_data *mlx5_shared_data;
132 extern struct rte_pci_driver mlx5_driver;
134 /* Dev ops structs */
135 extern const struct eth_dev_ops mlx5_os_dev_ops;
136 extern const struct eth_dev_ops mlx5_os_dev_sec_ops;
137 extern const struct eth_dev_ops mlx5_os_dev_ops_isolate;
139 struct mlx5_counter_ctrl {
140 /* Name of the counter. */
141 char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE];
142 /* Name of the counter on the device table. */
143 char ctr_name[RTE_ETH_XSTATS_NAME_SIZE];
144 uint32_t dev:1; /**< Nonzero for dev counters. */
147 struct mlx5_xstats_ctrl {
148 /* Number of device stats. */
150 /* Number of device stats identified by PMD. */
151 uint16_t mlx5_stats_n;
152 /* Index in the device counters table. */
153 uint16_t dev_table_idx[MLX5_MAX_XSTATS];
154 uint64_t base[MLX5_MAX_XSTATS];
155 uint64_t xstats[MLX5_MAX_XSTATS];
156 uint64_t hw_stats[MLX5_MAX_XSTATS];
157 struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS];
160 struct mlx5_stats_ctrl {
161 /* Base for imissed counter. */
162 uint64_t imissed_base;
166 /* Default PMD specific parameter value. */
167 #define MLX5_ARG_UNSET (-1)
169 #define MLX5_LRO_SUPPORTED(dev) \
170 (((struct mlx5_priv *)((dev)->data->dev_private))->config.lro.supported)
172 /* Maximal size of coalesced segment for LRO is set in chunks of 256 Bytes. */
173 #define MLX5_LRO_SEG_CHUNK_SIZE 256u
175 /* Maximal size of aggregated LRO packet. */
176 #define MLX5_MAX_LRO_SIZE (UINT8_MAX * MLX5_LRO_SEG_CHUNK_SIZE)
178 /* LRO configurations structure. */
179 struct mlx5_lro_config {
180 uint32_t supported:1; /* Whether LRO is supported. */
181 uint32_t timeout; /* User configuration. */
185 * Device configuration structure.
187 * Merged configuration from:
189 * - Device capabilities,
190 * - User device parameters disabled features.
192 struct mlx5_dev_config {
193 unsigned int hw_csum:1; /* Checksum offload is supported. */
194 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */
195 unsigned int hw_vlan_insert:1; /* VLAN insertion in WQE is supported. */
196 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */
197 unsigned int hw_padding:1; /* End alignment padding is supported. */
198 unsigned int vf:1; /* This is a VF. */
199 unsigned int tunnel_en:1;
200 /* Whether tunnel stateless offloads are supported. */
201 unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */
202 unsigned int cqe_comp:1; /* CQE compression is enabled. */
203 unsigned int cqe_pad:1; /* CQE padding is enabled. */
204 unsigned int tso:1; /* Whether TSO is supported. */
205 unsigned int rx_vec_en:1; /* Rx vector is enabled. */
206 unsigned int mr_ext_memseg_en:1;
207 /* Whether memseg should be extended for MR creation. */
208 unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */
209 unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */
210 unsigned int dv_esw_en:1; /* Enable E-Switch DV flow. */
211 unsigned int dv_flow_en:1; /* Enable DV flow. */
212 unsigned int dv_xmeta_en:2; /* Enable extensive flow metadata. */
213 unsigned int lacp_by_user:1;
214 /* Enable user to manage LACP traffic. */
215 unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */
216 unsigned int devx:1; /* Whether devx interface is available or not. */
217 unsigned int dest_tir:1; /* Whether advanced DR API is available. */
218 unsigned int reclaim_mode:2; /* Memory reclaim mode. */
219 unsigned int rt_timestamp:1; /* realtime timestamp format. */
221 unsigned int enabled:1; /* Whether MPRQ is enabled. */
222 unsigned int stride_num_n; /* Number of strides. */
223 unsigned int stride_size_n; /* Size of a stride. */
224 unsigned int min_stride_size_n; /* Min size of a stride. */
225 unsigned int max_stride_size_n; /* Max size of a stride. */
226 unsigned int max_memcpy_len;
227 /* Maximum packet size to memcpy Rx packets. */
228 unsigned int min_rxqs_num;
229 /* Rx queue count threshold to enable MPRQ. */
230 } mprq; /* Configurations for Multi-Packet RQ. */
231 int mps; /* Multi-packet send supported mode. */
232 int dbnc; /* Skip doorbell register write barrier. */
233 unsigned int flow_prio; /* Number of flow priorities. */
234 enum modify_reg flow_mreg_c[MLX5_MREG_C_NUM];
235 /* Availibility of mreg_c's. */
236 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */
237 unsigned int ind_table_max_size; /* Maximum indirection table size. */
238 unsigned int max_dump_files_num; /* Maximum dump files per queue. */
239 unsigned int log_hp_size; /* Single hairpin queue data size in total. */
240 int txqs_inline; /* Queue number threshold for inlining. */
241 int txq_inline_min; /* Minimal amount of data bytes to inline. */
242 int txq_inline_max; /* Max packet size for inlining with SEND. */
243 int txq_inline_mpw; /* Max packet size for inlining with eMPW. */
244 int tx_pp; /* Timestamp scheduling granularity in nanoseconds. */
245 int tx_skew; /* Tx scheduling skew between WQE and data on wire. */
246 struct mlx5_hca_attr hca_attr; /* HCA attributes. */
247 struct mlx5_lro_config lro; /* LRO configuration. */
252 * Type of object being allocated.
254 enum mlx5_verbs_alloc_type {
255 MLX5_VERBS_ALLOC_TYPE_NONE,
256 MLX5_VERBS_ALLOC_TYPE_TX_QUEUE,
257 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE,
260 /* Structure for VF VLAN workaround. */
261 struct mlx5_vf_vlan {
267 * Verbs allocator needs a context to know in the callback which kind of
268 * resources it is allocating.
270 struct mlx5_verbs_alloc_ctx {
271 enum mlx5_verbs_alloc_type type; /* Kind of object being allocated. */
272 const void *obj; /* Pointer to the DPDK object. */
275 /* Flow drop context necessary due to Verbs API. */
277 struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */
278 struct mlx5_rxq_obj *rxq; /* Rx queue object. */
281 #define MLX5_COUNTERS_PER_POOL 512
282 #define MLX5_MAX_PENDING_QUERIES 4
283 #define MLX5_CNT_CONTAINER_RESIZE 64
284 #define MLX5_CNT_AGE_OFFSET 0x80000000
285 #define CNT_SIZE (sizeof(struct mlx5_flow_counter))
286 #define CNTEXT_SIZE (sizeof(struct mlx5_flow_counter_ext))
287 #define AGE_SIZE (sizeof(struct mlx5_age_param))
288 #define MLX5_AGING_TIME_DELAY 7
289 #define CNT_POOL_TYPE_EXT (1 << 0)
290 #define CNT_POOL_TYPE_AGE (1 << 1)
291 #define IS_EXT_POOL(pool) (((pool)->type) & CNT_POOL_TYPE_EXT)
292 #define IS_AGE_POOL(pool) (((pool)->type) & CNT_POOL_TYPE_AGE)
293 #define MLX_CNT_IS_AGE(counter) ((counter) & MLX5_CNT_AGE_OFFSET ? 1 : 0)
294 #define MLX5_CNT_LEN(pool) \
296 (IS_AGE_POOL(pool) ? AGE_SIZE : 0) + \
297 (IS_EXT_POOL(pool) ? CNTEXT_SIZE : 0))
298 #define MLX5_POOL_GET_CNT(pool, index) \
299 ((struct mlx5_flow_counter *) \
300 ((uint8_t *)((pool) + 1) + (index) * (MLX5_CNT_LEN(pool))))
301 #define MLX5_CNT_ARRAY_IDX(pool, cnt) \
302 ((int)(((uint8_t *)(cnt) - (uint8_t *)((pool) + 1)) / \
305 * The pool index and offset of counter in the pool array makes up the
306 * counter index. In case the counter is from pool 0 and offset 0, it
307 * should plus 1 to avoid index 0, since 0 means invalid counter index
310 #define MLX5_MAKE_CNT_IDX(pi, offset) \
311 ((pi) * MLX5_COUNTERS_PER_POOL + (offset) + 1)
312 #define MLX5_CNT_TO_CNT_EXT(pool, cnt) \
313 ((struct mlx5_flow_counter_ext *)\
314 ((uint8_t *)((cnt) + 1) + \
315 (IS_AGE_POOL(pool) ? AGE_SIZE : 0)))
316 #define MLX5_GET_POOL_CNT_EXT(pool, offset) \
317 MLX5_CNT_TO_CNT_EXT(pool, MLX5_POOL_GET_CNT((pool), (offset)))
318 #define MLX5_CNT_TO_AGE(cnt) \
319 ((struct mlx5_age_param *)((cnt) + 1))
321 * The maximum single counter is 0x800000 as MLX5_CNT_BATCH_OFFSET
322 * defines. The pool size is 512, pool index should never reach
325 #define POOL_IDX_INVALID UINT16_MAX
327 struct mlx5_flow_counter_pool;
331 AGE_FREE, /* Initialized state. */
332 AGE_CANDIDATE, /* Counter assigned to flows. */
333 AGE_TMOUT, /* Timeout, wait for rte_flow_get_aged_flows and destroy. */
336 #define MLX5_CNT_CONTAINER(sh, batch, age) (&(sh)->cmng.ccont \
337 [(batch) * 2 + (age)])
340 MLX5_CCONT_TYPE_SINGLE,
341 MLX5_CCONT_TYPE_SINGLE_FOR_AGE,
342 MLX5_CCONT_TYPE_BATCH,
343 MLX5_CCONT_TYPE_BATCH_FOR_AGE,
347 /* Counter age parameter. */
348 struct mlx5_age_param {
349 rte_atomic16_t state; /**< Age state. */
350 uint16_t port_id; /**< Port id of the counter. */
351 uint32_t timeout:15; /**< Age timeout in unit of 0.1sec. */
352 uint32_t expire:16; /**< Expire time(0.1sec) in the future. */
353 void *context; /**< Flow counter age context. */
356 struct flow_counter_stats {
361 struct mlx5_flow_counter_pool;
362 /* Generic counters information. */
363 struct mlx5_flow_counter {
364 TAILQ_ENTRY(mlx5_flow_counter) next;
365 /**< Pointer to the next flow counter structure. */
367 uint64_t hits; /**< Reset value of hits packets. */
368 struct mlx5_flow_counter_pool *pool; /**< Counter pool. */
370 uint64_t bytes; /**< Reset value of bytes. */
371 void *action; /**< Pointer to the dv action. */
374 /* Extend counters information for none batch counters. */
375 struct mlx5_flow_counter_ext {
376 uint32_t shared:1; /**< Share counter ID with other flow rules. */
378 /**< Whether the counter was allocated by batch command. */
379 uint32_t ref_cnt:30; /**< Reference counter. */
380 uint32_t id; /**< User counter ID. */
381 union { /**< Holds the counters for the rule. */
382 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42)
383 struct ibv_counter_set *cs;
384 #elif defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
385 struct ibv_counters *cs;
387 struct mlx5_devx_obj *dcs; /**< Counter Devx object. */
391 TAILQ_HEAD(mlx5_counters, mlx5_flow_counter);
393 /* Generic counter pool structure - query is in pool resolution. */
394 struct mlx5_flow_counter_pool {
395 TAILQ_ENTRY(mlx5_flow_counter_pool) next;
396 struct mlx5_counters counters[2]; /* Free counter list. */
398 struct mlx5_devx_obj *min_dcs;
399 rte_atomic64_t a64_dcs;
401 /* The devx object of the minimum counter ID. */
402 uint32_t index:29; /* Pool index in container. */
403 uint32_t type:2; /* Memory type behind the counter array. */
404 volatile uint32_t query_gen:1; /* Query round. */
405 rte_spinlock_t sl; /* The pool lock. */
406 struct mlx5_counter_stats_raw *raw;
407 struct mlx5_counter_stats_raw *raw_hw; /* The raw on HW working. */
410 struct mlx5_counter_stats_raw;
412 /* Memory management structure for group of counter statistics raws. */
413 struct mlx5_counter_stats_mem_mng {
414 LIST_ENTRY(mlx5_counter_stats_mem_mng) next;
415 struct mlx5_counter_stats_raw *raws;
416 struct mlx5_devx_obj *dm;
420 /* Raw memory structure for the counter statistics values of a pool. */
421 struct mlx5_counter_stats_raw {
422 LIST_ENTRY(mlx5_counter_stats_raw) next;
424 struct mlx5_counter_stats_mem_mng *mem_mng;
425 volatile struct flow_counter_stats *data;
428 TAILQ_HEAD(mlx5_counter_pools, mlx5_flow_counter_pool);
430 /* Container structure for counter pools. */
431 struct mlx5_pools_container {
432 rte_atomic16_t n_valid; /* Number of valid pools. */
433 uint16_t n; /* Number of pools. */
434 uint16_t last_pool_idx; /* Last used pool index */
435 int min_id; /* The minimum counter ID in the pools. */
436 int max_id; /* The maximum counter ID in the pools. */
437 rte_spinlock_t resize_sl; /* The resize lock. */
438 rte_spinlock_t csl; /* The counter free list lock. */
439 struct mlx5_counters counters; /* Free counter list. */
440 struct mlx5_counter_pools pool_list; /* Counter pool list. */
441 struct mlx5_flow_counter_pool **pools; /* Counter pool array. */
442 struct mlx5_counter_stats_mem_mng *mem_mng;
443 /* Hold the memory management for the next allocated pools raws. */
446 /* Counter global management structure. */
447 struct mlx5_flow_counter_mng {
448 struct mlx5_pools_container ccont[MLX5_CCONT_TYPE_MAX];
449 struct mlx5_counters flow_counters; /* Legacy flow counter list. */
450 uint8_t pending_queries;
454 uint8_t query_thread_on;
455 LIST_HEAD(mem_mngs, mlx5_counter_stats_mem_mng) mem_mngs;
456 LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws;
459 /* Default miss action resource structure. */
460 struct mlx5_flow_default_miss_resource {
461 void *action; /* Pointer to the rdma-core action. */
462 rte_atomic32_t refcnt; /* Default miss action reference counter. */
465 #define MLX5_AGE_EVENT_NEW 1
466 #define MLX5_AGE_TRIGGER 2
467 #define MLX5_AGE_SET(age_info, BIT) \
468 ((age_info)->flags |= (1 << (BIT)))
469 #define MLX5_AGE_GET(age_info, BIT) \
470 ((age_info)->flags & (1 << (BIT)))
471 #define GET_PORT_AGE_INFO(priv) \
472 (&((priv)->sh->port[(priv)->dev_port - 1].age_info))
474 /* Aging information for per port. */
475 struct mlx5_age_info {
476 uint8_t flags; /*Indicate if is new event or need be trigered*/
477 struct mlx5_counters aged_counters; /* Aged flow counter list. */
478 rte_spinlock_t aged_sl; /* Aged flow counter list lock. */
481 /* Per port data of shared IB device. */
482 struct mlx5_dev_shared_port {
484 uint32_t devx_ih_port_id;
486 * Interrupt handler port_id. Used by shared interrupt
487 * handler to find the corresponding rte_eth device
488 * by IB port index. If value is equal or greater
489 * RTE_MAX_ETHPORTS it means there is no subhandler
490 * installed for specified IB port index.
492 struct mlx5_age_info age_info;
493 /* Aging information for per port. */
496 /* Table key of the hash organization. */
497 union mlx5_flow_tbl_key {
499 /* Table ID should be at the lowest address. */
500 uint32_t table_id; /**< ID of the table. */
501 uint16_t reserved; /**< must be zero for comparison. */
502 uint8_t domain; /**< 1 - FDB, 0 - NIC TX/RX. */
503 uint8_t direction; /**< 1 - egress, 0 - ingress. */
505 uint64_t v64; /**< full 64bits value of key */
508 /* Table structure. */
509 struct mlx5_flow_tbl_resource {
510 void *obj; /**< Pointer to DR table object. */
511 rte_atomic32_t refcnt; /**< Reference counter. */
514 #define MLX5_MAX_TABLES UINT16_MAX
515 #define MLX5_FLOW_TABLE_LEVEL_METER (UINT16_MAX - 3)
516 #define MLX5_FLOW_TABLE_LEVEL_SUFFIX (UINT16_MAX - 2)
517 #define MLX5_HAIRPIN_TX_TABLE (UINT16_MAX - 1)
518 /* Reserve the last two tables for metadata register copy. */
519 #define MLX5_FLOW_MREG_ACT_TABLE_GROUP (MLX5_MAX_TABLES - 1)
520 #define MLX5_FLOW_MREG_CP_TABLE_GROUP (MLX5_MAX_TABLES - 2)
521 /* Tables for metering splits should be added here. */
522 #define MLX5_MAX_TABLES_EXTERNAL (MLX5_MAX_TABLES - 3)
523 #define MLX5_MAX_TABLES_FDB UINT16_MAX
525 /* ID generation structure. */
526 struct mlx5_flow_id_pool {
527 uint32_t *free_arr; /**< Pointer to the a array of free values. */
529 /**< The next index that can be used without any free elements. */
530 uint32_t *curr; /**< Pointer to the index to pop. */
531 uint32_t *last; /**< Pointer to the last element in the empty arrray. */
532 uint32_t max_id; /**< Maximum id can be allocated from the pool. */
535 /* Tx pacing queue structure - for Clock and Rearm queues. */
536 struct mlx5_txpp_wq {
537 /* Completion Queue related data.*/
538 struct mlx5_devx_obj *cq;
539 struct mlx5dv_devx_umem *cq_umem;
541 volatile void *cq_buf;
542 volatile struct mlx5_cqe *cqes;
544 volatile uint32_t *cq_dbrec;
547 /* Send Queue related data.*/
548 struct mlx5_devx_obj *sq;
549 struct mlx5dv_devx_umem *sq_umem;
551 volatile void *sq_buf;
552 volatile struct mlx5_wqe *wqes;
554 uint16_t sq_size; /* Number of WQEs in the queue. */
555 uint16_t sq_ci; /* Next WQE to execute. */
556 volatile uint32_t *sq_dbrec;
559 /* Tx packet pacing internal timestamp. */
560 struct mlx5_txpp_ts {
561 rte_atomic64_t ci_ts;
565 /* Tx packet pacing structure. */
566 struct mlx5_dev_txpp {
567 pthread_mutex_t mutex; /* Pacing create/destroy mutex. */
568 uint32_t refcnt; /* Pacing reference counter. */
569 uint32_t freq; /* Timestamp frequency, Hz. */
570 uint32_t tick; /* Completion tick duration in nanoseconds. */
571 uint32_t test; /* Packet pacing test mode. */
572 int32_t skew; /* Scheduling skew. */
573 uint32_t eqn; /* Event Queue number. */
574 struct rte_intr_handle intr_handle; /* Periodic interrupt. */
575 struct mlx5dv_devx_event_channel *echan; /* Event Channel. */
576 struct mlx5_txpp_wq clock_queue; /* Clock Queue. */
577 struct mlx5_txpp_wq rearm_queue; /* Clock Queue. */
578 struct mlx5dv_pp *pp; /* Packet pacing context. */
579 uint16_t pp_id; /* Packet pacing context index. */
580 uint16_t ts_n; /* Number of captured timestamps. */
581 uint16_t ts_p; /* Pointer to statisticks timestamp. */
582 struct mlx5_txpp_ts *tsa; /* Timestamps sliding window stats. */
583 struct mlx5_txpp_ts ts; /* Cached completion id/timestamp. */
584 uint32_t sync_lost:1; /* ci/timestamp synchronization lost. */
585 /* Statistics counters. */
586 rte_atomic32_t err_miss_int; /* Missed service interrupt. */
587 rte_atomic32_t err_rearm_queue; /* Rearm Queue errors. */
588 rte_atomic32_t err_clock_queue; /* Clock Queue errors. */
589 rte_atomic32_t err_ts_past; /* Timestamp in the past. */
590 rte_atomic32_t err_ts_future; /* Timestamp in the distant future. */
593 /* Supported flex parser profile ID. */
594 enum mlx5_flex_parser_profile_id {
595 MLX5_FLEX_PARSER_ECPRI_0 = 0,
596 MLX5_FLEX_PARSER_MAX = 8,
599 /* Sample ID information of flex parser structure. */
600 struct mlx5_flex_parser_profiles {
601 uint32_t num; /* Actual number of samples. */
602 uint32_t ids[8]; /* Sample IDs for this profile. */
603 uint8_t offset[8]; /* Bytes offset of each parser. */
604 void *obj; /* Flex parser node object. */
608 * Shared Infiniband device context for Master/Representors
609 * which belong to same IB device with multiple IB ports.
611 struct mlx5_dev_ctx_shared {
612 LIST_ENTRY(mlx5_dev_ctx_shared) next;
614 uint32_t devx:1; /* Opened with DV. */
615 uint32_t max_port; /* Maximal IB device port index. */
616 void *ctx; /* Verbs/DV/DevX context. */
617 void *pd; /* Protection Domain. */
618 uint32_t pdn; /* Protection Domain number. */
619 uint32_t tdn; /* Transport Domain number. */
620 char ibdev_name[DEV_SYSFS_NAME_MAX]; /* SYSFS dev name. */
621 char ibdev_path[DEV_SYSFS_PATH_MAX]; /* SYSFS dev path for secondary */
622 struct mlx5_dev_attr device_attr; /* Device properties. */
623 int numa_node; /* Numa node of backing physical device. */
624 LIST_ENTRY(mlx5_dev_ctx_shared) mem_event_cb;
625 /**< Called by memory event callback. */
626 struct mlx5_mr_share_cache share_cache;
627 /* Packet pacing related structure. */
628 struct mlx5_dev_txpp txpp;
629 /* Shared DV/DR flow data section. */
630 pthread_mutex_t dv_mutex; /* DV context mutex. */
631 uint32_t dv_meta_mask; /* flow META metadata supported mask. */
632 uint32_t dv_mark_mask; /* flow MARK metadata supported mask. */
633 uint32_t dv_regc0_mask; /* available bits of metatada reg_c[0]. */
634 uint32_t dv_refcnt; /* DV/DR data reference counter. */
635 void *fdb_domain; /* FDB Direct Rules name space handle. */
636 void *rx_domain; /* RX Direct Rules name space handle. */
637 void *tx_domain; /* TX Direct Rules name space handle. */
639 rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */
640 rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX];
641 /* UAR same-page access control required in 32bit implementations. */
643 struct mlx5_hlist *flow_tbls;
644 /* Direct Rules tables for FDB, NIC TX+RX */
645 void *esw_drop_action; /* Pointer to DR E-Switch drop action. */
646 void *pop_vlan_action; /* Pointer to DR pop VLAN action. */
647 uint32_t encaps_decaps; /* Encap/decap action indexed memory list. */
648 LIST_HEAD(modify_cmd, mlx5_flow_dv_modify_hdr_resource) modify_cmds;
649 struct mlx5_hlist *tag_table;
650 uint32_t port_id_action_list; /* List of port ID actions. */
651 uint32_t push_vlan_action_list; /* List of push VLAN actions. */
652 struct mlx5_flow_counter_mng cmng; /* Counters management structure. */
653 struct mlx5_flow_default_miss_resource default_miss;
654 /* Default miss action resource structure. */
655 struct mlx5_indexed_pool *ipool[MLX5_IPOOL_MAX];
656 /* Memory Pool for mlx5 flow resources. */
657 struct mlx5_l3t_tbl *cnt_id_tbl; /* Shared counter lookup table. */
658 /* Shared interrupt handler section. */
659 struct rte_intr_handle intr_handle; /* Interrupt handler for device. */
660 struct rte_intr_handle intr_handle_devx; /* DEVX interrupt handler. */
661 void *devx_comp; /* DEVX async comp obj. */
662 struct mlx5_devx_obj *tis; /* TIS object. */
663 struct mlx5_devx_obj *td; /* Transport domain. */
664 struct mlx5_flow_id_pool *flow_id_pool; /* Flow ID pool. */
665 struct mlx5dv_devx_uar *tx_uar; /* Tx/packer pacing shared UAR. */
666 struct mlx5_flex_parser_profiles fp[MLX5_FLEX_PARSER_MAX];
667 /* Flex parser profiles information. */
668 struct mlx5_dev_shared_port port[]; /* per device port data array. */
671 /* Per-process private structure. */
672 struct mlx5_proc_priv {
674 /* Size of UAR register table. */
676 /* Table of UAR registers for each process. */
679 /* MTR profile list. */
680 TAILQ_HEAD(mlx5_mtr_profiles, mlx5_flow_meter_profile);
682 TAILQ_HEAD(mlx5_flow_meters, mlx5_flow_meter);
684 #define MLX5_PROC_PRIV(port_id) \
685 ((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private)
688 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */
689 struct mlx5_dev_ctx_shared *sh; /* Shared device context. */
690 uint32_t dev_port; /* Device port number. */
691 struct rte_pci_device *pci_dev; /* Backend PCI device. */
692 struct rte_ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */
693 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES);
694 /* Bit-field of MAC addresses owned by the PMD. */
695 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */
696 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */
697 /* Device properties. */
698 uint16_t mtu; /* Configured MTU. */
699 unsigned int isolated:1; /* Whether isolated mode is enabled. */
700 unsigned int representor:1; /* Device is a port representor. */
701 unsigned int master:1; /* Device is a E-Switch master. */
702 unsigned int dr_shared:1; /* DV/DR data is shared. */
703 unsigned int txpp_en:1; /* Tx packet pacing enabled. */
704 unsigned int counter_fallback:1; /* Use counter fallback management. */
705 unsigned int mtr_en:1; /* Whether support meter. */
706 unsigned int mtr_reg_share:1; /* Whether support meter REG_C share. */
707 uint16_t domain_id; /* Switch domain identifier. */
708 uint16_t vport_id; /* Associated VF vport index (if any). */
709 uint32_t vport_meta_tag; /* Used for vport index match ove VF LAG. */
710 uint32_t vport_meta_mask; /* Used for vport index field match mask. */
711 int32_t representor_id; /* Port representor identifier. */
712 int32_t pf_bond; /* >=0 means PF index in bonding configuration. */
713 unsigned int if_index; /* Associated kernel network device index. */
715 unsigned int rxqs_n; /* RX queues array size. */
716 unsigned int txqs_n; /* TX queues array size. */
717 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */
718 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */
719 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
720 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */
721 unsigned int (*reta_idx)[]; /* RETA index table. */
722 unsigned int reta_idx_n; /* RETA index size. */
723 struct mlx5_drop drop_queue; /* Flow drop queues. */
724 uint32_t flows; /* RTE Flow rules. */
725 uint32_t ctrl_flows; /* Control flow rules. */
726 void *inter_flows; /* Intermediate resources for flow creation. */
727 void *rss_desc; /* Intermediate rss description resources. */
728 int flow_idx; /* Intermediate device flow index. */
729 int flow_nested_idx; /* Intermediate device flow index, nested. */
730 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */
731 LIST_HEAD(rxqobj, mlx5_rxq_obj) rxqsobj; /* Verbs/DevX Rx queues. */
732 uint32_t hrxqs; /* Verbs Hash Rx queues. */
733 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */
734 LIST_HEAD(txqobj, mlx5_txq_obj) txqsobj; /* Verbs/DevX Tx queues. */
735 /* Indirection tables. */
736 LIST_HEAD(ind_tables, mlx5_ind_table_obj) ind_tbls;
737 /* Pointer to next element. */
738 rte_atomic32_t refcnt; /**< Reference counter. */
739 struct ibv_flow_action *verbs_action;
740 /**< Verbs modify header action object. */
741 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
742 uint8_t max_lro_msg_size;
743 /* Tags resources cache. */
744 uint32_t link_speed_capa; /* Link speed capabilities. */
745 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */
746 struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */
747 struct mlx5_dev_config config; /* Device configuration. */
748 struct mlx5_verbs_alloc_ctx verbs_alloc_ctx;
749 /* Context for Verbs allocator. */
750 int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */
751 int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */
752 struct mlx5_dbr_page_list dbrpgs; /* Door-bell pages. */
753 struct mlx5_nl_vlan_vmwa_context *vmwa_context; /* VLAN WA context. */
754 struct mlx5_flow_id_pool *qrss_id_pool;
755 struct mlx5_hlist *mreg_cp_tbl;
756 /* Hash table of Rx metadata register copy table. */
757 uint8_t mtr_sfx_reg; /* Meter prefix-suffix flow match REG_C. */
758 uint8_t mtr_color_reg; /* Meter color match REG_C. */
759 struct mlx5_mtr_profiles flow_meter_profiles; /* MTR profile list. */
760 struct mlx5_flow_meters flow_meters; /* MTR list. */
761 uint8_t skip_default_rss_reta; /* Skip configuration of default reta. */
762 uint8_t fdb_def_rule; /* Whether fdb jump to table 1 is configured. */
763 struct mlx5_mp_id mp_id; /* ID of a multi-process process */
764 LIST_HEAD(fdir, mlx5_fdir_flow) fdir_flows; /* fdir flows. */
767 #define PORT_ID(priv) ((priv)->dev_data->port_id)
768 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)])
772 int mlx5_getenv_int(const char *);
773 int mlx5_proc_priv_init(struct rte_eth_dev *dev);
774 int mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev,
775 struct rte_eth_udp_tunnel *udp_tunnel);
776 uint16_t mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev);
777 void mlx5_dev_close(struct rte_eth_dev *dev);
779 /* Macro to iterate over all valid ports for mlx5 driver. */
780 #define MLX5_ETH_FOREACH_DEV(port_id, pci_dev) \
781 for (port_id = mlx5_eth_find_next(0, pci_dev); \
782 port_id < RTE_MAX_ETHPORTS; \
783 port_id = mlx5_eth_find_next(port_id + 1, pci_dev))
784 int mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs);
785 struct mlx5_dev_ctx_shared *
786 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
787 const struct mlx5_dev_config *config);
788 void mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh);
789 void mlx5_free_table_hash_list(struct mlx5_priv *priv);
790 int mlx5_alloc_table_hash_list(struct mlx5_priv *priv);
791 void mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
792 struct mlx5_dev_config *config);
793 void mlx5_set_metadata_mask(struct rte_eth_dev *dev);
794 int mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
795 struct mlx5_dev_config *config);
796 int mlx5_init_once(void);
797 int mlx5_dev_configure(struct rte_eth_dev *dev);
798 int mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info);
799 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size);
800 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
801 int mlx5_hairpin_cap_get(struct rte_eth_dev *dev,
802 struct rte_eth_hairpin_cap *cap);
803 bool mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev);
804 int mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev);
808 int mlx5_dev_configure(struct rte_eth_dev *dev);
809 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver,
811 int mlx5_dev_infos_get(struct rte_eth_dev *dev,
812 struct rte_eth_dev_info *info);
813 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev);
814 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
815 int mlx5_hairpin_cap_get(struct rte_eth_dev *dev,
816 struct rte_eth_hairpin_cap *cap);
818 /* mlx5_ethdev_os.c */
820 int mlx5_get_ifname(const struct rte_eth_dev *dev, char (*ifname)[IF_NAMESIZE]);
821 unsigned int mlx5_ifindex(const struct rte_eth_dev *dev);
822 int mlx5_ifreq(const struct rte_eth_dev *dev, int req, struct ifreq *ifr);
823 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu);
824 int mlx5_set_flags(struct rte_eth_dev *dev, unsigned int keep,
826 int mlx5_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
827 int mlx5_read_clock(struct rte_eth_dev *dev, uint64_t *clock);
828 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete);
829 int mlx5_force_link_status_change(struct rte_eth_dev *dev, int status);
830 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev,
831 struct rte_eth_fc_conf *fc_conf);
832 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev,
833 struct rte_eth_fc_conf *fc_conf);
834 void mlx5_dev_link_status_handler(void *arg);
835 void mlx5_dev_interrupt_handler(void *arg);
836 void mlx5_dev_interrupt_handler_devx(void *arg);
837 void mlx5_dev_interrupt_handler_uninstall(struct rte_eth_dev *dev);
838 void mlx5_dev_interrupt_handler_install(struct rte_eth_dev *dev);
839 int mlx5_set_link_down(struct rte_eth_dev *dev);
840 int mlx5_set_link_up(struct rte_eth_dev *dev);
841 int mlx5_is_removed(struct rte_eth_dev *dev);
842 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev);
843 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev);
844 struct mlx5_priv *mlx5_port_to_eswitch_info(uint16_t port, bool valid);
845 struct mlx5_priv *mlx5_dev_to_eswitch_info(struct rte_eth_dev *dev);
846 int mlx5_sysfs_switch_info(unsigned int ifindex,
847 struct mlx5_switch_info *info);
848 void mlx5_sysfs_check_switch_info(bool device_dir,
849 struct mlx5_switch_info *switch_info);
850 void mlx5_translate_port_name(const char *port_name_in,
851 struct mlx5_switch_info *port_info_out);
852 void mlx5_intr_callback_unregister(const struct rte_intr_handle *handle,
853 rte_intr_callback_fn cb_fn, void *cb_arg);
854 int mlx5_get_module_info(struct rte_eth_dev *dev,
855 struct rte_eth_dev_module_info *modinfo);
856 int mlx5_get_module_eeprom(struct rte_eth_dev *dev,
857 struct rte_dev_eeprom_info *info);
858 int mlx5_dev_configure_rss_reta(struct rte_eth_dev *dev);
862 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]);
863 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
864 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
865 uint32_t index, uint32_t vmdq);
866 struct mlx5_nl_vlan_vmwa_context *mlx5_vlan_vmwa_init
867 (struct rte_eth_dev *dev, uint32_t ifindex);
868 int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr);
869 int mlx5_set_mc_addr_list(struct rte_eth_dev *dev,
870 struct rte_ether_addr *mc_addr_set,
871 uint32_t nb_mc_addr);
875 int mlx5_rss_hash_update(struct rte_eth_dev *dev,
876 struct rte_eth_rss_conf *rss_conf);
877 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev,
878 struct rte_eth_rss_conf *rss_conf);
879 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size);
880 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev,
881 struct rte_eth_rss_reta_entry64 *reta_conf,
883 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev,
884 struct rte_eth_rss_reta_entry64 *reta_conf,
889 int mlx5_promiscuous_enable(struct rte_eth_dev *dev);
890 int mlx5_promiscuous_disable(struct rte_eth_dev *dev);
891 int mlx5_allmulticast_enable(struct rte_eth_dev *dev);
892 int mlx5_allmulticast_disable(struct rte_eth_dev *dev);
896 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
897 int mlx5_stats_reset(struct rte_eth_dev *dev);
898 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats,
900 int mlx5_xstats_reset(struct rte_eth_dev *dev);
901 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
902 struct rte_eth_xstat_name *xstats_names,
907 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
908 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on);
909 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask);
910 void mlx5_vlan_vmwa_exit(struct mlx5_nl_vlan_vmwa_context *ctx);
911 void mlx5_vlan_vmwa_release(struct rte_eth_dev *dev,
912 struct mlx5_vf_vlan *vf_vlan);
913 void mlx5_vlan_vmwa_acquire(struct rte_eth_dev *dev,
914 struct mlx5_vf_vlan *vf_vlan);
918 int mlx5_dev_start(struct rte_eth_dev *dev);
919 void mlx5_dev_stop(struct rte_eth_dev *dev);
920 int mlx5_traffic_enable(struct rte_eth_dev *dev);
921 void mlx5_traffic_disable(struct rte_eth_dev *dev);
922 int mlx5_traffic_restart(struct rte_eth_dev *dev);
926 int mlx5_flow_discover_mreg_c(struct rte_eth_dev *eth_dev);
927 bool mlx5_flow_ext_mreg_supported(struct rte_eth_dev *dev);
928 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
929 void mlx5_flow_print(struct rte_flow *flow);
930 int mlx5_flow_validate(struct rte_eth_dev *dev,
931 const struct rte_flow_attr *attr,
932 const struct rte_flow_item items[],
933 const struct rte_flow_action actions[],
934 struct rte_flow_error *error);
935 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev,
936 const struct rte_flow_attr *attr,
937 const struct rte_flow_item items[],
938 const struct rte_flow_action actions[],
939 struct rte_flow_error *error);
940 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow,
941 struct rte_flow_error *error);
942 void mlx5_flow_list_flush(struct rte_eth_dev *dev, uint32_t *list, bool active);
943 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error);
944 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow,
945 const struct rte_flow_action *action, void *data,
946 struct rte_flow_error *error);
947 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable,
948 struct rte_flow_error *error);
949 int mlx5_dev_filter_ctrl(struct rte_eth_dev *dev,
950 enum rte_filter_type filter_type,
951 enum rte_filter_op filter_op,
953 int mlx5_flow_start(struct rte_eth_dev *dev, uint32_t *list);
954 void mlx5_flow_stop(struct rte_eth_dev *dev, uint32_t *list);
955 int mlx5_flow_start_default(struct rte_eth_dev *dev);
956 void mlx5_flow_stop_default(struct rte_eth_dev *dev);
957 void mlx5_flow_alloc_intermediate(struct rte_eth_dev *dev);
958 void mlx5_flow_free_intermediate(struct rte_eth_dev *dev);
959 int mlx5_flow_verify(struct rte_eth_dev *dev);
960 int mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, uint32_t queue);
961 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev,
962 struct rte_flow_item_eth *eth_spec,
963 struct rte_flow_item_eth *eth_mask,
964 struct rte_flow_item_vlan *vlan_spec,
965 struct rte_flow_item_vlan *vlan_mask);
966 int mlx5_ctrl_flow(struct rte_eth_dev *dev,
967 struct rte_flow_item_eth *eth_spec,
968 struct rte_flow_item_eth *eth_mask);
969 int mlx5_flow_lacp_miss(struct rte_eth_dev *dev);
970 struct rte_flow *mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev);
971 int mlx5_flow_create_drop_queue(struct rte_eth_dev *dev);
972 void mlx5_flow_delete_drop_queue(struct rte_eth_dev *dev);
973 void mlx5_flow_async_pool_query_handle(struct mlx5_dev_ctx_shared *sh,
974 uint64_t async_id, int status);
975 void mlx5_set_query_alarm(struct mlx5_dev_ctx_shared *sh);
976 void mlx5_flow_query_alarm(void *arg);
977 uint32_t mlx5_counter_alloc(struct rte_eth_dev *dev);
978 void mlx5_counter_free(struct rte_eth_dev *dev, uint32_t cnt);
979 int mlx5_counter_query(struct rte_eth_dev *dev, uint32_t cnt,
980 bool clear, uint64_t *pkts, uint64_t *bytes);
981 int mlx5_flow_dev_dump(struct rte_eth_dev *dev, FILE *file,
982 struct rte_flow_error *error);
983 void mlx5_flow_rxq_dynf_metadata_set(struct rte_eth_dev *dev);
984 int mlx5_flow_get_aged_flows(struct rte_eth_dev *dev, void **contexts,
985 uint32_t nb_contexts, struct rte_flow_error *error);
988 int mlx5_mp_primary_handle(const struct rte_mp_msg *mp_msg, const void *peer);
989 int mlx5_mp_secondary_handle(const struct rte_mp_msg *mp_msg, const void *peer);
990 void mlx5_mp_req_start_rxtx(struct rte_eth_dev *dev);
991 void mlx5_mp_req_stop_rxtx(struct rte_eth_dev *dev);
995 int mlx5_pmd_socket_init(void);
997 /* mlx5_flow_meter.c */
999 int mlx5_flow_meter_ops_get(struct rte_eth_dev *dev, void *arg);
1000 struct mlx5_flow_meter *mlx5_flow_meter_find(struct mlx5_priv *priv,
1002 struct mlx5_flow_meter *mlx5_flow_meter_attach
1003 (struct mlx5_priv *priv,
1005 const struct rte_flow_attr *attr,
1006 struct rte_flow_error *error);
1007 void mlx5_flow_meter_detach(struct mlx5_flow_meter *fm);
1010 struct rte_pci_driver;
1011 int mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *dev_attr);
1012 void mlx5_os_free_shared_dr(struct mlx5_priv *priv);
1013 int mlx5_os_open_device(const struct mlx5_dev_spawn_data *spawn,
1014 const struct mlx5_dev_config *config,
1015 struct mlx5_dev_ctx_shared *sh);
1016 int mlx5_os_get_pdn(void *pd, uint32_t *pdn);
1017 int mlx5_os_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1018 struct rte_pci_device *pci_dev);
1019 void mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh);
1020 void mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh);
1021 int mlx5_os_read_dev_stat(struct mlx5_priv *priv,
1022 const char *ctr_name, uint64_t *stat);
1023 int mlx5_os_read_dev_counters(struct rte_eth_dev *dev, uint64_t *stats);
1024 int mlx5_os_get_stats_n(struct rte_eth_dev *dev);
1025 void mlx5_os_stats_init(struct rte_eth_dev *dev);
1026 void mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb,
1027 mlx5_dereg_mr_t *dereg_mr_cb);
1030 int mlx5_txpp_start(struct rte_eth_dev *dev);
1031 void mlx5_txpp_stop(struct rte_eth_dev *dev);
1032 int mlx5_txpp_read_clock(struct rte_eth_dev *dev, uint64_t *timestamp);
1033 int mlx5_txpp_xstats_get(struct rte_eth_dev *dev,
1034 struct rte_eth_xstat *stats,
1035 unsigned int n, unsigned int n_used);
1036 int mlx5_txpp_xstats_reset(struct rte_eth_dev *dev);
1037 int mlx5_txpp_xstats_get_names(struct rte_eth_dev *dev,
1038 struct rte_eth_xstat_name *xstats_names,
1039 unsigned int n, unsigned int n_used);
1040 void mlx5_txpp_interrupt_handler(void *cb_arg);
1042 #endif /* RTE_PMD_MLX5_H_ */