1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_H_
7 #define RTE_PMD_MLX5_H_
13 #include <sys/queue.h>
16 #include <rte_ether.h>
17 #include <ethdev_driver.h>
18 #include <rte_rwlock.h>
19 #include <rte_interrupts.h>
20 #include <rte_errno.h>
24 #include <mlx5_glue.h>
25 #include <mlx5_devx_cmds.h>
27 #include <mlx5_common_mp.h>
28 #include <mlx5_common_mr.h>
29 #include <mlx5_common_devx.h>
30 #include <mlx5_common_defs.h>
32 #include "mlx5_defs.h"
33 #include "mlx5_utils.h"
35 #include "mlx5_autoconf.h"
38 #define MLX5_SH(dev) (((struct mlx5_priv *)(dev)->data->dev_private)->sh)
41 * Number of modification commands.
42 * The maximal actions amount in FW is some constant, and it is 16 in the
43 * latest releases. In some old releases, it will be limited to 8.
44 * Since there is no interface to query the capacity, the maximal value should
45 * be used to allow PMD to create the flow. The validation will be done in the
46 * lower driver layer or FW. A failure will be returned if exceeds the maximal
47 * supported actions number on the root table.
48 * On non-root tables, there is no limitation, but 32 is enough right now.
50 #define MLX5_MAX_MODIFY_NUM 32
51 #define MLX5_ROOT_TBL_MODIFY_NUM 16
53 /* Maximal number of flex items created on the port.*/
54 #define MLX5_PORT_FLEX_ITEM_NUM 4
56 /* Maximal number of field/field parts to map into sample registers .*/
57 #define MLX5_FLEX_ITEM_MAPPING_NUM 32
59 enum mlx5_ipool_index {
60 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
61 MLX5_IPOOL_DECAP_ENCAP = 0, /* Pool for encap/decap resource. */
62 MLX5_IPOOL_PUSH_VLAN, /* Pool for push vlan resource. */
63 MLX5_IPOOL_TAG, /* Pool for tag resource. */
64 MLX5_IPOOL_PORT_ID, /* Pool for port id resource. */
65 MLX5_IPOOL_JUMP, /* Pool for jump resource. */
66 MLX5_IPOOL_SAMPLE, /* Pool for sample resource. */
67 MLX5_IPOOL_DEST_ARRAY, /* Pool for destination array resource. */
68 MLX5_IPOOL_TUNNEL_ID, /* Pool for tunnel offload context */
69 MLX5_IPOOL_TNL_TBL_ID, /* Pool for tunnel table ID. */
71 MLX5_IPOOL_MTR, /* Pool for meter resource. */
72 MLX5_IPOOL_MCP, /* Pool for metadata resource. */
73 MLX5_IPOOL_HRXQ, /* Pool for hrxq resource. */
74 MLX5_IPOOL_MLX5_FLOW, /* Pool for mlx5 flow handle. */
75 MLX5_IPOOL_RTE_FLOW, /* Pool for rte_flow. */
76 MLX5_IPOOL_RSS_EXPANTION_FLOW_ID, /* Pool for Queue/RSS flow ID. */
77 MLX5_IPOOL_RSS_SHARED_ACTIONS, /* Pool for RSS shared actions. */
78 MLX5_IPOOL_MTR_POLICY, /* Pool for meter policy resource. */
83 * There are three reclaim memory mode supported.
84 * 0(none) means no memory reclaim.
85 * 1(light) means only PMD level reclaim.
86 * 2(aggressive) means both PMD and rdma-core level reclaim.
88 enum mlx5_reclaim_mem_mode {
89 MLX5_RCM_NONE, /* Don't reclaim memory. */
90 MLX5_RCM_LIGHT, /* Reclaim PMD level. */
91 MLX5_RCM_AGGR, /* Reclaim PMD and rdma-core level. */
94 /* The type of flow. */
96 MLX5_FLOW_TYPE_CTL, /* Control flow. */
97 MLX5_FLOW_TYPE_GEN, /* General flow. */
98 MLX5_FLOW_TYPE_MCP, /* MCP flow. */
102 /* Hlist and list callback context. */
103 struct mlx5_flow_cb_ctx {
104 struct rte_eth_dev *dev;
105 struct rte_flow_error *error;
110 /* Device attributes used in mlx5 PMD */
111 struct mlx5_dev_attr {
112 uint64_t device_cap_flags_ex;
122 uint32_t raw_packet_caps;
123 uint32_t max_rwq_indirection_table_size;
125 uint32_t tso_supported_qpts;
128 uint32_t sw_parsing_offloads;
129 uint32_t min_single_stride_log_num_of_bytes;
130 uint32_t max_single_stride_log_num_of_bytes;
131 uint32_t min_single_wqe_log_num_of_strides;
132 uint32_t max_single_wqe_log_num_of_strides;
133 uint32_t stride_supported_qpts;
134 uint32_t tunnel_offloads_caps;
138 /** Data associated with devices to spawn. */
139 struct mlx5_dev_spawn_data {
140 uint32_t ifindex; /**< Network interface index. */
141 uint32_t max_port; /**< Device maximal port index. */
142 uint32_t phys_port; /**< Device physical port index. */
143 int pf_bond; /**< bonding device PF index. < 0 - no bonding */
144 struct mlx5_switch_info info; /**< Switch information. */
145 const char *phys_dev_name; /**< Name of physical device. */
146 struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */
147 struct rte_pci_device *pci_dev; /**< Backend PCI device. */
148 struct mlx5_common_device *cdev; /**< Backend common device. */
149 struct mlx5_bond_info *bond_info;
152 /** Data associated with socket messages. */
153 struct mlx5_flow_dump_req {
154 uint32_t port_id; /**< There are plans in DPDK to extend port_id. */
158 struct mlx5_flow_dump_ack {
159 int rc; /**< Return code. */
162 LIST_HEAD(mlx5_dev_list, mlx5_dev_ctx_shared);
164 /* Shared data between primary and secondary processes. */
165 struct mlx5_shared_data {
167 /* Global spinlock for primary and secondary processes. */
168 int init_done; /* Whether primary has done initialization. */
169 unsigned int secondary_cnt; /* Number of secondary processes init'd. */
172 /* Per-process data structure, not visible to other processes. */
173 struct mlx5_local_data {
174 int init_done; /* Whether a secondary has done initialization. */
177 extern struct mlx5_shared_data *mlx5_shared_data;
179 /* Dev ops structs */
180 extern const struct eth_dev_ops mlx5_dev_ops;
181 extern const struct eth_dev_ops mlx5_dev_sec_ops;
182 extern const struct eth_dev_ops mlx5_dev_ops_isolate;
184 struct mlx5_counter_ctrl {
185 /* Name of the counter. */
186 char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE];
187 /* Name of the counter on the device table. */
188 char ctr_name[RTE_ETH_XSTATS_NAME_SIZE];
189 uint32_t dev:1; /**< Nonzero for dev counters. */
192 struct mlx5_xstats_ctrl {
193 /* Number of device stats. */
195 /* Number of device stats identified by PMD. */
196 uint16_t mlx5_stats_n;
197 /* Index in the device counters table. */
198 uint16_t dev_table_idx[MLX5_MAX_XSTATS];
199 uint64_t base[MLX5_MAX_XSTATS];
200 uint64_t xstats[MLX5_MAX_XSTATS];
201 uint64_t hw_stats[MLX5_MAX_XSTATS];
202 struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS];
205 struct mlx5_stats_ctrl {
206 /* Base for imissed counter. */
207 uint64_t imissed_base;
211 #define MLX5_LRO_SUPPORTED(dev) \
212 (((struct mlx5_priv *)((dev)->data->dev_private))->config.lro.supported)
214 /* Maximal size of coalesced segment for LRO is set in chunks of 256 Bytes. */
215 #define MLX5_LRO_SEG_CHUNK_SIZE 256u
217 /* Maximal size of aggregated LRO packet. */
218 #define MLX5_MAX_LRO_SIZE (UINT8_MAX * MLX5_LRO_SEG_CHUNK_SIZE)
220 /* Maximal number of segments to split. */
221 #define MLX5_MAX_RXQ_NSEG (1u << MLX5_MAX_LOG_RQ_SEGS)
223 /* LRO configurations structure. */
224 struct mlx5_lro_config {
225 uint32_t supported:1; /* Whether LRO is supported. */
226 uint32_t timeout; /* User configuration. */
230 * Device configuration structure.
232 * Merged configuration from:
234 * - Device capabilities,
235 * - User device parameters disabled features.
237 struct mlx5_dev_config {
238 unsigned int hw_csum:1; /* Checksum offload is supported. */
239 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */
240 unsigned int hw_vlan_insert:1; /* VLAN insertion in WQE is supported. */
241 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */
242 unsigned int hw_padding:1; /* End alignment padding is supported. */
243 unsigned int vf:1; /* This is a VF. */
244 unsigned int sf:1; /* This is a SF. */
245 unsigned int tunnel_en:3;
246 /* Whether tunnel stateless offloads are supported. */
247 unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */
248 unsigned int cqe_comp:1; /* CQE compression is enabled. */
249 unsigned int cqe_comp_fmt:3; /* CQE compression format. */
250 unsigned int tso:1; /* Whether TSO is supported. */
251 unsigned int rx_vec_en:1; /* Rx vector is enabled. */
252 unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */
253 unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */
254 unsigned int dv_esw_en:1; /* Enable E-Switch DV flow. */
255 unsigned int dv_flow_en:1; /* Enable DV flow. */
256 unsigned int dv_xmeta_en:2; /* Enable extensive flow metadata. */
257 unsigned int lacp_by_user:1;
258 /* Enable user to manage LACP traffic. */
259 unsigned int swp:3; /* Tx generic tunnel checksum and TSO offload. */
260 unsigned int dest_tir:1; /* Whether advanced DR API is available. */
261 unsigned int reclaim_mode:2; /* Memory reclaim mode. */
262 unsigned int rt_timestamp:1; /* realtime timestamp format. */
263 unsigned int decap_en:1; /* Whether decap will be used or not. */
264 unsigned int dv_miss_info:1; /* restore packet after partial hw miss */
265 unsigned int allow_duplicate_pattern:1;
266 /* Allow/Prevent the duplicate rules pattern. */
268 unsigned int enabled:1; /* Whether MPRQ is enabled. */
269 unsigned int stride_num_n; /* Number of strides. */
270 unsigned int stride_size_n; /* Size of a stride. */
271 unsigned int min_stride_size_n; /* Min size of a stride. */
272 unsigned int max_stride_size_n; /* Max size of a stride. */
273 unsigned int max_memcpy_len;
274 /* Maximum packet size to memcpy Rx packets. */
275 unsigned int min_rxqs_num;
276 /* Rx queue count threshold to enable MPRQ. */
277 } mprq; /* Configurations for Multi-Packet RQ. */
278 int mps; /* Multi-packet send supported mode. */
279 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */
280 unsigned int ind_table_max_size; /* Maximum indirection table size. */
281 unsigned int max_dump_files_num; /* Maximum dump files per queue. */
282 unsigned int log_hp_size; /* Single hairpin queue data size in total. */
283 int txqs_inline; /* Queue number threshold for inlining. */
284 int txq_inline_min; /* Minimal amount of data bytes to inline. */
285 int txq_inline_max; /* Max packet size for inlining with SEND. */
286 int txq_inline_mpw; /* Max packet size for inlining with eMPW. */
287 int tx_pp; /* Timestamp scheduling granularity in nanoseconds. */
288 int tx_skew; /* Tx scheduling skew between WQE and data on wire. */
289 struct mlx5_hca_attr hca_attr; /* HCA attributes. */
290 struct mlx5_lro_config lro; /* LRO configuration. */
294 /* Structure for VF VLAN workaround. */
295 struct mlx5_vf_vlan {
300 /* Flow drop context necessary due to Verbs API. */
302 struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */
303 struct mlx5_rxq_priv *rxq; /* Rx queue. */
306 /* Loopback dummy queue resources required due to Verbs API. */
308 struct ibv_qp *qp; /* QP object. */
309 void *ibv_cq; /* Completion queue. */
310 uint16_t refcnt; /* Reference count for representors. */
313 #define MLX5_COUNTERS_PER_POOL 512
314 #define MLX5_MAX_PENDING_QUERIES 4
315 #define MLX5_CNT_CONTAINER_RESIZE 64
316 #define MLX5_CNT_SHARED_OFFSET 0x80000000
317 #define IS_BATCH_CNT(cnt) (((cnt) & (MLX5_CNT_SHARED_OFFSET - 1)) >= \
318 MLX5_CNT_BATCH_OFFSET)
319 #define MLX5_CNT_SIZE (sizeof(struct mlx5_flow_counter))
320 #define MLX5_AGE_SIZE (sizeof(struct mlx5_age_param))
322 #define MLX5_CNT_LEN(pool) \
324 ((pool)->is_aged ? MLX5_AGE_SIZE : 0))
325 #define MLX5_POOL_GET_CNT(pool, index) \
326 ((struct mlx5_flow_counter *) \
327 ((uint8_t *)((pool) + 1) + (index) * (MLX5_CNT_LEN(pool))))
328 #define MLX5_CNT_ARRAY_IDX(pool, cnt) \
329 ((int)(((uint8_t *)(cnt) - (uint8_t *)((pool) + 1)) / \
332 * The pool index and offset of counter in the pool array makes up the
333 * counter index. In case the counter is from pool 0 and offset 0, it
334 * should plus 1 to avoid index 0, since 0 means invalid counter index
337 #define MLX5_MAKE_CNT_IDX(pi, offset) \
338 ((pi) * MLX5_COUNTERS_PER_POOL + (offset) + 1)
339 #define MLX5_CNT_TO_AGE(cnt) \
340 ((struct mlx5_age_param *)((cnt) + 1))
342 * The maximum single counter is 0x800000 as MLX5_CNT_BATCH_OFFSET
343 * defines. The pool size is 512, pool index should never reach
346 #define POOL_IDX_INVALID UINT16_MAX
350 AGE_FREE, /* Initialized state. */
351 AGE_CANDIDATE, /* Counter assigned to flows. */
352 AGE_TMOUT, /* Timeout, wait for rte_flow_get_aged_flows and destroy. */
355 enum mlx5_counter_type {
356 MLX5_COUNTER_TYPE_ORIGIN,
357 MLX5_COUNTER_TYPE_AGE,
358 MLX5_COUNTER_TYPE_MAX,
361 /* Counter age parameter. */
362 struct mlx5_age_param {
363 uint16_t state; /**< Age state (atomically accessed). */
364 uint16_t port_id; /**< Port id of the counter. */
365 uint32_t timeout:24; /**< Aging timeout in seconds. */
366 uint32_t sec_since_last_hit;
367 /**< Time in seconds since last hit (atomically accessed). */
368 void *context; /**< Flow counter age context. */
371 struct flow_counter_stats {
376 /* Shared counters information for counters. */
377 struct mlx5_flow_counter_shared {
379 uint32_t refcnt; /* Only for shared action management. */
380 uint32_t id; /* User counter ID for legacy sharing. */
384 struct mlx5_flow_counter_pool;
385 /* Generic counters information. */
386 struct mlx5_flow_counter {
389 * User-defined counter shared info is only used during
390 * counter active time. And aging counter sharing is not
391 * supported, so active shared counter will not be chained
392 * to the aging list. For shared counter, only when it is
393 * released, the TAILQ entry memory will be used, at that
394 * time, shared memory is not used anymore.
396 * Similarly to none-batch counter dcs, since it doesn't
397 * support aging, while counter is allocated, the entry
398 * memory is not used anymore. In this case, as bytes
399 * memory is used only when counter is allocated, and
400 * entry memory is used only when counter is free. The
401 * dcs pointer can be saved to these two different place
402 * at different stage. It will eliminate the individual
403 * counter extend struct.
405 TAILQ_ENTRY(mlx5_flow_counter) next;
406 /**< Pointer to the next flow counter structure. */
408 struct mlx5_flow_counter_shared shared_info;
409 /**< Shared counter information. */
410 void *dcs_when_active;
412 * For non-batch mode, the dcs will be saved
413 * here when the counter is free.
418 uint64_t hits; /**< Reset value of hits packets. */
419 struct mlx5_flow_counter_pool *pool; /**< Counter pool. */
422 uint64_t bytes; /**< Reset value of bytes. */
425 * For non-batch mode, the dcs will be saved here
426 * when the counter is free.
429 void *action; /**< Pointer to the dv action. */
432 TAILQ_HEAD(mlx5_counters, mlx5_flow_counter);
434 /* Generic counter pool structure - query is in pool resolution. */
435 struct mlx5_flow_counter_pool {
436 TAILQ_ENTRY(mlx5_flow_counter_pool) next;
437 struct mlx5_counters counters[2]; /* Free counter list. */
438 struct mlx5_devx_obj *min_dcs;
439 /* The devx object of the minimum counter ID. */
440 uint64_t time_of_last_age_check;
441 /* System time (from rte_rdtsc()) read in the last aging check. */
442 uint32_t index:30; /* Pool index in container. */
443 uint32_t is_aged:1; /* Pool with aging counter. */
444 volatile uint32_t query_gen:1; /* Query round. */
445 rte_spinlock_t sl; /* The pool lock. */
446 rte_spinlock_t csl; /* The pool counter free list lock. */
447 struct mlx5_counter_stats_raw *raw;
448 struct mlx5_counter_stats_raw *raw_hw;
449 /* The raw on HW working. */
452 /* Memory management structure for group of counter statistics raws. */
453 struct mlx5_counter_stats_mem_mng {
454 LIST_ENTRY(mlx5_counter_stats_mem_mng) next;
455 struct mlx5_counter_stats_raw *raws;
456 struct mlx5_devx_obj *dm;
460 /* Raw memory structure for the counter statistics values of a pool. */
461 struct mlx5_counter_stats_raw {
462 LIST_ENTRY(mlx5_counter_stats_raw) next;
463 struct mlx5_counter_stats_mem_mng *mem_mng;
464 volatile struct flow_counter_stats *data;
467 TAILQ_HEAD(mlx5_counter_pools, mlx5_flow_counter_pool);
469 /* Counter global management structure. */
470 struct mlx5_flow_counter_mng {
471 volatile uint16_t n_valid; /* Number of valid pools. */
472 uint16_t n; /* Number of pools. */
473 uint16_t last_pool_idx; /* Last used pool index */
474 int min_id; /* The minimum counter ID in the pools. */
475 int max_id; /* The maximum counter ID in the pools. */
476 rte_spinlock_t pool_update_sl; /* The pool update lock. */
477 rte_spinlock_t csl[MLX5_COUNTER_TYPE_MAX];
478 /* The counter free list lock. */
479 struct mlx5_counters counters[MLX5_COUNTER_TYPE_MAX];
480 /* Free counter list. */
481 struct mlx5_flow_counter_pool **pools; /* Counter pool array. */
482 struct mlx5_counter_stats_mem_mng *mem_mng;
483 /* Hold the memory management for the next allocated pools raws. */
484 struct mlx5_counters flow_counters; /* Legacy flow counter list. */
485 uint8_t pending_queries;
487 uint8_t query_thread_on;
488 bool relaxed_ordering_read;
489 bool relaxed_ordering_write;
490 bool counter_fallback; /* Use counter fallback management. */
491 LIST_HEAD(mem_mngs, mlx5_counter_stats_mem_mng) mem_mngs;
492 LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws;
495 /* ASO structures. */
496 #define MLX5_ASO_QUEUE_LOG_DESC 10
501 struct mlx5_devx_cq cq_obj;
505 struct mlx5_aso_sq_elem {
508 struct mlx5_aso_age_pool *pool;
511 struct mlx5_aso_mtr *mtr;
513 struct mlx5_aso_ct_action *ct;
522 struct mlx5_aso_cq cq;
523 struct mlx5_devx_sq sq_obj;
524 volatile uint64_t *uar_addr;
525 struct mlx5_pmd_mr mr;
530 struct mlx5_aso_sq_elem elts[1 << MLX5_ASO_QUEUE_LOG_DESC];
531 uint16_t next; /* Pool index of the next pool to query. */
534 struct mlx5_aso_age_action {
535 LIST_ENTRY(mlx5_aso_age_action) next;
538 /* Following fields relevant only when action is active. */
539 uint16_t offset; /* Offset of ASO Flow Hit flag in DevX object. */
540 struct mlx5_age_param age_params;
543 #define MLX5_ASO_AGE_ACTIONS_PER_POOL 512
545 struct mlx5_aso_age_pool {
546 struct mlx5_devx_obj *flow_hit_aso_obj;
547 uint16_t index; /* Pool index in pools array. */
548 uint64_t time_of_last_age_check; /* In seconds. */
549 struct mlx5_aso_age_action actions[MLX5_ASO_AGE_ACTIONS_PER_POOL];
552 LIST_HEAD(aso_age_list, mlx5_aso_age_action);
554 struct mlx5_aso_age_mng {
555 struct mlx5_aso_age_pool **pools;
556 uint16_t n; /* Total number of pools. */
557 uint16_t next; /* Number of pools in use, index of next free pool. */
558 rte_rwlock_t resize_rwl; /* Lock for resize objects. */
559 rte_spinlock_t free_sl; /* Lock for free list access. */
560 struct aso_age_list free; /* Free age actions list - ready to use. */
561 struct mlx5_aso_sq aso_sq; /* ASO queue objects. */
564 /* Management structure for geneve tlv option */
565 struct mlx5_geneve_tlv_option_resource {
566 struct mlx5_devx_obj *obj; /* Pointer to the geneve tlv opt object. */
567 rte_be16_t option_class; /* geneve tlv opt class.*/
568 uint8_t option_type; /* geneve tlv opt type.*/
569 uint8_t length; /* geneve tlv opt length. */
570 uint32_t refcnt; /* geneve tlv object reference counter */
574 #define MLX5_AGE_EVENT_NEW 1
575 #define MLX5_AGE_TRIGGER 2
576 #define MLX5_AGE_SET(age_info, BIT) \
577 ((age_info)->flags |= (1 << (BIT)))
578 #define MLX5_AGE_UNSET(age_info, BIT) \
579 ((age_info)->flags &= ~(1 << (BIT)))
580 #define MLX5_AGE_GET(age_info, BIT) \
581 ((age_info)->flags & (1 << (BIT)))
582 #define GET_PORT_AGE_INFO(priv) \
583 (&((priv)->sh->port[(priv)->dev_port - 1].age_info))
584 /* Current time in seconds. */
585 #define MLX5_CURR_TIME_SEC (rte_rdtsc() / rte_get_tsc_hz())
587 /* Aging information for per port. */
588 struct mlx5_age_info {
589 uint8_t flags; /* Indicate if is new event or need to be triggered. */
590 struct mlx5_counters aged_counters; /* Aged counter list. */
591 struct aso_age_list aged_aso; /* Aged ASO actions list. */
592 rte_spinlock_t aged_sl; /* Aged flow list lock. */
595 /* Per port data of shared IB device. */
596 struct mlx5_dev_shared_port {
598 uint32_t devx_ih_port_id;
600 * Interrupt handler port_id. Used by shared interrupt
601 * handler to find the corresponding rte_eth device
602 * by IB port index. If value is equal or greater
603 * RTE_MAX_ETHPORTS it means there is no subhandler
604 * installed for specified IB port index.
606 struct mlx5_age_info age_info;
607 /* Aging information for per port. */
611 * Max number of actions per DV flow.
612 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED
613 * in rdma-core file providers/mlx5/verbs.c.
615 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8
617 /* ASO flow meter structures */
618 /* Modify this value if enum rte_mtr_color changes. */
619 #define RTE_MTR_DROPPED RTE_COLORS
620 /* Yellow is now supported. */
621 #define MLX5_MTR_RTE_COLORS (RTE_COLOR_YELLOW + 1)
622 /* table_id 22 bits in mlx5_flow_tbl_key so limit policy number. */
623 #define MLX5_MAX_SUB_POLICY_TBL_NUM 0x3FFFFF
624 #define MLX5_INVALID_POLICY_ID UINT32_MAX
625 /* Suffix table_id on MLX5_FLOW_TABLE_LEVEL_METER. */
626 #define MLX5_MTR_TABLE_ID_SUFFIX 1
627 /* Drop table_id on MLX5_FLOW_TABLE_LEVEL_METER. */
628 #define MLX5_MTR_TABLE_ID_DROP 2
629 /* Priority of the meter policy matcher. */
630 #define MLX5_MTR_POLICY_MATCHER_PRIO 0
631 /* Default policy. */
632 #define MLX5_MTR_POLICY_MODE_DEF 1
633 /* Only green color valid. */
634 #define MLX5_MTR_POLICY_MODE_OG 2
635 /* Only yellow color valid. */
636 #define MLX5_MTR_POLICY_MODE_OY 3
638 enum mlx5_meter_domain {
639 MLX5_MTR_DOMAIN_INGRESS,
640 MLX5_MTR_DOMAIN_EGRESS,
641 MLX5_MTR_DOMAIN_TRANSFER,
644 #define MLX5_MTR_DOMAIN_INGRESS_BIT (1 << MLX5_MTR_DOMAIN_INGRESS)
645 #define MLX5_MTR_DOMAIN_EGRESS_BIT (1 << MLX5_MTR_DOMAIN_EGRESS)
646 #define MLX5_MTR_DOMAIN_TRANSFER_BIT (1 << MLX5_MTR_DOMAIN_TRANSFER)
647 #define MLX5_MTR_ALL_DOMAIN_BIT (MLX5_MTR_DOMAIN_INGRESS_BIT | \
648 MLX5_MTR_DOMAIN_EGRESS_BIT | \
649 MLX5_MTR_DOMAIN_TRANSFER_BIT)
651 /* The color tag rule structure. */
652 struct mlx5_sub_policy_color_rule {
654 /* The color rule. */
655 struct mlx5_flow_dv_matcher *matcher;
656 /* The color matcher. */
657 TAILQ_ENTRY(mlx5_sub_policy_color_rule) next_port;
658 /**< Pointer to the next color rule structure. */
660 /* On which src port this rule applied. */
663 TAILQ_HEAD(mlx5_sub_policy_color_rules, mlx5_sub_policy_color_rule);
666 * Meter sub-policy structure.
667 * Each RSS TIR in meter policy need its own sub-policy resource.
669 struct mlx5_flow_meter_sub_policy {
670 uint32_t main_policy_id:1;
671 /* Main policy id is same as this sub_policy id. */
673 /* Index to sub_policy ipool entity. */
675 /* Point to struct mlx5_flow_meter_policy. */
676 struct mlx5_flow_tbl_resource *tbl_rsc;
677 /* The sub-policy table resource. */
678 uint32_t rix_hrxq[MLX5_MTR_RTE_COLORS];
679 /* Index to TIR resource. */
680 struct mlx5_flow_tbl_resource *jump_tbl[MLX5_MTR_RTE_COLORS];
681 /* Meter jump/drop table. */
682 struct mlx5_sub_policy_color_rules color_rules[RTE_COLORS];
683 /* List for the color rules. */
686 struct mlx5_meter_policy_acts {
688 /* Number of actions. */
689 void *dv_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS];
693 struct mlx5_meter_policy_action_container {
695 /* Index to the mark action. */
696 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
697 /* Pointer to modify header resource in cache. */
699 /* Fate action type. */
701 struct rte_flow_action *rss;
702 /* Rss action configuration. */
703 uint32_t rix_port_id_action;
704 /* Index to port ID action resource. */
705 void *dr_jump_action[MLX5_MTR_DOMAIN_MAX];
706 /* Jump/drop action per color. */
708 /* Queue action configuration. */
710 uint32_t next_mtr_id;
711 /* The next meter id. */
712 void *next_sub_policy;
713 /* Next meter's sub-policy. */
718 /* Flow meter policy parameter structure. */
719 struct mlx5_flow_meter_policy {
720 struct rte_eth_dev *dev;
721 /* The port dev on which policy is created. */
723 /* Is RSS policy table. */
725 /* Rule applies to ingress domain. */
727 /* Rule applies to egress domain. */
729 /* Rule applies to transfer domain. */
731 /* Is queue action in policy table. */
732 uint32_t is_hierarchy:1;
733 /* Is meter action in policy table. */
735 /* If yellow color policy is skipped. */
737 /* If green color policy is skipped. */
741 struct mlx5_meter_policy_action_container act_cnt[MLX5_MTR_RTE_COLORS];
742 /* Policy actions container. */
743 void *dr_drop_action[MLX5_MTR_DOMAIN_MAX];
744 /* drop action for red color. */
745 uint16_t sub_policy_num;
746 /* Count sub policy tables, 3 bits per domain. */
747 struct mlx5_flow_meter_sub_policy **sub_policys[MLX5_MTR_DOMAIN_MAX];
748 /* Sub policy table array must be the end of struct. */
751 /* The maximum sub policy is relate to struct mlx5_rss_hash_fields[]. */
752 #define MLX5_MTR_RSS_MAX_SUB_POLICY 7
753 #define MLX5_MTR_SUB_POLICY_NUM_SHIFT 3
754 #define MLX5_MTR_SUB_POLICY_NUM_MASK 0x7
755 #define MLX5_MTRS_DEFAULT_RULE_PRIORITY 0xFFFF
756 #define MLX5_MTR_CHAIN_MAX_NUM 8
758 /* Flow meter default policy parameter structure.
759 * Policy index 0 is reserved by default policy table.
760 * Action per color as below:
761 * green - do nothing, yellow - do nothing, red - drop
763 struct mlx5_flow_meter_def_policy {
764 struct mlx5_flow_meter_sub_policy sub_policy;
765 /* Policy rules jump to other tables. */
766 void *dr_jump_action[RTE_COLORS];
767 /* Jump action per color. */
770 /* Meter parameter structure. */
771 struct mlx5_flow_meter_info {
775 /* Policy id, the first sub_policy idx. */
776 struct mlx5_flow_meter_profile *profile;
777 /**< Meter profile parameters. */
778 rte_spinlock_t sl; /**< Meter action spinlock. */
779 /** Set of stats counters to be enabled.
780 * @see enum rte_mtr_stats_type
782 uint32_t bytes_dropped:1;
783 /** Set bytes dropped stats to be enabled. */
784 uint32_t pkts_dropped:1;
785 /** Set packets dropped stats to be enabled. */
786 uint32_t active_state:1;
787 /**< Meter hw active state. */
789 /**< Meter shared or not. */
790 uint32_t is_enable:1;
791 /**< Meter disable/enable state. */
793 /**< Rule applies to egress traffic. */
796 * Instead of simply matching the properties of traffic as it would
797 * appear on a given DPDK port ID, enabling this attribute transfers
798 * a flow rule to the lowest possible level of any device endpoints
799 * found in the pattern.
801 * When supported, this effectively enables an application to
802 * re-route traffic not necessarily intended for it (e.g. coming
803 * from or addressed to different physical ports, VFs or
804 * applications) at the device level.
806 * It complements the behavior of some pattern items such as
807 * RTE_FLOW_ITEM_TYPE_PHY_PORT and is meaningless without them.
809 * When transferring flow rules, ingress and egress attributes keep
810 * their original meaning, as if processing traffic emitted or
811 * received by the application.
814 uint32_t def_policy:1;
815 /* Meter points to default policy. */
816 void *drop_rule[MLX5_MTR_DOMAIN_MAX];
817 /* Meter drop rule in drop table. */
819 /**< Color counter for drop. */
822 struct mlx5_indexed_pool *flow_ipool;
823 /**< Index pool for flow id. */
825 /**< Flow meter action. */
828 /* PPS(packets per second) map to BPS(Bytes per second).
829 * HW treat packet as 128bytes in PPS mode
831 #define MLX5_MTRS_PPS_MAP_BPS_SHIFT 7
833 /* RFC2697 parameter structure. */
834 struct mlx5_flow_meter_srtcm_rfc2697_prm {
837 * bit 24-28: cbs_exponent, bit 16-23 cbs_mantissa,
838 * bit 8-12: cir_exponent, bit 0-7 cir_mantissa.
842 * bit 24-28: ebs_exponent, bit 16-23 ebs_mantissa,
843 * bit 8-12: eir_exponent, bit 0-7 eir_mantissa.
847 /* Flow meter profile structure. */
848 struct mlx5_flow_meter_profile {
849 TAILQ_ENTRY(mlx5_flow_meter_profile) next;
850 /**< Pointer to the next flow meter structure. */
851 uint32_t id; /**< Profile id. */
852 struct rte_mtr_meter_profile profile; /**< Profile detail. */
854 struct mlx5_flow_meter_srtcm_rfc2697_prm srtcm_prm;
855 /**< srtcm_rfc2697 struct. */
857 uint32_t ref_cnt; /**< Use count. */
858 uint32_t g_support:1; /**< If G color will be generated. */
859 uint32_t y_support:1; /**< If Y color will be generated. */
862 /* 2 meters in each ASO cache line */
863 #define MLX5_MTRS_CONTAINER_RESIZE 64
865 * The pool index and offset of meter in the pool array makes up the
866 * meter index. In case the meter is from pool 0 and offset 0, it
867 * should plus 1 to avoid index 0, since 0 means invalid meter index
870 #define MLX5_MAKE_MTR_IDX(pi, offset) \
871 ((pi) * MLX5_ASO_MTRS_PER_POOL + (offset) + 1)
873 /*aso flow meter state*/
874 enum mlx5_aso_mtr_state {
875 ASO_METER_FREE, /* In free list. */
876 ASO_METER_WAIT, /* ACCESS_ASO WQE in progress. */
877 ASO_METER_READY, /* CQE received. */
880 /* Generic aso_flow_meter information. */
881 struct mlx5_aso_mtr {
882 LIST_ENTRY(mlx5_aso_mtr) next;
883 struct mlx5_flow_meter_info fm;
884 /**< Pointer to the next aso flow meter structure. */
885 uint8_t state; /**< ASO flow meter state. */
889 /* Generic aso_flow_meter pool structure. */
890 struct mlx5_aso_mtr_pool {
891 struct mlx5_aso_mtr mtrs[MLX5_ASO_MTRS_PER_POOL];
892 /*Must be the first in pool*/
893 struct mlx5_devx_obj *devx_obj;
894 /* The devx object of the minimum aso flow meter ID. */
895 uint32_t index; /* Pool index in management structure. */
898 LIST_HEAD(aso_meter_list, mlx5_aso_mtr);
899 /* Pools management structure for ASO flow meter pools. */
900 struct mlx5_aso_mtr_pools_mng {
901 volatile uint16_t n_valid; /* Number of valid pools. */
902 uint16_t n; /* Number of pools. */
903 rte_spinlock_t mtrsl; /* The ASO flow meter free list lock. */
904 rte_rwlock_t resize_mtrwl; /* Lock for resize objects. */
905 struct aso_meter_list meters; /* Free ASO flow meter list. */
906 struct mlx5_aso_sq sq; /*SQ using by ASO flow meter. */
907 struct mlx5_aso_mtr_pool **pools; /* ASO flow meter pool array. */
910 /* Meter management structure for global flow meter resource. */
911 struct mlx5_flow_mtr_mng {
912 struct mlx5_aso_mtr_pools_mng pools_mng;
913 /* Pools management structure for ASO flow meter pools. */
914 struct mlx5_flow_meter_def_policy *def_policy[MLX5_MTR_DOMAIN_MAX];
915 /* Default policy table. */
916 uint32_t def_policy_id;
917 /* Default policy id. */
918 uint32_t def_policy_ref_cnt;
919 /** def_policy meter use count. */
920 struct mlx5_flow_tbl_resource *drop_tbl[MLX5_MTR_DOMAIN_MAX];
921 /* Meter drop table. */
922 struct mlx5_flow_dv_matcher *
923 drop_matcher[MLX5_MTR_DOMAIN_MAX][MLX5_REG_BITS];
924 /* Matcher meter in drop table. */
925 struct mlx5_flow_dv_matcher *def_matcher[MLX5_MTR_DOMAIN_MAX];
926 /* Default matcher in drop table. */
927 void *def_rule[MLX5_MTR_DOMAIN_MAX];
928 /* Default rule in drop table. */
929 uint8_t max_mtr_bits;
930 /* Indicate how many bits are used by meter id at the most. */
931 uint8_t max_mtr_flow_bits;
932 /* Indicate how many bits are used by meter flow id at the most. */
935 /* Table key of the hash organization. */
936 union mlx5_flow_tbl_key {
938 /* Table ID should be at the lowest address. */
939 uint32_t level; /**< Level of the table. */
940 uint32_t id:22; /**< ID of the table. */
941 uint32_t dummy:1; /**< Dummy table for DV API. */
942 uint32_t is_fdb:1; /**< 1 - FDB, 0 - NIC TX/RX. */
943 uint32_t is_egress:1; /**< 1 - egress, 0 - ingress. */
944 uint32_t reserved:7; /**< must be zero for comparison. */
946 uint64_t v64; /**< full 64bits value of key */
949 /* Table structure. */
950 struct mlx5_flow_tbl_resource {
951 void *obj; /**< Pointer to DR table object. */
952 uint32_t refcnt; /**< Reference counter. */
955 #define MLX5_MAX_TABLES UINT16_MAX
956 #define MLX5_HAIRPIN_TX_TABLE (UINT16_MAX - 1)
957 /* Reserve the last two tables for metadata register copy. */
958 #define MLX5_FLOW_MREG_ACT_TABLE_GROUP (MLX5_MAX_TABLES - 1)
959 #define MLX5_FLOW_MREG_CP_TABLE_GROUP (MLX5_MAX_TABLES - 2)
960 /* Tables for metering splits should be added here. */
961 #define MLX5_FLOW_TABLE_LEVEL_METER (MLX5_MAX_TABLES - 3)
962 #define MLX5_FLOW_TABLE_LEVEL_POLICY (MLX5_MAX_TABLES - 4)
963 #define MLX5_MAX_TABLES_EXTERNAL MLX5_FLOW_TABLE_LEVEL_POLICY
964 #define MLX5_MAX_TABLES_FDB UINT16_MAX
965 #define MLX5_FLOW_TABLE_FACTOR 10
967 /* ID generation structure. */
968 struct mlx5_flow_id_pool {
969 uint32_t *free_arr; /**< Pointer to the a array of free values. */
971 /**< The next index that can be used without any free elements. */
972 uint32_t *curr; /**< Pointer to the index to pop. */
973 uint32_t *last; /**< Pointer to the last element in the empty arrray. */
974 uint32_t max_id; /**< Maximum id can be allocated from the pool. */
977 /* Tx pacing queue structure - for Clock and Rearm queues. */
978 struct mlx5_txpp_wq {
979 /* Completion Queue related data.*/
980 struct mlx5_devx_cq cq_obj;
983 /* Send Queue related data.*/
984 struct mlx5_devx_sq sq_obj;
985 uint16_t sq_size; /* Number of WQEs in the queue. */
986 uint16_t sq_ci; /* Next WQE to execute. */
989 /* Tx packet pacing internal timestamp. */
990 struct mlx5_txpp_ts {
995 /* Tx packet pacing structure. */
996 struct mlx5_dev_txpp {
997 pthread_mutex_t mutex; /* Pacing create/destroy mutex. */
998 uint32_t refcnt; /* Pacing reference counter. */
999 uint32_t freq; /* Timestamp frequency, Hz. */
1000 uint32_t tick; /* Completion tick duration in nanoseconds. */
1001 uint32_t test; /* Packet pacing test mode. */
1002 int32_t skew; /* Scheduling skew. */
1003 struct rte_intr_handle *intr_handle; /* Periodic interrupt. */
1004 void *echan; /* Event Channel. */
1005 struct mlx5_txpp_wq clock_queue; /* Clock Queue. */
1006 struct mlx5_txpp_wq rearm_queue; /* Clock Queue. */
1007 void *pp; /* Packet pacing context. */
1008 uint16_t pp_id; /* Packet pacing context index. */
1009 uint16_t ts_n; /* Number of captured timestamps. */
1010 uint16_t ts_p; /* Pointer to statisticks timestamp. */
1011 struct mlx5_txpp_ts *tsa; /* Timestamps sliding window stats. */
1012 struct mlx5_txpp_ts ts; /* Cached completion id/timestamp. */
1013 uint32_t sync_lost:1; /* ci/timestamp synchronization lost. */
1014 /* Statistics counters. */
1015 uint64_t err_miss_int; /* Missed service interrupt. */
1016 uint64_t err_rearm_queue; /* Rearm Queue errors. */
1017 uint64_t err_clock_queue; /* Clock Queue errors. */
1018 uint64_t err_ts_past; /* Timestamp in the past. */
1019 uint64_t err_ts_future; /* Timestamp in the distant future. */
1022 /* Sample ID information of eCPRI flex parser structure. */
1023 struct mlx5_ecpri_parser_profile {
1024 uint32_t num; /* Actual number of samples. */
1025 uint32_t ids[8]; /* Sample IDs for this profile. */
1026 uint8_t offset[8]; /* Bytes offset of each parser. */
1027 void *obj; /* Flex parser node object. */
1030 /* Max member ports per bonding device. */
1031 #define MLX5_BOND_MAX_PORTS 2
1033 /* Bonding device information. */
1034 struct mlx5_bond_info {
1035 int n_port; /* Number of bond member ports. */
1037 char ifname[MLX5_NAMESIZE + 1];
1039 char ifname[MLX5_NAMESIZE + 1];
1041 struct rte_pci_addr pci_addr;
1042 } ports[MLX5_BOND_MAX_PORTS];
1045 /* Number of connection tracking objects per pool: must be a power of 2. */
1046 #define MLX5_ASO_CT_ACTIONS_PER_POOL 64
1048 /* Generate incremental and unique CT index from pool and offset. */
1049 #define MLX5_MAKE_CT_IDX(pool, offset) \
1050 ((pool) * MLX5_ASO_CT_ACTIONS_PER_POOL + (offset) + 1)
1052 /* ASO Conntrack state. */
1053 enum mlx5_aso_ct_state {
1054 ASO_CONNTRACK_FREE, /* Inactive, in the free list. */
1055 ASO_CONNTRACK_WAIT, /* WQE sent in the SQ. */
1056 ASO_CONNTRACK_READY, /* CQE received w/o error. */
1057 ASO_CONNTRACK_QUERY, /* WQE for query sent. */
1058 ASO_CONNTRACK_MAX, /* Guard. */
1061 /* Generic ASO connection tracking structure. */
1062 struct mlx5_aso_ct_action {
1063 LIST_ENTRY(mlx5_aso_ct_action) next; /* Pointer to the next ASO CT. */
1064 void *dr_action_orig; /* General action object for original dir. */
1065 void *dr_action_rply; /* General action object for reply dir. */
1066 uint32_t refcnt; /* Action used count in device flows. */
1067 uint16_t offset; /* Offset of ASO CT in DevX objects bulk. */
1068 uint16_t peer; /* The only peer port index could also use this CT. */
1069 enum mlx5_aso_ct_state state; /* ASO CT state. */
1070 bool is_original; /* The direction of the DR action to be used. */
1073 /* CT action object state update. */
1074 #define MLX5_ASO_CT_UPDATE_STATE(c, s) \
1075 __atomic_store_n(&((c)->state), (s), __ATOMIC_RELAXED)
1077 /* ASO connection tracking software pool definition. */
1078 struct mlx5_aso_ct_pool {
1079 uint16_t index; /* Pool index in pools array. */
1080 struct mlx5_devx_obj *devx_obj;
1081 /* The first devx object in the bulk, used for freeing (not yet). */
1082 struct mlx5_aso_ct_action actions[MLX5_ASO_CT_ACTIONS_PER_POOL];
1083 /* CT action structures bulk. */
1086 LIST_HEAD(aso_ct_list, mlx5_aso_ct_action);
1088 /* Pools management structure for ASO connection tracking pools. */
1089 struct mlx5_aso_ct_pools_mng {
1090 struct mlx5_aso_ct_pool **pools;
1091 uint16_t n; /* Total number of pools. */
1092 uint16_t next; /* Number of pools in use, index of next free pool. */
1093 rte_spinlock_t ct_sl; /* The ASO CT free list lock. */
1094 rte_rwlock_t resize_rwl; /* The ASO CT pool resize lock. */
1095 struct aso_ct_list free_cts; /* Free ASO CT objects list. */
1096 struct mlx5_aso_sq aso_sq; /* ASO queue objects. */
1101 uint8_t tx_remap_affinity[16]; /* The PF port number of affinity */
1102 uint8_t affinity_mode; /* TIS or hash based affinity */
1105 /* DevX flex parser context. */
1106 struct mlx5_flex_parser_devx {
1107 struct mlx5_list_entry entry; /* List element at the beginning. */
1108 uint32_t num_samples;
1110 struct mlx5_devx_graph_node_attr devx_conf;
1111 uint32_t sample_ids[MLX5_GRAPH_NODE_SAMPLE_NUM];
1114 /* Pattern field dscriptor - how to translate flex pattern into samples. */
1116 struct mlx5_flex_pattern_field {
1121 #define MLX5_INVALID_SAMPLE_REG_ID 0x1F
1123 /* Port flex item context. */
1124 struct mlx5_flex_item {
1125 struct mlx5_flex_parser_devx *devx_fp; /* DevX flex parser object. */
1126 uint32_t refcnt; /* Atomically accessed refcnt by flows. */
1127 enum rte_flow_item_flex_tunnel_mode tunnel_mode; /* Tunnel mode. */
1128 uint32_t mapnum; /* Number of pattern translation entries. */
1129 struct mlx5_flex_pattern_field map[MLX5_FLEX_ITEM_MAPPING_NUM];
1133 * Shared Infiniband device context for Master/Representors
1134 * which belong to same IB device with multiple IB ports.
1136 struct mlx5_dev_ctx_shared {
1137 LIST_ENTRY(mlx5_dev_ctx_shared) next;
1139 uint32_t devx:1; /* Opened with DV. */
1140 uint32_t flow_hit_aso_en:1; /* Flow Hit ASO is supported. */
1141 uint32_t steering_format_version:4;
1142 /* Indicates the device steering logic format. */
1143 uint32_t meter_aso_en:1; /* Flow Meter ASO is supported. */
1144 uint32_t ct_aso_en:1; /* Connection Tracking ASO is supported. */
1145 uint32_t tunnel_header_0_1:1; /* tunnel_header_0_1 is supported. */
1146 uint32_t misc5_cap:1; /* misc5 matcher parameter is supported. */
1147 uint32_t reclaim_mode:1; /* Reclaim memory. */
1148 uint32_t dr_drop_action_en:1; /* Use DR drop action. */
1149 uint32_t drop_action_check_flag:1; /* Check Flag for drop action. */
1150 uint32_t flow_priority_check_flag:1; /* Check Flag for flow priority. */
1151 uint32_t metadata_regc_check_flag:1; /* Check Flag for metadata REGC. */
1152 uint32_t max_port; /* Maximal IB device port index. */
1153 struct mlx5_bond_info bond; /* Bonding information. */
1154 struct mlx5_common_device *cdev; /* Backend mlx5 device. */
1155 uint32_t tdn; /* Transport Domain number. */
1156 char ibdev_name[MLX5_FS_NAME_MAX]; /* SYSFS dev name. */
1157 char ibdev_path[MLX5_FS_PATH_MAX]; /* SYSFS dev path for secondary */
1158 struct mlx5_dev_attr device_attr; /* Device properties. */
1159 int numa_node; /* Numa node of backing physical device. */
1160 /* Packet pacing related structure. */
1161 struct mlx5_dev_txpp txpp;
1162 /* Shared DV/DR flow data section. */
1163 uint32_t dv_meta_mask; /* flow META metadata supported mask. */
1164 uint32_t dv_mark_mask; /* flow MARK metadata supported mask. */
1165 uint32_t dv_regc0_mask; /* available bits of metatada reg_c[0]. */
1166 void *fdb_domain; /* FDB Direct Rules name space handle. */
1167 void *rx_domain; /* RX Direct Rules name space handle. */
1168 void *tx_domain; /* TX Direct Rules name space handle. */
1170 rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */
1171 rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX];
1172 /* UAR same-page access control required in 32bit implementations. */
1174 struct mlx5_hlist *flow_tbls;
1175 struct mlx5_flow_tunnel_hub *tunnel_hub;
1176 /* Direct Rules tables for FDB, NIC TX+RX */
1177 void *dr_drop_action; /* Pointer to DR drop action, any domain. */
1178 void *pop_vlan_action; /* Pointer to DR pop VLAN action. */
1179 struct mlx5_hlist *encaps_decaps; /* Encap/decap action hash list. */
1180 struct mlx5_hlist *modify_cmds;
1181 struct mlx5_hlist *tag_table;
1182 struct mlx5_list *port_id_action_list; /* Port ID action list. */
1183 struct mlx5_list *push_vlan_action_list; /* Push VLAN actions. */
1184 struct mlx5_list *sample_action_list; /* List of sample actions. */
1185 struct mlx5_list *dest_array_list;
1186 struct mlx5_list *flex_parsers_dv; /* Flex Item parsers. */
1187 /* List of destination array actions. */
1188 struct mlx5_flow_counter_mng cmng; /* Counters management structure. */
1189 void *default_miss_action; /* Default miss action. */
1190 struct mlx5_indexed_pool *ipool[MLX5_IPOOL_MAX];
1191 struct mlx5_indexed_pool *mdh_ipools[MLX5_MAX_MODIFY_NUM];
1192 /* Shared interrupt handler section. */
1193 struct rte_intr_handle *intr_handle; /* Interrupt handler for device. */
1194 struct rte_intr_handle *intr_handle_devx; /* DEVX interrupt handler. */
1195 void *devx_comp; /* DEVX async comp obj. */
1196 struct mlx5_devx_obj *tis[16]; /* TIS object. */
1197 struct mlx5_devx_obj *td; /* Transport domain. */
1198 struct mlx5_lag lag; /* LAG attributes */
1199 void *tx_uar; /* Tx/packet pacing shared UAR. */
1200 struct mlx5_ecpri_parser_profile ecpri_parser;
1201 /* Flex parser profiles information. */
1202 void *devx_rx_uar; /* DevX UAR for Rx. */
1203 struct mlx5_aso_age_mng *aso_age_mng;
1204 /* Management data for aging mechanism using ASO Flow Hit. */
1205 struct mlx5_geneve_tlv_option_resource *geneve_tlv_option_resource;
1206 /* Management structure for geneve tlv option */
1207 rte_spinlock_t geneve_tlv_opt_sl; /* Lock for geneve tlv resource */
1208 struct mlx5_flow_mtr_mng *mtrmng;
1209 /* Meter management structure. */
1210 struct mlx5_aso_ct_pools_mng *ct_mng;
1211 /* Management data for ASO connection tracking. */
1212 struct mlx5_lb_ctx self_lb; /* QP to enable self loopback for Devx. */
1213 unsigned int flow_max_priority;
1214 enum modify_reg flow_mreg_c[MLX5_MREG_C_NUM];
1215 /* Availability of mreg_c's. */
1216 struct mlx5_dev_shared_port port[]; /* per device port data array. */
1220 * Per-process private structure.
1221 * Caution, secondary process may rebuild the struct during port start.
1223 struct mlx5_proc_priv {
1224 size_t uar_table_sz;
1225 /* Size of UAR register table. */
1227 /* Table of UAR registers for each process. */
1230 /* MTR profile list. */
1231 TAILQ_HEAD(mlx5_mtr_profiles, mlx5_flow_meter_profile);
1233 TAILQ_HEAD(mlx5_legacy_flow_meters, mlx5_legacy_flow_meter);
1235 /* RSS description. */
1236 struct mlx5_flow_rss_desc {
1238 uint32_t queue_num; /**< Number of entries in @p queue. */
1239 uint64_t types; /**< Specific RSS hash types (see RTE_ETH_RSS_*). */
1240 uint64_t hash_fields; /* Verbs Hash fields. */
1241 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
1242 uint32_t key_len; /**< RSS hash key len. */
1243 uint32_t tunnel; /**< Queue in tunnel. */
1244 uint32_t shared_rss; /**< Shared RSS index. */
1245 struct mlx5_ind_table_obj *ind_tbl;
1246 /**< Indirection table for shared RSS hash RX queues. */
1248 uint16_t *queue; /**< Destination queues. */
1249 const uint16_t *const_q; /**< Const pointer convert. */
1253 #define MLX5_PROC_PRIV(port_id) \
1254 ((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private)
1256 /* Verbs/DevX Rx queue elements. */
1257 struct mlx5_rxq_obj {
1258 LIST_ENTRY(mlx5_rxq_obj) next; /* Pointer to the next element. */
1259 struct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */
1260 int fd; /* File descriptor for event channel */
1264 void *wq; /* Work Queue. */
1265 void *ibv_cq; /* Completion Queue. */
1268 struct mlx5_devx_obj *rq; /* DevX RQ object for hairpin. */
1270 struct mlx5_devx_cq cq_obj; /* DevX CQ object. */
1276 /* Indirection table. */
1277 struct mlx5_ind_table_obj {
1278 LIST_ENTRY(mlx5_ind_table_obj) next; /* Pointer to the next element. */
1279 uint32_t refcnt; /* Reference counter. */
1282 void *ind_table; /**< Indirection table. */
1283 struct mlx5_devx_obj *rqt; /* DevX RQT object. */
1285 uint32_t queues_n; /**< Number of queues in the list. */
1286 uint16_t *queues; /**< Queue list. */
1289 /* Hash Rx queue. */
1292 struct mlx5_list_entry entry; /* List entry. */
1293 uint32_t standalone:1; /* This object used in shared action. */
1294 struct mlx5_ind_table_obj *ind_table; /* Indirection table. */
1297 void *qp; /* Verbs queue pair. */
1298 struct mlx5_devx_obj *tir; /* DevX TIR object. */
1300 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
1301 void *action; /* DV QP action pointer. */
1303 uint64_t hash_fields; /* Verbs Hash fields. */
1304 uint32_t rss_key_len; /* Hash key length in bytes. */
1305 uint32_t idx; /* Hash Rx queue index. */
1306 uint8_t rss_key[]; /* Hash key. */
1309 /* Verbs/DevX Tx queue elements. */
1310 struct mlx5_txq_obj {
1311 LIST_ENTRY(mlx5_txq_obj) next; /* Pointer to the next element. */
1312 struct mlx5_txq_ctrl *txq_ctrl; /* Pointer to the control queue. */
1316 void *cq; /* Completion Queue. */
1317 void *qp; /* Queue Pair. */
1320 struct mlx5_devx_obj *sq;
1321 /* DevX object for Sx queue. */
1322 struct mlx5_devx_obj *tis; /* The TIS object. */
1325 struct rte_eth_dev *dev;
1326 struct mlx5_devx_cq cq_obj;
1327 /* DevX CQ object and its resources. */
1328 struct mlx5_devx_sq sq_obj;
1329 /* DevX SQ object and its resources. */
1334 enum mlx5_rxq_modify_type {
1335 MLX5_RXQ_MOD_ERR2RST, /* modify state from error to reset. */
1336 MLX5_RXQ_MOD_RST2RDY, /* modify state from reset to ready. */
1337 MLX5_RXQ_MOD_RDY2ERR, /* modify state from ready to error. */
1338 MLX5_RXQ_MOD_RDY2RST, /* modify state from ready to reset. */
1341 enum mlx5_txq_modify_type {
1342 MLX5_TXQ_MOD_RST2RDY, /* modify state from reset to ready. */
1343 MLX5_TXQ_MOD_RDY2RST, /* modify state from ready to reset. */
1344 MLX5_TXQ_MOD_ERR2RDY, /* modify state from error to ready. */
1347 struct mlx5_rxq_priv;
1349 /* HW objects operations structure. */
1350 struct mlx5_obj_ops {
1351 int (*rxq_obj_modify_vlan_strip)(struct mlx5_rxq_priv *rxq, int on);
1352 int (*rxq_obj_new)(struct mlx5_rxq_priv *rxq);
1353 int (*rxq_event_get)(struct mlx5_rxq_obj *rxq_obj);
1354 int (*rxq_obj_modify)(struct mlx5_rxq_priv *rxq, uint8_t type);
1355 void (*rxq_obj_release)(struct mlx5_rxq_priv *rxq);
1356 int (*ind_table_new)(struct rte_eth_dev *dev, const unsigned int log_n,
1357 struct mlx5_ind_table_obj *ind_tbl);
1358 int (*ind_table_modify)(struct rte_eth_dev *dev,
1359 const unsigned int log_n,
1360 const uint16_t *queues, const uint32_t queues_n,
1361 struct mlx5_ind_table_obj *ind_tbl);
1362 void (*ind_table_destroy)(struct mlx5_ind_table_obj *ind_tbl);
1363 int (*hrxq_new)(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq,
1364 int tunnel __rte_unused);
1365 int (*hrxq_modify)(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq,
1366 const uint8_t *rss_key,
1367 uint64_t hash_fields,
1368 const struct mlx5_ind_table_obj *ind_tbl);
1369 void (*hrxq_destroy)(struct mlx5_hrxq *hrxq);
1370 int (*drop_action_create)(struct rte_eth_dev *dev);
1371 void (*drop_action_destroy)(struct rte_eth_dev *dev);
1372 int (*txq_obj_new)(struct rte_eth_dev *dev, uint16_t idx);
1373 int (*txq_obj_modify)(struct mlx5_txq_obj *obj,
1374 enum mlx5_txq_modify_type type, uint8_t dev_port);
1375 void (*txq_obj_release)(struct mlx5_txq_obj *txq_obj);
1376 int (*lb_dummy_queue_create)(struct rte_eth_dev *dev);
1377 void (*lb_dummy_queue_release)(struct rte_eth_dev *dev);
1380 #define MLX5_RSS_HASH_FIELDS_LEN RTE_DIM(mlx5_rss_hash_fields)
1383 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */
1384 struct mlx5_dev_ctx_shared *sh; /* Shared device context. */
1385 uint32_t dev_port; /* Device port number. */
1386 struct rte_pci_device *pci_dev; /* Backend PCI device. */
1387 struct rte_ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */
1388 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES);
1389 /* Bit-field of MAC addresses owned by the PMD. */
1390 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */
1391 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */
1392 /* Device properties. */
1393 uint16_t mtu; /* Configured MTU. */
1394 unsigned int isolated:1; /* Whether isolated mode is enabled. */
1395 unsigned int representor:1; /* Device is a port representor. */
1396 unsigned int master:1; /* Device is a E-Switch master. */
1397 unsigned int txpp_en:1; /* Tx packet pacing enabled. */
1398 unsigned int sampler_en:1; /* Whether support sampler. */
1399 unsigned int mtr_en:1; /* Whether support meter. */
1400 unsigned int mtr_reg_share:1; /* Whether support meter REG_C share. */
1401 unsigned int lb_used:1; /* Loopback queue is referred to. */
1402 uint16_t domain_id; /* Switch domain identifier. */
1403 uint16_t vport_id; /* Associated VF vport index (if any). */
1404 uint32_t vport_meta_tag; /* Used for vport index match ove VF LAG. */
1405 uint32_t vport_meta_mask; /* Used for vport index field match mask. */
1406 uint16_t representor_id; /* UINT16_MAX if not a representor. */
1407 int32_t pf_bond; /* >=0, representor owner PF index in bonding. */
1408 unsigned int if_index; /* Associated kernel network device index. */
1410 unsigned int rxqs_n; /* RX queues array size. */
1411 unsigned int txqs_n; /* TX queues array size. */
1412 struct mlx5_rxq_priv *(*rxq_privs)[]; /* RX queue non-shared data. */
1413 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */
1414 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
1415 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */
1416 unsigned int (*reta_idx)[]; /* RETA index table. */
1417 unsigned int reta_idx_n; /* RETA index size. */
1418 struct mlx5_drop drop_queue; /* Flow drop queues. */
1419 void *root_drop_action; /* Pointer to root drop action. */
1420 struct mlx5_indexed_pool *flows[MLX5_FLOW_TYPE_MAXI];
1421 /* RTE Flow rules. */
1422 uint32_t ctrl_flows; /* Control flow rules. */
1423 rte_spinlock_t flow_list_lock;
1424 struct mlx5_obj_ops obj_ops; /* HW objects operations. */
1425 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */
1426 LIST_HEAD(rxqobj, mlx5_rxq_obj) rxqsobj; /* Verbs/DevX Rx queues. */
1427 struct mlx5_list *hrxqs; /* Hash Rx queues. */
1428 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */
1429 LIST_HEAD(txqobj, mlx5_txq_obj) txqsobj; /* Verbs/DevX Tx queues. */
1430 /* Indirection tables. */
1431 LIST_HEAD(ind_tables, mlx5_ind_table_obj) ind_tbls;
1432 /* Pointer to next element. */
1433 rte_rwlock_t ind_tbls_lock;
1434 uint32_t refcnt; /**< Reference counter. */
1435 /**< Verbs modify header action object. */
1436 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
1437 uint8_t max_lro_msg_size;
1438 uint32_t link_speed_capa; /* Link speed capabilities. */
1439 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */
1440 struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */
1441 struct mlx5_dev_config config; /* Device configuration. */
1442 /* Context for Verbs allocator. */
1443 int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */
1444 int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */
1445 struct mlx5_nl_vlan_vmwa_context *vmwa_context; /* VLAN WA context. */
1446 struct mlx5_hlist *mreg_cp_tbl;
1447 /* Hash table of Rx metadata register copy table. */
1448 uint8_t mtr_sfx_reg; /* Meter prefix-suffix flow match REG_C. */
1449 uint8_t mtr_color_reg; /* Meter color match REG_C. */
1450 struct mlx5_legacy_flow_meters flow_meters; /* MTR list. */
1451 struct mlx5_l3t_tbl *mtr_profile_tbl; /* Meter index lookup table. */
1452 struct mlx5_l3t_tbl *policy_idx_tbl; /* Policy index lookup table. */
1453 struct mlx5_l3t_tbl *mtr_idx_tbl; /* Meter index lookup table. */
1454 uint8_t skip_default_rss_reta; /* Skip configuration of default reta. */
1455 uint8_t fdb_def_rule; /* Whether fdb jump to table 1 is configured. */
1456 struct mlx5_mp_id mp_id; /* ID of a multi-process process */
1457 LIST_HEAD(fdir, mlx5_fdir_flow) fdir_flows; /* fdir flows. */
1458 rte_spinlock_t shared_act_sl; /* Shared actions spinlock. */
1459 uint32_t rss_shared_actions; /* RSS shared actions. */
1460 struct mlx5_devx_obj *q_counters; /* DevX queue counter object. */
1461 uint32_t counter_set_id; /* Queue counter ID to set in DevX objects. */
1462 uint32_t lag_affinity_idx; /* LAG mode queue 0 affinity starting. */
1463 rte_spinlock_t flex_item_sl; /* Flex item list spinlock. */
1464 struct mlx5_flex_item flex_item[MLX5_PORT_FLEX_ITEM_NUM];
1465 /* Flex items have been created on the port. */
1466 uint32_t flex_item_map; /* Map of allocated flex item elements. */
1469 #define PORT_ID(priv) ((priv)->dev_data->port_id)
1470 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)])
1472 struct rte_hairpin_peer_info {
1476 uint16_t tx_explicit;
1477 uint16_t manual_bind;
1480 #define BUF_SIZE 1024
1481 enum dr_dump_rec_type {
1482 DR_DUMP_REC_TYPE_PMD_PKT_REFORMAT = 4410,
1483 DR_DUMP_REC_TYPE_PMD_MODIFY_HDR = 4420,
1484 DR_DUMP_REC_TYPE_PMD_COUNTER = 4430,
1489 int mlx5_getenv_int(const char *);
1490 int mlx5_proc_priv_init(struct rte_eth_dev *dev);
1491 void mlx5_proc_priv_uninit(struct rte_eth_dev *dev);
1492 int mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev,
1493 struct rte_eth_udp_tunnel *udp_tunnel);
1494 uint16_t mlx5_eth_find_next(uint16_t port_id, struct rte_device *odev);
1495 int mlx5_dev_close(struct rte_eth_dev *dev);
1496 int mlx5_net_remove(struct mlx5_common_device *cdev);
1497 bool mlx5_is_hpf(struct rte_eth_dev *dev);
1498 bool mlx5_is_sf_repr(struct rte_eth_dev *dev);
1499 void mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh);
1501 /* Macro to iterate over all valid ports for mlx5 driver. */
1502 #define MLX5_ETH_FOREACH_DEV(port_id, dev) \
1503 for (port_id = mlx5_eth_find_next(0, dev); \
1504 port_id < RTE_MAX_ETHPORTS; \
1505 port_id = mlx5_eth_find_next(port_id + 1, dev))
1506 int mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs);
1507 struct mlx5_dev_ctx_shared *
1508 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
1509 const struct mlx5_dev_config *config);
1510 void mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh);
1511 int mlx5_dev_ctx_shared_mempool_subscribe(struct rte_eth_dev *dev);
1512 void mlx5_free_table_hash_list(struct mlx5_priv *priv);
1513 int mlx5_alloc_table_hash_list(struct mlx5_priv *priv);
1514 void mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1515 struct mlx5_dev_config *config);
1516 void mlx5_set_metadata_mask(struct rte_eth_dev *dev);
1517 int mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
1518 struct mlx5_dev_config *config,
1519 struct rte_device *dpdk_dev);
1520 int mlx5_dev_configure(struct rte_eth_dev *dev);
1521 int mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info);
1522 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size);
1523 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
1524 int mlx5_hairpin_cap_get(struct rte_eth_dev *dev,
1525 struct rte_eth_hairpin_cap *cap);
1526 bool mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev);
1527 int mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev);
1528 int mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh);
1529 int mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh);
1530 int mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh);
1534 int mlx5_dev_configure(struct rte_eth_dev *dev);
1535 int mlx5_representor_info_get(struct rte_eth_dev *dev,
1536 struct rte_eth_representor_info *info);
1537 #define MLX5_REPRESENTOR_ID(pf, type, repr) \
1538 (((pf) << 14) + ((type) << 12) + ((repr) & 0xfff))
1539 #define MLX5_REPRESENTOR_REPR(repr_id) \
1541 #define MLX5_REPRESENTOR_TYPE(repr_id) \
1542 (((repr_id) >> 12) & 3)
1543 uint16_t mlx5_representor_id_encode(const struct mlx5_switch_info *info,
1544 enum rte_eth_representor_type hpf_type);
1545 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver,
1547 int mlx5_dev_infos_get(struct rte_eth_dev *dev,
1548 struct rte_eth_dev_info *info);
1549 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev);
1550 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
1551 int mlx5_hairpin_cap_get(struct rte_eth_dev *dev,
1552 struct rte_eth_hairpin_cap *cap);
1553 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev);
1554 struct mlx5_priv *mlx5_port_to_eswitch_info(uint16_t port, bool valid);
1555 struct mlx5_priv *mlx5_dev_to_eswitch_info(struct rte_eth_dev *dev);
1556 int mlx5_dev_configure_rss_reta(struct rte_eth_dev *dev);
1558 /* mlx5_ethdev_os.c */
1560 int mlx5_get_ifname(const struct rte_eth_dev *dev,
1561 char (*ifname)[MLX5_NAMESIZE]);
1562 unsigned int mlx5_ifindex(const struct rte_eth_dev *dev);
1563 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]);
1564 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu);
1565 int mlx5_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
1566 int mlx5_read_clock(struct rte_eth_dev *dev, uint64_t *clock);
1567 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete);
1568 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev,
1569 struct rte_eth_fc_conf *fc_conf);
1570 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev,
1571 struct rte_eth_fc_conf *fc_conf);
1572 void mlx5_dev_interrupt_handler(void *arg);
1573 void mlx5_dev_interrupt_handler_devx(void *arg);
1574 int mlx5_set_link_down(struct rte_eth_dev *dev);
1575 int mlx5_set_link_up(struct rte_eth_dev *dev);
1576 int mlx5_is_removed(struct rte_eth_dev *dev);
1577 int mlx5_sysfs_switch_info(unsigned int ifindex,
1578 struct mlx5_switch_info *info);
1579 void mlx5_translate_port_name(const char *port_name_in,
1580 struct mlx5_switch_info *port_info_out);
1581 void mlx5_intr_callback_unregister(const struct rte_intr_handle *handle,
1582 rte_intr_callback_fn cb_fn, void *cb_arg);
1583 int mlx5_sysfs_bond_info(unsigned int pf_ifindex, unsigned int *ifindex,
1585 int mlx5_get_module_info(struct rte_eth_dev *dev,
1586 struct rte_eth_dev_module_info *modinfo);
1587 int mlx5_get_module_eeprom(struct rte_eth_dev *dev,
1588 struct rte_dev_eeprom_info *info);
1589 int mlx5_os_read_dev_stat(struct mlx5_priv *priv,
1590 const char *ctr_name, uint64_t *stat);
1591 int mlx5_os_read_dev_counters(struct rte_eth_dev *dev, uint64_t *stats);
1592 int mlx5_os_get_stats_n(struct rte_eth_dev *dev);
1593 void mlx5_os_stats_init(struct rte_eth_dev *dev);
1597 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
1598 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
1599 uint32_t index, uint32_t vmdq);
1600 int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr);
1601 int mlx5_set_mc_addr_list(struct rte_eth_dev *dev,
1602 struct rte_ether_addr *mc_addr_set,
1603 uint32_t nb_mc_addr);
1607 int mlx5_rss_hash_update(struct rte_eth_dev *dev,
1608 struct rte_eth_rss_conf *rss_conf);
1609 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev,
1610 struct rte_eth_rss_conf *rss_conf);
1611 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size);
1612 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev,
1613 struct rte_eth_rss_reta_entry64 *reta_conf,
1614 uint16_t reta_size);
1615 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev,
1616 struct rte_eth_rss_reta_entry64 *reta_conf,
1617 uint16_t reta_size);
1621 int mlx5_promiscuous_enable(struct rte_eth_dev *dev);
1622 int mlx5_promiscuous_disable(struct rte_eth_dev *dev);
1623 int mlx5_allmulticast_enable(struct rte_eth_dev *dev);
1624 int mlx5_allmulticast_disable(struct rte_eth_dev *dev);
1628 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
1629 int mlx5_stats_reset(struct rte_eth_dev *dev);
1630 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats,
1632 int mlx5_xstats_reset(struct rte_eth_dev *dev);
1633 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
1634 struct rte_eth_xstat_name *xstats_names,
1639 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
1640 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on);
1641 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask);
1643 /* mlx5_vlan_os.c */
1645 void mlx5_vlan_vmwa_exit(void *ctx);
1646 void mlx5_vlan_vmwa_release(struct rte_eth_dev *dev,
1647 struct mlx5_vf_vlan *vf_vlan);
1648 void mlx5_vlan_vmwa_acquire(struct rte_eth_dev *dev,
1649 struct mlx5_vf_vlan *vf_vlan);
1650 void *mlx5_vlan_vmwa_init(struct rte_eth_dev *dev, uint32_t ifindex);
1652 /* mlx5_trigger.c */
1654 int mlx5_dev_start(struct rte_eth_dev *dev);
1655 int mlx5_dev_stop(struct rte_eth_dev *dev);
1656 int mlx5_traffic_enable(struct rte_eth_dev *dev);
1657 void mlx5_traffic_disable(struct rte_eth_dev *dev);
1658 int mlx5_traffic_restart(struct rte_eth_dev *dev);
1659 int mlx5_hairpin_queue_peer_update(struct rte_eth_dev *dev, uint16_t peer_queue,
1660 struct rte_hairpin_peer_info *current_info,
1661 struct rte_hairpin_peer_info *peer_info,
1662 uint32_t direction);
1663 int mlx5_hairpin_queue_peer_bind(struct rte_eth_dev *dev, uint16_t cur_queue,
1664 struct rte_hairpin_peer_info *peer_info,
1665 uint32_t direction);
1666 int mlx5_hairpin_queue_peer_unbind(struct rte_eth_dev *dev, uint16_t cur_queue,
1667 uint32_t direction);
1668 int mlx5_hairpin_bind(struct rte_eth_dev *dev, uint16_t rx_port);
1669 int mlx5_hairpin_unbind(struct rte_eth_dev *dev, uint16_t rx_port);
1670 int mlx5_hairpin_get_peer_ports(struct rte_eth_dev *dev, uint16_t *peer_ports,
1671 size_t len, uint32_t direction);
1675 int mlx5_flow_discover_mreg_c(struct rte_eth_dev *eth_dev);
1676 bool mlx5_flow_ext_mreg_supported(struct rte_eth_dev *dev);
1677 void mlx5_flow_print(struct rte_flow *flow);
1678 int mlx5_flow_validate(struct rte_eth_dev *dev,
1679 const struct rte_flow_attr *attr,
1680 const struct rte_flow_item items[],
1681 const struct rte_flow_action actions[],
1682 struct rte_flow_error *error);
1683 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev,
1684 const struct rte_flow_attr *attr,
1685 const struct rte_flow_item items[],
1686 const struct rte_flow_action actions[],
1687 struct rte_flow_error *error);
1688 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow,
1689 struct rte_flow_error *error);
1690 void mlx5_flow_list_flush(struct rte_eth_dev *dev, enum mlx5_flow_type type,
1692 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error);
1693 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow,
1694 const struct rte_flow_action *action, void *data,
1695 struct rte_flow_error *error);
1696 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable,
1697 struct rte_flow_error *error);
1698 int mlx5_flow_ops_get(struct rte_eth_dev *dev, const struct rte_flow_ops **ops);
1699 int mlx5_flow_start_default(struct rte_eth_dev *dev);
1700 void mlx5_flow_stop_default(struct rte_eth_dev *dev);
1701 int mlx5_flow_verify(struct rte_eth_dev *dev);
1702 int mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, uint32_t queue);
1703 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev,
1704 struct rte_flow_item_eth *eth_spec,
1705 struct rte_flow_item_eth *eth_mask,
1706 struct rte_flow_item_vlan *vlan_spec,
1707 struct rte_flow_item_vlan *vlan_mask);
1708 int mlx5_ctrl_flow(struct rte_eth_dev *dev,
1709 struct rte_flow_item_eth *eth_spec,
1710 struct rte_flow_item_eth *eth_mask);
1711 int mlx5_flow_lacp_miss(struct rte_eth_dev *dev);
1712 struct rte_flow *mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev);
1713 uint32_t mlx5_flow_create_devx_sq_miss_flow(struct rte_eth_dev *dev,
1715 void mlx5_flow_async_pool_query_handle(struct mlx5_dev_ctx_shared *sh,
1716 uint64_t async_id, int status);
1717 void mlx5_set_query_alarm(struct mlx5_dev_ctx_shared *sh);
1718 void mlx5_flow_query_alarm(void *arg);
1719 uint32_t mlx5_counter_alloc(struct rte_eth_dev *dev);
1720 void mlx5_counter_free(struct rte_eth_dev *dev, uint32_t cnt);
1721 int mlx5_counter_query(struct rte_eth_dev *dev, uint32_t cnt,
1722 bool clear, uint64_t *pkts, uint64_t *bytes);
1723 int mlx5_flow_dev_dump(struct rte_eth_dev *dev, struct rte_flow *flow,
1724 FILE *file, struct rte_flow_error *error);
1725 int save_dump_file(const unsigned char *data, uint32_t size,
1726 uint32_t type, uint64_t id, void *arg, FILE *file);
1727 int mlx5_flow_query_counter(struct rte_eth_dev *dev, struct rte_flow *flow,
1728 struct rte_flow_query_count *count, struct rte_flow_error *error);
1729 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1730 int mlx5_flow_dev_dump_ipool(struct rte_eth_dev *dev, struct rte_flow *flow,
1731 FILE *file, struct rte_flow_error *error);
1733 void mlx5_flow_rxq_dynf_metadata_set(struct rte_eth_dev *dev);
1734 int mlx5_flow_get_aged_flows(struct rte_eth_dev *dev, void **contexts,
1735 uint32_t nb_contexts, struct rte_flow_error *error);
1736 int mlx5_validate_action_ct(struct rte_eth_dev *dev,
1737 const struct rte_flow_action_conntrack *conntrack,
1738 struct rte_flow_error *error);
1743 int mlx5_mp_os_primary_handle(const struct rte_mp_msg *mp_msg,
1745 int mlx5_mp_os_secondary_handle(const struct rte_mp_msg *mp_msg,
1747 void mlx5_mp_os_req_start_rxtx(struct rte_eth_dev *dev);
1748 void mlx5_mp_os_req_stop_rxtx(struct rte_eth_dev *dev);
1749 int mlx5_mp_os_req_queue_control(struct rte_eth_dev *dev, uint16_t queue_id,
1750 enum mlx5_mp_req_type req_type);
1754 int mlx5_pmd_socket_init(void);
1755 void mlx5_pmd_socket_uninit(void);
1757 /* mlx5_flow_meter.c */
1759 int mlx5_flow_meter_ops_get(struct rte_eth_dev *dev, void *arg);
1760 struct mlx5_flow_meter_info *mlx5_flow_meter_find(struct mlx5_priv *priv,
1761 uint32_t meter_id, uint32_t *mtr_idx);
1762 struct mlx5_flow_meter_info *
1763 flow_dv_meter_find_by_idx(struct mlx5_priv *priv, uint32_t idx);
1764 int mlx5_flow_meter_attach(struct mlx5_priv *priv,
1765 struct mlx5_flow_meter_info *fm,
1766 const struct rte_flow_attr *attr,
1767 struct rte_flow_error *error);
1768 void mlx5_flow_meter_detach(struct mlx5_priv *priv,
1769 struct mlx5_flow_meter_info *fm);
1770 struct mlx5_flow_meter_policy *mlx5_flow_meter_policy_find
1771 (struct rte_eth_dev *dev,
1773 uint32_t *policy_idx);
1774 struct mlx5_flow_meter_policy *
1775 mlx5_flow_meter_hierarchy_get_final_policy(struct rte_eth_dev *dev,
1776 struct mlx5_flow_meter_policy *policy);
1777 int mlx5_flow_meter_flush(struct rte_eth_dev *dev,
1778 struct rte_mtr_error *error);
1779 void mlx5_flow_meter_rxq_flush(struct rte_eth_dev *dev);
1782 struct rte_pci_driver;
1783 int mlx5_os_get_dev_attr(struct mlx5_common_device *dev,
1784 struct mlx5_dev_attr *dev_attr);
1785 void mlx5_os_free_shared_dr(struct mlx5_priv *priv);
1786 int mlx5_os_net_probe(struct mlx5_common_device *cdev);
1787 void mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh);
1788 void mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh);
1789 void mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
1790 int mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
1792 int mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv, unsigned int iface_idx,
1793 struct rte_ether_addr *mac_addr,
1795 int mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable);
1796 int mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable);
1797 int mlx5_os_set_nonblock_channel_fd(int fd);
1798 void mlx5_os_mac_addr_flush(struct rte_eth_dev *dev);
1799 void mlx5_os_net_cleanup(void);
1803 int mlx5_txpp_start(struct rte_eth_dev *dev);
1804 void mlx5_txpp_stop(struct rte_eth_dev *dev);
1805 int mlx5_txpp_read_clock(struct rte_eth_dev *dev, uint64_t *timestamp);
1806 int mlx5_txpp_xstats_get(struct rte_eth_dev *dev,
1807 struct rte_eth_xstat *stats,
1808 unsigned int n, unsigned int n_used);
1809 int mlx5_txpp_xstats_reset(struct rte_eth_dev *dev);
1810 int mlx5_txpp_xstats_get_names(struct rte_eth_dev *dev,
1811 struct rte_eth_xstat_name *xstats_names,
1812 unsigned int n, unsigned int n_used);
1813 void mlx5_txpp_interrupt_handler(void *cb_arg);
1817 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev);
1819 /* mlx5_flow_aso.c */
1821 int mlx5_aso_queue_init(struct mlx5_dev_ctx_shared *sh,
1822 enum mlx5_access_aso_opc_mod aso_opc_mod);
1823 int mlx5_aso_flow_hit_queue_poll_start(struct mlx5_dev_ctx_shared *sh);
1824 int mlx5_aso_flow_hit_queue_poll_stop(struct mlx5_dev_ctx_shared *sh);
1825 void mlx5_aso_queue_uninit(struct mlx5_dev_ctx_shared *sh,
1826 enum mlx5_access_aso_opc_mod aso_opc_mod);
1827 int mlx5_aso_meter_update_by_wqe(struct mlx5_dev_ctx_shared *sh,
1828 struct mlx5_aso_mtr *mtr);
1829 int mlx5_aso_mtr_wait(struct mlx5_dev_ctx_shared *sh,
1830 struct mlx5_aso_mtr *mtr);
1831 int mlx5_aso_ct_update_by_wqe(struct mlx5_dev_ctx_shared *sh,
1832 struct mlx5_aso_ct_action *ct,
1833 const struct rte_flow_action_conntrack *profile);
1834 int mlx5_aso_ct_wait_ready(struct mlx5_dev_ctx_shared *sh,
1835 struct mlx5_aso_ct_action *ct);
1836 int mlx5_aso_ct_query_by_wqe(struct mlx5_dev_ctx_shared *sh,
1837 struct mlx5_aso_ct_action *ct,
1838 struct rte_flow_action_conntrack *profile);
1839 int mlx5_aso_ct_available(struct mlx5_dev_ctx_shared *sh,
1840 struct mlx5_aso_ct_action *ct);
1842 mlx5_get_supported_sw_parsing_offloads(const struct mlx5_hca_attr *attr);
1844 mlx5_get_supported_tunneling_offloads(const struct mlx5_hca_attr *attr);
1846 /* mlx5_flow_flex.c */
1848 struct rte_flow_item_flex_handle *
1849 flow_dv_item_create(struct rte_eth_dev *dev,
1850 const struct rte_flow_item_flex_conf *conf,
1851 struct rte_flow_error *error);
1852 int flow_dv_item_release(struct rte_eth_dev *dev,
1853 const struct rte_flow_item_flex_handle *flex_handle,
1854 struct rte_flow_error *error);
1855 int mlx5_flex_item_port_init(struct rte_eth_dev *dev);
1856 void mlx5_flex_item_port_cleanup(struct rte_eth_dev *dev);
1857 void mlx5_flex_flow_translate_item(struct rte_eth_dev *dev, void *matcher,
1858 void *key, const struct rte_flow_item *item,
1860 int mlx5_flex_acquire_index(struct rte_eth_dev *dev,
1861 struct rte_flow_item_flex_handle *handle,
1863 int mlx5_flex_release_index(struct rte_eth_dev *dev, int index);
1865 /* Flex parser list callbacks. */
1866 struct mlx5_list_entry *mlx5_flex_parser_create_cb(void *list_ctx, void *ctx);
1867 int mlx5_flex_parser_match_cb(void *list_ctx,
1868 struct mlx5_list_entry *iter, void *ctx);
1869 void mlx5_flex_parser_remove_cb(void *list_ctx, struct mlx5_list_entry *entry);
1870 struct mlx5_list_entry *mlx5_flex_parser_clone_cb(void *list_ctx,
1871 struct mlx5_list_entry *entry,
1873 void mlx5_flex_parser_clone_free_cb(void *tool_ctx,
1874 struct mlx5_list_entry *entry);
1875 #endif /* RTE_PMD_MLX5_H_ */