1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_H_
7 #define RTE_PMD_MLX5_H_
13 #include <netinet/in.h>
14 #include <sys/queue.h>
17 #include <rte_ether.h>
18 #include <rte_ethdev_driver.h>
19 #include <rte_rwlock.h>
20 #include <rte_interrupts.h>
21 #include <rte_errno.h>
24 #include <mlx5_glue.h>
25 #include <mlx5_devx_cmds.h>
27 #include <mlx5_common_mp.h>
28 #include <mlx5_common_mr.h>
30 #include "mlx5_defs.h"
31 #include "mlx5_utils.h"
33 #include "mlx5_autoconf.h"
36 #define MLX5_SH(dev) (((struct mlx5_priv *)(dev)->data->dev_private)->sh)
38 enum mlx5_ipool_index {
39 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
40 MLX5_IPOOL_DECAP_ENCAP = 0, /* Pool for encap/decap resource. */
41 MLX5_IPOOL_PUSH_VLAN, /* Pool for push vlan resource. */
42 MLX5_IPOOL_TAG, /* Pool for tag resource. */
43 MLX5_IPOOL_PORT_ID, /* Pool for port id resource. */
44 MLX5_IPOOL_JUMP, /* Pool for jump resource. */
45 MLX5_IPOOL_SAMPLE, /* Pool for sample resource. */
46 MLX5_IPOOL_DEST_ARRAY, /* Pool for destination array resource. */
48 MLX5_IPOOL_MTR, /* Pool for meter resource. */
49 MLX5_IPOOL_MCP, /* Pool for metadata resource. */
50 MLX5_IPOOL_HRXQ, /* Pool for hrxq resource. */
51 MLX5_IPOOL_MLX5_FLOW, /* Pool for mlx5 flow handle. */
52 MLX5_IPOOL_RTE_FLOW, /* Pool for rte_flow. */
53 MLX5_IPOOL_RSS_EXPANTION_FLOW_ID, /* Pool for Queue/RSS flow ID. */
54 MLX5_IPOOL_TUNNEL_ID, /* Pool for flow tunnel ID. */
55 MLX5_IPOOL_TNL_TBL_ID, /* Pool for tunnel table ID. */
60 * There are three reclaim memory mode supported.
61 * 0(none) means no memory reclaim.
62 * 1(light) means only PMD level reclaim.
63 * 2(aggressive) means both PMD and rdma-core level reclaim.
65 enum mlx5_reclaim_mem_mode {
66 MLX5_RCM_NONE, /* Don't reclaim memory. */
67 MLX5_RCM_LIGHT, /* Reclaim PMD level. */
68 MLX5_RCM_AGGR, /* Reclaim PMD and rdma-core level. */
71 /* Hash and cache list callback context. */
72 struct mlx5_flow_cb_ctx {
73 struct rte_eth_dev *dev;
74 struct rte_flow_error *error;
78 /* Device attributes used in mlx5 PMD */
79 struct mlx5_dev_attr {
80 uint64_t device_cap_flags_ex;
85 uint32_t raw_packet_caps;
86 uint32_t max_rwq_indirection_table_size;
88 uint32_t tso_supported_qpts;
91 uint32_t sw_parsing_offloads;
92 uint32_t min_single_stride_log_num_of_bytes;
93 uint32_t max_single_stride_log_num_of_bytes;
94 uint32_t min_single_wqe_log_num_of_strides;
95 uint32_t max_single_wqe_log_num_of_strides;
96 uint32_t stride_supported_qpts;
97 uint32_t tunnel_offloads_caps;
101 /** Data associated with devices to spawn. */
102 struct mlx5_dev_spawn_data {
103 uint32_t ifindex; /**< Network interface index. */
104 uint32_t max_port; /**< Device maximal port index. */
105 uint32_t phys_port; /**< Device physical port index. */
106 int pf_bond; /**< bonding device PF index. < 0 - no bonding */
107 struct mlx5_switch_info info; /**< Switch information. */
108 void *phys_dev; /**< Associated physical device. */
109 struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */
110 struct rte_pci_device *pci_dev; /**< Backend PCI device. */
113 /** Key string for IPC. */
114 #define MLX5_MP_NAME "net_mlx5_mp"
117 LIST_HEAD(mlx5_dev_list, mlx5_dev_ctx_shared);
119 /* Shared data between primary and secondary processes. */
120 struct mlx5_shared_data {
122 /* Global spinlock for primary and secondary processes. */
123 int init_done; /* Whether primary has done initialization. */
124 unsigned int secondary_cnt; /* Number of secondary processes init'd. */
125 struct mlx5_dev_list mem_event_cb_list;
126 rte_rwlock_t mem_event_rwlock;
129 /* Per-process data structure, not visible to other processes. */
130 struct mlx5_local_data {
131 int init_done; /* Whether a secondary has done initialization. */
134 extern struct mlx5_shared_data *mlx5_shared_data;
136 /* Dev ops structs */
137 extern const struct eth_dev_ops mlx5_os_dev_ops;
138 extern const struct eth_dev_ops mlx5_os_dev_sec_ops;
139 extern const struct eth_dev_ops mlx5_os_dev_ops_isolate;
141 struct mlx5_counter_ctrl {
142 /* Name of the counter. */
143 char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE];
144 /* Name of the counter on the device table. */
145 char ctr_name[RTE_ETH_XSTATS_NAME_SIZE];
146 uint32_t dev:1; /**< Nonzero for dev counters. */
149 struct mlx5_xstats_ctrl {
150 /* Number of device stats. */
152 /* Number of device stats identified by PMD. */
153 uint16_t mlx5_stats_n;
154 /* Index in the device counters table. */
155 uint16_t dev_table_idx[MLX5_MAX_XSTATS];
156 uint64_t base[MLX5_MAX_XSTATS];
157 uint64_t xstats[MLX5_MAX_XSTATS];
158 uint64_t hw_stats[MLX5_MAX_XSTATS];
159 struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS];
162 struct mlx5_stats_ctrl {
163 /* Base for imissed counter. */
164 uint64_t imissed_base;
168 /* Default PMD specific parameter value. */
169 #define MLX5_ARG_UNSET (-1)
171 #define MLX5_LRO_SUPPORTED(dev) \
172 (((struct mlx5_priv *)((dev)->data->dev_private))->config.lro.supported)
174 /* Maximal size of coalesced segment for LRO is set in chunks of 256 Bytes. */
175 #define MLX5_LRO_SEG_CHUNK_SIZE 256u
177 /* Maximal size of aggregated LRO packet. */
178 #define MLX5_MAX_LRO_SIZE (UINT8_MAX * MLX5_LRO_SEG_CHUNK_SIZE)
180 /* Maximal number of segments to split. */
181 #define MLX5_MAX_RXQ_NSEG (1u << MLX5_MAX_LOG_RQ_SEGS)
183 /* LRO configurations structure. */
184 struct mlx5_lro_config {
185 uint32_t supported:1; /* Whether LRO is supported. */
186 uint32_t timeout; /* User configuration. */
190 * Device configuration structure.
192 * Merged configuration from:
194 * - Device capabilities,
195 * - User device parameters disabled features.
197 struct mlx5_dev_config {
198 unsigned int hw_csum:1; /* Checksum offload is supported. */
199 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */
200 unsigned int hw_vlan_insert:1; /* VLAN insertion in WQE is supported. */
201 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */
202 unsigned int hw_padding:1; /* End alignment padding is supported. */
203 unsigned int vf:1; /* This is a VF. */
204 unsigned int tunnel_en:1;
205 /* Whether tunnel stateless offloads are supported. */
206 unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */
207 unsigned int cqe_comp:1; /* CQE compression is enabled. */
208 unsigned int cqe_pad:1; /* CQE padding is enabled. */
209 unsigned int tso:1; /* Whether TSO is supported. */
210 unsigned int rx_vec_en:1; /* Rx vector is enabled. */
211 unsigned int mr_ext_memseg_en:1;
212 /* Whether memseg should be extended for MR creation. */
213 unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */
214 unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */
215 unsigned int dv_esw_en:1; /* Enable E-Switch DV flow. */
216 unsigned int dv_flow_en:1; /* Enable DV flow. */
217 unsigned int dv_xmeta_en:2; /* Enable extensive flow metadata. */
218 unsigned int lacp_by_user:1;
219 /* Enable user to manage LACP traffic. */
220 unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */
221 unsigned int devx:1; /* Whether devx interface is available or not. */
222 unsigned int dest_tir:1; /* Whether advanced DR API is available. */
223 unsigned int reclaim_mode:2; /* Memory reclaim mode. */
224 unsigned int rt_timestamp:1; /* realtime timestamp format. */
225 unsigned int sys_mem_en:1; /* The default memory allocator. */
226 unsigned int decap_en:1; /* Whether decap will be used or not. */
227 unsigned int dv_miss_info:1; /* restore packet after partial hw miss */
229 unsigned int enabled:1; /* Whether MPRQ is enabled. */
230 unsigned int stride_num_n; /* Number of strides. */
231 unsigned int stride_size_n; /* Size of a stride. */
232 unsigned int min_stride_size_n; /* Min size of a stride. */
233 unsigned int max_stride_size_n; /* Max size of a stride. */
234 unsigned int max_memcpy_len;
235 /* Maximum packet size to memcpy Rx packets. */
236 unsigned int min_rxqs_num;
237 /* Rx queue count threshold to enable MPRQ. */
238 } mprq; /* Configurations for Multi-Packet RQ. */
239 int mps; /* Multi-packet send supported mode. */
240 int dbnc; /* Skip doorbell register write barrier. */
241 unsigned int flow_prio; /* Number of flow priorities. */
242 enum modify_reg flow_mreg_c[MLX5_MREG_C_NUM];
243 /* Availibility of mreg_c's. */
244 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */
245 unsigned int ind_table_max_size; /* Maximum indirection table size. */
246 unsigned int max_dump_files_num; /* Maximum dump files per queue. */
247 unsigned int log_hp_size; /* Single hairpin queue data size in total. */
248 int txqs_inline; /* Queue number threshold for inlining. */
249 int txq_inline_min; /* Minimal amount of data bytes to inline. */
250 int txq_inline_max; /* Max packet size for inlining with SEND. */
251 int txq_inline_mpw; /* Max packet size for inlining with eMPW. */
252 int tx_pp; /* Timestamp scheduling granularity in nanoseconds. */
253 int tx_skew; /* Tx scheduling skew between WQE and data on wire. */
254 struct mlx5_hca_attr hca_attr; /* HCA attributes. */
255 struct mlx5_lro_config lro; /* LRO configuration. */
260 * Type of object being allocated.
262 enum mlx5_verbs_alloc_type {
263 MLX5_VERBS_ALLOC_TYPE_NONE,
264 MLX5_VERBS_ALLOC_TYPE_TX_QUEUE,
265 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE,
268 /* Structure for VF VLAN workaround. */
269 struct mlx5_vf_vlan {
275 * Verbs allocator needs a context to know in the callback which kind of
276 * resources it is allocating.
278 struct mlx5_verbs_alloc_ctx {
279 enum mlx5_verbs_alloc_type type; /* Kind of object being allocated. */
280 const void *obj; /* Pointer to the DPDK object. */
283 /* Flow drop context necessary due to Verbs API. */
285 struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */
286 struct mlx5_rxq_obj *rxq; /* Rx queue object. */
289 #define MLX5_COUNTERS_PER_POOL 512
290 #define MLX5_MAX_PENDING_QUERIES 4
291 #define MLX5_CNT_CONTAINER_RESIZE 64
292 #define MLX5_CNT_SHARED_OFFSET 0x80000000
293 #define IS_SHARED_CNT(cnt) (!!((cnt) & MLX5_CNT_SHARED_OFFSET))
294 #define IS_BATCH_CNT(cnt) (((cnt) & (MLX5_CNT_SHARED_OFFSET - 1)) >= \
295 MLX5_CNT_BATCH_OFFSET)
296 #define MLX5_CNT_SIZE (sizeof(struct mlx5_flow_counter))
297 #define MLX5_AGE_SIZE (sizeof(struct mlx5_age_param))
299 #define MLX5_CNT_LEN(pool) \
301 ((pool)->is_aged ? MLX5_AGE_SIZE : 0))
302 #define MLX5_POOL_GET_CNT(pool, index) \
303 ((struct mlx5_flow_counter *) \
304 ((uint8_t *)((pool) + 1) + (index) * (MLX5_CNT_LEN(pool))))
305 #define MLX5_CNT_ARRAY_IDX(pool, cnt) \
306 ((int)(((uint8_t *)(cnt) - (uint8_t *)((pool) + 1)) / \
309 * The pool index and offset of counter in the pool array makes up the
310 * counter index. In case the counter is from pool 0 and offset 0, it
311 * should plus 1 to avoid index 0, since 0 means invalid counter index
314 #define MLX5_MAKE_CNT_IDX(pi, offset) \
315 ((pi) * MLX5_COUNTERS_PER_POOL + (offset) + 1)
316 #define MLX5_CNT_TO_AGE(cnt) \
317 ((struct mlx5_age_param *)((cnt) + 1))
319 * The maximum single counter is 0x800000 as MLX5_CNT_BATCH_OFFSET
320 * defines. The pool size is 512, pool index should never reach
323 #define POOL_IDX_INVALID UINT16_MAX
327 AGE_FREE, /* Initialized state. */
328 AGE_CANDIDATE, /* Counter assigned to flows. */
329 AGE_TMOUT, /* Timeout, wait for rte_flow_get_aged_flows and destroy. */
332 enum mlx5_counter_type {
333 MLX5_COUNTER_TYPE_ORIGIN,
334 MLX5_COUNTER_TYPE_AGE,
335 MLX5_COUNTER_TYPE_MAX,
338 /* Counter age parameter. */
339 struct mlx5_age_param {
340 uint16_t state; /**< Age state (atomically accessed). */
341 uint16_t port_id; /**< Port id of the counter. */
342 uint32_t timeout:24; /**< Aging timeout in seconds. */
343 uint32_t sec_since_last_hit;
344 /**< Time in seconds since last hit (atomically accessed). */
345 void *context; /**< Flow counter age context. */
348 struct flow_counter_stats {
353 /* Shared counters information for counters. */
354 struct mlx5_flow_counter_shared {
355 uint32_t id; /**< User counter ID. */
358 /* Shared counter configuration. */
359 struct mlx5_shared_counter_conf {
360 struct rte_eth_dev *dev; /* The device shared counter belongs to. */
361 uint32_t id; /* The shared counter ID. */
364 struct mlx5_flow_counter_pool;
365 /* Generic counters information. */
366 struct mlx5_flow_counter {
369 * User-defined counter shared info is only used during
370 * counter active time. And aging counter sharing is not
371 * supported, so active shared counter will not be chained
372 * to the aging list. For shared counter, only when it is
373 * released, the TAILQ entry memory will be used, at that
374 * time, shared memory is not used anymore.
376 * Similarly to none-batch counter dcs, since it doesn't
377 * support aging, while counter is allocated, the entry
378 * memory is not used anymore. In this case, as bytes
379 * memory is used only when counter is allocated, and
380 * entry memory is used only when counter is free. The
381 * dcs pointer can be saved to these two different place
382 * at different stage. It will eliminate the individual
383 * counter extend struct.
385 TAILQ_ENTRY(mlx5_flow_counter) next;
386 /**< Pointer to the next flow counter structure. */
388 struct mlx5_flow_counter_shared shared_info;
389 /**< Shared counter information. */
390 void *dcs_when_active;
392 * For non-batch mode, the dcs will be saved
393 * here when the counter is free.
398 uint64_t hits; /**< Reset value of hits packets. */
399 struct mlx5_flow_counter_pool *pool; /**< Counter pool. */
402 uint64_t bytes; /**< Reset value of bytes. */
405 * For non-batch mode, the dcs will be saved here
406 * when the counter is free.
409 void *action; /**< Pointer to the dv action. */
412 TAILQ_HEAD(mlx5_counters, mlx5_flow_counter);
414 /* Generic counter pool structure - query is in pool resolution. */
415 struct mlx5_flow_counter_pool {
416 TAILQ_ENTRY(mlx5_flow_counter_pool) next;
417 struct mlx5_counters counters[2]; /* Free counter list. */
418 struct mlx5_devx_obj *min_dcs;
419 /* The devx object of the minimum counter ID. */
420 uint64_t time_of_last_age_check;
421 /* System time (from rte_rdtsc()) read in the last aging check. */
422 uint32_t index:30; /* Pool index in container. */
423 uint32_t is_aged:1; /* Pool with aging counter. */
424 volatile uint32_t query_gen:1; /* Query round. */
425 rte_spinlock_t sl; /* The pool lock. */
426 rte_spinlock_t csl; /* The pool counter free list lock. */
427 struct mlx5_counter_stats_raw *raw;
428 struct mlx5_counter_stats_raw *raw_hw;
429 /* The raw on HW working. */
432 /* Memory management structure for group of counter statistics raws. */
433 struct mlx5_counter_stats_mem_mng {
434 LIST_ENTRY(mlx5_counter_stats_mem_mng) next;
435 struct mlx5_counter_stats_raw *raws;
436 struct mlx5_devx_obj *dm;
440 /* Raw memory structure for the counter statistics values of a pool. */
441 struct mlx5_counter_stats_raw {
442 LIST_ENTRY(mlx5_counter_stats_raw) next;
443 struct mlx5_counter_stats_mem_mng *mem_mng;
444 volatile struct flow_counter_stats *data;
447 TAILQ_HEAD(mlx5_counter_pools, mlx5_flow_counter_pool);
449 /* Counter global management structure. */
450 struct mlx5_flow_counter_mng {
451 volatile uint16_t n_valid; /* Number of valid pools. */
452 uint16_t n; /* Number of pools. */
453 uint16_t last_pool_idx; /* Last used pool index */
454 int min_id; /* The minimum counter ID in the pools. */
455 int max_id; /* The maximum counter ID in the pools. */
456 rte_spinlock_t pool_update_sl; /* The pool update lock. */
457 rte_spinlock_t csl[MLX5_COUNTER_TYPE_MAX];
458 /* The counter free list lock. */
459 struct mlx5_counters counters[MLX5_COUNTER_TYPE_MAX];
460 /* Free counter list. */
461 struct mlx5_flow_counter_pool **pools; /* Counter pool array. */
462 struct mlx5_counter_stats_mem_mng *mem_mng;
463 /* Hold the memory management for the next allocated pools raws. */
464 struct mlx5_counters flow_counters; /* Legacy flow counter list. */
465 uint8_t pending_queries;
467 uint8_t query_thread_on;
468 bool relaxed_ordering;
469 bool counter_fallback; /* Use counter fallback management. */
470 LIST_HEAD(mem_mngs, mlx5_counter_stats_mem_mng) mem_mngs;
471 LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws;
474 #define MLX5_AGE_EVENT_NEW 1
475 #define MLX5_AGE_TRIGGER 2
476 #define MLX5_AGE_SET(age_info, BIT) \
477 ((age_info)->flags |= (1 << (BIT)))
478 #define MLX5_AGE_GET(age_info, BIT) \
479 ((age_info)->flags & (1 << (BIT)))
480 #define GET_PORT_AGE_INFO(priv) \
481 (&((priv)->sh->port[(priv)->dev_port - 1].age_info))
482 /* Current time in seconds. */
483 #define MLX5_CURR_TIME_SEC (rte_rdtsc() / rte_get_tsc_hz())
485 /* Aging information for per port. */
486 struct mlx5_age_info {
487 uint8_t flags; /* Indicate if is new event or need to be triggered. */
488 struct mlx5_counters aged_counters; /* Aged flow counter list. */
489 rte_spinlock_t aged_sl; /* Aged flow counter list lock. */
492 /* Per port data of shared IB device. */
493 struct mlx5_dev_shared_port {
495 uint32_t devx_ih_port_id;
497 * Interrupt handler port_id. Used by shared interrupt
498 * handler to find the corresponding rte_eth device
499 * by IB port index. If value is equal or greater
500 * RTE_MAX_ETHPORTS it means there is no subhandler
501 * installed for specified IB port index.
503 struct mlx5_age_info age_info;
504 /* Aging information for per port. */
507 /* Table key of the hash organization. */
508 union mlx5_flow_tbl_key {
510 /* Table ID should be at the lowest address. */
511 uint32_t table_id; /**< ID of the table. */
512 uint16_t dummy; /**< Dummy table for DV API. */
513 uint8_t domain; /**< 1 - FDB, 0 - NIC TX/RX. */
514 uint8_t direction; /**< 1 - egress, 0 - ingress. */
516 uint64_t v64; /**< full 64bits value of key */
519 /* Table structure. */
520 struct mlx5_flow_tbl_resource {
521 void *obj; /**< Pointer to DR table object. */
522 uint32_t refcnt; /**< Reference counter. */
525 #define MLX5_MAX_TABLES UINT16_MAX
526 #define MLX5_HAIRPIN_TX_TABLE (UINT16_MAX - 1)
527 /* Reserve the last two tables for metadata register copy. */
528 #define MLX5_FLOW_MREG_ACT_TABLE_GROUP (MLX5_MAX_TABLES - 1)
529 #define MLX5_FLOW_MREG_CP_TABLE_GROUP (MLX5_MAX_TABLES - 2)
530 /* Tables for metering splits should be added here. */
531 #define MLX5_MAX_TABLES_EXTERNAL (MLX5_MAX_TABLES - 3)
532 #define MLX5_FLOW_TABLE_LEVEL_METER (MLX5_MAX_TABLES - 4)
533 #define MLX5_FLOW_TABLE_LEVEL_SUFFIX (MLX5_MAX_TABLES - 3)
534 #define MLX5_MAX_TABLES_FDB UINT16_MAX
535 #define MLX5_FLOW_TABLE_FACTOR 10
537 /* ID generation structure. */
538 struct mlx5_flow_id_pool {
539 uint32_t *free_arr; /**< Pointer to the a array of free values. */
541 /**< The next index that can be used without any free elements. */
542 uint32_t *curr; /**< Pointer to the index to pop. */
543 uint32_t *last; /**< Pointer to the last element in the empty arrray. */
544 uint32_t max_id; /**< Maximum id can be allocated from the pool. */
547 /* Tx pacing queue structure - for Clock and Rearm queues. */
548 struct mlx5_txpp_wq {
549 /* Completion Queue related data.*/
550 struct mlx5_devx_obj *cq;
553 volatile void *cq_buf;
554 volatile struct mlx5_cqe *cqes;
556 volatile uint32_t *cq_dbrec;
559 /* Send Queue related data.*/
560 struct mlx5_devx_obj *sq;
563 volatile void *sq_buf;
564 volatile struct mlx5_wqe *wqes;
566 uint16_t sq_size; /* Number of WQEs in the queue. */
567 uint16_t sq_ci; /* Next WQE to execute. */
568 volatile uint32_t *sq_dbrec;
571 /* Tx packet pacing internal timestamp. */
572 struct mlx5_txpp_ts {
577 /* Tx packet pacing structure. */
578 struct mlx5_dev_txpp {
579 pthread_mutex_t mutex; /* Pacing create/destroy mutex. */
580 uint32_t refcnt; /* Pacing reference counter. */
581 uint32_t freq; /* Timestamp frequency, Hz. */
582 uint32_t tick; /* Completion tick duration in nanoseconds. */
583 uint32_t test; /* Packet pacing test mode. */
584 int32_t skew; /* Scheduling skew. */
585 struct rte_intr_handle intr_handle; /* Periodic interrupt. */
586 void *echan; /* Event Channel. */
587 struct mlx5_txpp_wq clock_queue; /* Clock Queue. */
588 struct mlx5_txpp_wq rearm_queue; /* Clock Queue. */
589 void *pp; /* Packet pacing context. */
590 uint16_t pp_id; /* Packet pacing context index. */
591 uint16_t ts_n; /* Number of captured timestamps. */
592 uint16_t ts_p; /* Pointer to statisticks timestamp. */
593 struct mlx5_txpp_ts *tsa; /* Timestamps sliding window stats. */
594 struct mlx5_txpp_ts ts; /* Cached completion id/timestamp. */
595 uint32_t sync_lost:1; /* ci/timestamp synchronization lost. */
596 /* Statistics counters. */
597 uint64_t err_miss_int; /* Missed service interrupt. */
598 uint64_t err_rearm_queue; /* Rearm Queue errors. */
599 uint64_t err_clock_queue; /* Clock Queue errors. */
600 uint64_t err_ts_past; /* Timestamp in the past. */
601 uint64_t err_ts_future; /* Timestamp in the distant future. */
604 /* Supported flex parser profile ID. */
605 enum mlx5_flex_parser_profile_id {
606 MLX5_FLEX_PARSER_ECPRI_0 = 0,
607 MLX5_FLEX_PARSER_MAX = 8,
610 /* Sample ID information of flex parser structure. */
611 struct mlx5_flex_parser_profiles {
612 uint32_t num; /* Actual number of samples. */
613 uint32_t ids[8]; /* Sample IDs for this profile. */
614 uint8_t offset[8]; /* Bytes offset of each parser. */
615 void *obj; /* Flex parser node object. */
619 * Shared Infiniband device context for Master/Representors
620 * which belong to same IB device with multiple IB ports.
622 struct mlx5_dev_ctx_shared {
623 LIST_ENTRY(mlx5_dev_ctx_shared) next;
625 uint32_t devx:1; /* Opened with DV. */
626 uint32_t eqn; /* Event Queue number. */
627 uint32_t max_port; /* Maximal IB device port index. */
628 void *ctx; /* Verbs/DV/DevX context. */
629 void *pd; /* Protection Domain. */
630 uint32_t pdn; /* Protection Domain number. */
631 uint32_t tdn; /* Transport Domain number. */
632 char ibdev_name[DEV_SYSFS_NAME_MAX]; /* SYSFS dev name. */
633 char ibdev_path[DEV_SYSFS_PATH_MAX]; /* SYSFS dev path for secondary */
634 struct mlx5_dev_attr device_attr; /* Device properties. */
635 int numa_node; /* Numa node of backing physical device. */
636 LIST_ENTRY(mlx5_dev_ctx_shared) mem_event_cb;
637 /**< Called by memory event callback. */
638 struct mlx5_mr_share_cache share_cache;
639 /* Packet pacing related structure. */
640 struct mlx5_dev_txpp txpp;
641 /* Shared DV/DR flow data section. */
642 uint32_t dv_meta_mask; /* flow META metadata supported mask. */
643 uint32_t dv_mark_mask; /* flow MARK metadata supported mask. */
644 uint32_t dv_regc0_mask; /* available bits of metatada reg_c[0]. */
645 void *fdb_domain; /* FDB Direct Rules name space handle. */
646 void *rx_domain; /* RX Direct Rules name space handle. */
647 void *tx_domain; /* TX Direct Rules name space handle. */
649 rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */
650 rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX];
651 /* UAR same-page access control required in 32bit implementations. */
653 struct mlx5_hlist *flow_tbls;
654 struct mlx5_flow_tunnel_hub *tunnel_hub;
655 /* Direct Rules tables for FDB, NIC TX+RX */
656 void *esw_drop_action; /* Pointer to DR E-Switch drop action. */
657 void *pop_vlan_action; /* Pointer to DR pop VLAN action. */
658 struct mlx5_hlist *encaps_decaps; /* Encap/decap action hash list. */
659 struct mlx5_hlist *modify_cmds;
660 struct mlx5_hlist *tag_table;
661 struct mlx5_cache_list port_id_action_list; /* Port ID action cache. */
662 struct mlx5_cache_list push_vlan_action_list; /* Push VLAN actions. */
663 struct mlx5_cache_list sample_action_list; /* List of sample actions. */
664 struct mlx5_cache_list dest_array_list;
665 /* List of destination array actions. */
666 struct mlx5_flow_counter_mng cmng; /* Counters management structure. */
667 void *default_miss_action; /* Default miss action. */
668 struct mlx5_indexed_pool *ipool[MLX5_IPOOL_MAX];
669 /* Memory Pool for mlx5 flow resources. */
670 struct mlx5_l3t_tbl *cnt_id_tbl; /* Shared counter lookup table. */
671 /* Shared interrupt handler section. */
672 struct rte_intr_handle intr_handle; /* Interrupt handler for device. */
673 struct rte_intr_handle intr_handle_devx; /* DEVX interrupt handler. */
674 void *devx_comp; /* DEVX async comp obj. */
675 struct mlx5_devx_obj *tis; /* TIS object. */
676 struct mlx5_devx_obj *td; /* Transport domain. */
677 void *tx_uar; /* Tx/packet pacing shared UAR. */
678 struct mlx5_flex_parser_profiles fp[MLX5_FLEX_PARSER_MAX];
679 /* Flex parser profiles information. */
680 void *devx_rx_uar; /* DevX UAR for Rx. */
681 struct mlx5_dev_shared_port port[]; /* per device port data array. */
684 /* Per-process private structure. */
685 struct mlx5_proc_priv {
687 /* Size of UAR register table. */
689 /* Table of UAR registers for each process. */
692 /* MTR profile list. */
693 TAILQ_HEAD(mlx5_mtr_profiles, mlx5_flow_meter_profile);
695 TAILQ_HEAD(mlx5_flow_meters, mlx5_flow_meter);
697 /* RSS description. */
698 struct mlx5_flow_rss_desc {
700 uint32_t queue_num; /**< Number of entries in @p queue. */
701 uint64_t types; /**< Specific RSS hash types (see ETH_RSS_*). */
702 uint64_t hash_fields; /* Verbs Hash fields. */
703 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
704 uint32_t key_len; /**< RSS hash key len. */
705 uint32_t tunnel; /**< Queue in tunnel. */
707 uint16_t *queue; /**< Destination queues. */
708 const uint16_t *const_q; /**< Const pointer convert. */
710 bool standalone; /**< Queue is standalone or not. */
713 #define MLX5_PROC_PRIV(port_id) \
714 ((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private)
716 /* Verbs/DevX Rx queue elements. */
717 struct mlx5_rxq_obj {
718 LIST_ENTRY(mlx5_rxq_obj) next; /* Pointer to the next element. */
719 struct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */
720 int fd; /* File descriptor for event channel */
724 void *wq; /* Work Queue. */
725 void *ibv_cq; /* Completion Queue. */
729 struct mlx5_devx_obj *rq; /* DevX Rx Queue object. */
730 struct mlx5_devx_obj *devx_cq; /* DevX CQ object. */
736 /* Indirection table. */
737 struct mlx5_ind_table_obj {
738 LIST_ENTRY(mlx5_ind_table_obj) next; /* Pointer to the next element. */
739 uint32_t refcnt; /* Reference counter. */
742 void *ind_table; /**< Indirection table. */
743 struct mlx5_devx_obj *rqt; /* DevX RQT object. */
745 uint32_t queues_n; /**< Number of queues in the list. */
746 uint16_t queues[]; /**< Queue list. */
752 struct mlx5_cache_entry entry; /* Cache entry. */
753 uint32_t refcnt; /* Reference counter. */
754 uint32_t standalone:1; /* This object used in shared action. */
755 struct mlx5_ind_table_obj *ind_table; /* Indirection table. */
758 void *qp; /* Verbs queue pair. */
759 struct mlx5_devx_obj *tir; /* DevX TIR object. */
761 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
762 void *action; /* DV QP action pointer. */
764 uint64_t hash_fields; /* Verbs Hash fields. */
765 uint32_t rss_key_len; /* Hash key length in bytes. */
766 uint32_t idx; /* Hash Rx queue index. */
767 uint8_t rss_key[]; /* Hash key. */
770 /* Verbs/DevX Tx queue elements. */
771 struct mlx5_txq_obj {
772 LIST_ENTRY(mlx5_txq_obj) next; /* Pointer to the next element. */
773 struct mlx5_txq_ctrl *txq_ctrl; /* Pointer to the control queue. */
777 void *cq; /* Completion Queue. */
778 void *qp; /* Queue Pair. */
781 struct mlx5_devx_obj *sq;
782 /* DevX object for Sx queue. */
783 struct mlx5_devx_obj *tis; /* The TIS object. */
786 struct rte_eth_dev *dev;
787 struct mlx5_devx_obj *cq_devx;
790 int64_t cq_dbrec_offset;
791 struct mlx5_devx_dbr_page *cq_dbrec_page;
792 struct mlx5_devx_obj *sq_devx;
795 int64_t sq_dbrec_offset;
796 struct mlx5_devx_dbr_page *sq_dbrec_page;
801 enum mlx5_rxq_modify_type {
802 MLX5_RXQ_MOD_ERR2RST, /* modify state from error to reset. */
803 MLX5_RXQ_MOD_RST2RDY, /* modify state from reset to ready. */
804 MLX5_RXQ_MOD_RDY2ERR, /* modify state from ready to error. */
805 MLX5_RXQ_MOD_RDY2RST, /* modify state from ready to reset. */
808 enum mlx5_txq_modify_type {
809 MLX5_TXQ_MOD_RST2RDY, /* modify state from reset to ready. */
810 MLX5_TXQ_MOD_RDY2RST, /* modify state from ready to reset. */
811 MLX5_TXQ_MOD_ERR2RDY, /* modify state from error to ready. */
814 /* HW objects operations structure. */
815 struct mlx5_obj_ops {
816 int (*rxq_obj_modify_vlan_strip)(struct mlx5_rxq_obj *rxq_obj, int on);
817 int (*rxq_obj_new)(struct rte_eth_dev *dev, uint16_t idx);
818 int (*rxq_event_get)(struct mlx5_rxq_obj *rxq_obj);
819 int (*rxq_obj_modify)(struct mlx5_rxq_obj *rxq_obj, uint8_t type);
820 void (*rxq_obj_release)(struct mlx5_rxq_obj *rxq_obj);
821 int (*ind_table_new)(struct rte_eth_dev *dev, const unsigned int log_n,
822 struct mlx5_ind_table_obj *ind_tbl);
823 void (*ind_table_destroy)(struct mlx5_ind_table_obj *ind_tbl);
824 int (*hrxq_new)(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq,
825 int tunnel __rte_unused);
826 int (*hrxq_modify)(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq,
827 const uint8_t *rss_key,
828 uint64_t hash_fields,
829 const struct mlx5_ind_table_obj *ind_tbl);
830 void (*hrxq_destroy)(struct mlx5_hrxq *hrxq);
831 int (*drop_action_create)(struct rte_eth_dev *dev);
832 void (*drop_action_destroy)(struct rte_eth_dev *dev);
833 int (*txq_obj_new)(struct rte_eth_dev *dev, uint16_t idx);
834 int (*txq_obj_modify)(struct mlx5_txq_obj *obj,
835 enum mlx5_txq_modify_type type, uint8_t dev_port);
836 void (*txq_obj_release)(struct mlx5_txq_obj *txq_obj);
840 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */
841 struct mlx5_dev_ctx_shared *sh; /* Shared device context. */
842 uint32_t dev_port; /* Device port number. */
843 struct rte_pci_device *pci_dev; /* Backend PCI device. */
844 struct rte_ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */
845 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES);
846 /* Bit-field of MAC addresses owned by the PMD. */
847 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */
848 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */
849 /* Device properties. */
850 uint16_t mtu; /* Configured MTU. */
851 unsigned int isolated:1; /* Whether isolated mode is enabled. */
852 unsigned int representor:1; /* Device is a port representor. */
853 unsigned int master:1; /* Device is a E-Switch master. */
854 unsigned int txpp_en:1; /* Tx packet pacing enabled. */
855 unsigned int mtr_en:1; /* Whether support meter. */
856 unsigned int mtr_reg_share:1; /* Whether support meter REG_C share. */
857 unsigned int sampler_en:1; /* Whether support sampler. */
858 uint16_t domain_id; /* Switch domain identifier. */
859 uint16_t vport_id; /* Associated VF vport index (if any). */
860 uint32_t vport_meta_tag; /* Used for vport index match ove VF LAG. */
861 uint32_t vport_meta_mask; /* Used for vport index field match mask. */
862 int32_t representor_id; /* Port representor identifier. */
863 int32_t pf_bond; /* >=0 means PF index in bonding configuration. */
864 unsigned int if_index; /* Associated kernel network device index. */
865 uint32_t bond_ifindex; /**< Bond interface index. */
866 char bond_name[IF_NAMESIZE]; /**< Bond interface name. */
868 unsigned int rxqs_n; /* RX queues array size. */
869 unsigned int txqs_n; /* TX queues array size. */
870 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */
871 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */
872 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
873 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */
874 unsigned int (*reta_idx)[]; /* RETA index table. */
875 unsigned int reta_idx_n; /* RETA index size. */
876 struct mlx5_drop drop_queue; /* Flow drop queues. */
877 uint32_t flows; /* RTE Flow rules. */
878 uint32_t ctrl_flows; /* Control flow rules. */
879 rte_spinlock_t flow_list_lock;
880 struct mlx5_obj_ops obj_ops; /* HW objects operations. */
881 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */
882 LIST_HEAD(rxqobj, mlx5_rxq_obj) rxqsobj; /* Verbs/DevX Rx queues. */
883 struct mlx5_cache_list hrxqs; /* Hash Rx queues. */
884 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */
885 LIST_HEAD(txqobj, mlx5_txq_obj) txqsobj; /* Verbs/DevX Tx queues. */
886 /* Indirection tables. */
887 LIST_HEAD(ind_tables, mlx5_ind_table_obj) ind_tbls;
888 /* Pointer to next element. */
889 uint32_t refcnt; /**< Reference counter. */
890 /**< Verbs modify header action object. */
891 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
892 uint8_t max_lro_msg_size;
893 /* Tags resources cache. */
894 uint32_t link_speed_capa; /* Link speed capabilities. */
895 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */
896 struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */
897 struct mlx5_dev_config config; /* Device configuration. */
898 struct mlx5_verbs_alloc_ctx verbs_alloc_ctx;
899 /* Context for Verbs allocator. */
900 int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */
901 int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */
902 struct mlx5_dbr_page_list dbrpgs; /* Door-bell pages. */
903 struct mlx5_nl_vlan_vmwa_context *vmwa_context; /* VLAN WA context. */
904 struct mlx5_hlist *mreg_cp_tbl;
905 /* Hash table of Rx metadata register copy table. */
906 uint8_t mtr_sfx_reg; /* Meter prefix-suffix flow match REG_C. */
907 uint8_t mtr_color_reg; /* Meter color match REG_C. */
908 struct mlx5_mtr_profiles flow_meter_profiles; /* MTR profile list. */
909 struct mlx5_flow_meters flow_meters; /* MTR list. */
910 uint8_t skip_default_rss_reta; /* Skip configuration of default reta. */
911 uint8_t fdb_def_rule; /* Whether fdb jump to table 1 is configured. */
912 struct mlx5_mp_id mp_id; /* ID of a multi-process process */
913 LIST_HEAD(fdir, mlx5_fdir_flow) fdir_flows; /* fdir flows. */
914 rte_spinlock_t shared_act_sl; /* Shared actions spinlock. */
915 LIST_HEAD(shared_action, rte_flow_shared_action) shared_actions;
919 #define PORT_ID(priv) ((priv)->dev_data->port_id)
920 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)])
922 struct rte_hairpin_peer_info {
926 uint16_t tx_explicit;
927 uint16_t manual_bind;
932 int mlx5_getenv_int(const char *);
933 int mlx5_proc_priv_init(struct rte_eth_dev *dev);
934 int mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev,
935 struct rte_eth_udp_tunnel *udp_tunnel);
936 uint16_t mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev);
937 int mlx5_dev_close(struct rte_eth_dev *dev);
939 /* Macro to iterate over all valid ports for mlx5 driver. */
940 #define MLX5_ETH_FOREACH_DEV(port_id, pci_dev) \
941 for (port_id = mlx5_eth_find_next(0, pci_dev); \
942 port_id < RTE_MAX_ETHPORTS; \
943 port_id = mlx5_eth_find_next(port_id + 1, pci_dev))
944 int mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs);
945 struct mlx5_dev_ctx_shared *
946 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
947 const struct mlx5_dev_config *config);
948 void mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh);
949 void mlx5_free_table_hash_list(struct mlx5_priv *priv);
950 int mlx5_alloc_table_hash_list(struct mlx5_priv *priv);
951 void mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
952 struct mlx5_dev_config *config);
953 void mlx5_set_metadata_mask(struct rte_eth_dev *dev);
954 int mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
955 struct mlx5_dev_config *config);
956 int mlx5_dev_configure(struct rte_eth_dev *dev);
957 int mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info);
958 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size);
959 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
960 int mlx5_hairpin_cap_get(struct rte_eth_dev *dev,
961 struct rte_eth_hairpin_cap *cap);
962 bool mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev);
963 int mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev);
967 int mlx5_dev_configure(struct rte_eth_dev *dev);
968 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver,
970 int mlx5_dev_infos_get(struct rte_eth_dev *dev,
971 struct rte_eth_dev_info *info);
972 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev);
973 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
974 int mlx5_hairpin_cap_get(struct rte_eth_dev *dev,
975 struct rte_eth_hairpin_cap *cap);
976 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev);
977 struct mlx5_priv *mlx5_port_to_eswitch_info(uint16_t port, bool valid);
978 struct mlx5_priv *mlx5_dev_to_eswitch_info(struct rte_eth_dev *dev);
979 int mlx5_dev_configure_rss_reta(struct rte_eth_dev *dev);
981 /* mlx5_ethdev_os.c */
983 unsigned int mlx5_ifindex(const struct rte_eth_dev *dev);
984 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]);
985 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu);
986 int mlx5_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
987 int mlx5_read_clock(struct rte_eth_dev *dev, uint64_t *clock);
988 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete);
989 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev,
990 struct rte_eth_fc_conf *fc_conf);
991 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev,
992 struct rte_eth_fc_conf *fc_conf);
993 void mlx5_dev_interrupt_handler(void *arg);
994 void mlx5_dev_interrupt_handler_devx(void *arg);
995 int mlx5_set_link_down(struct rte_eth_dev *dev);
996 int mlx5_set_link_up(struct rte_eth_dev *dev);
997 int mlx5_is_removed(struct rte_eth_dev *dev);
998 int mlx5_sysfs_switch_info(unsigned int ifindex,
999 struct mlx5_switch_info *info);
1000 void mlx5_translate_port_name(const char *port_name_in,
1001 struct mlx5_switch_info *port_info_out);
1002 void mlx5_intr_callback_unregister(const struct rte_intr_handle *handle,
1003 rte_intr_callback_fn cb_fn, void *cb_arg);
1004 int mlx5_sysfs_bond_info(unsigned int pf_ifindex, unsigned int *ifindex,
1006 int mlx5_get_module_info(struct rte_eth_dev *dev,
1007 struct rte_eth_dev_module_info *modinfo);
1008 int mlx5_get_module_eeprom(struct rte_eth_dev *dev,
1009 struct rte_dev_eeprom_info *info);
1010 int mlx5_os_read_dev_stat(struct mlx5_priv *priv,
1011 const char *ctr_name, uint64_t *stat);
1012 int mlx5_os_read_dev_counters(struct rte_eth_dev *dev, uint64_t *stats);
1013 int mlx5_os_get_stats_n(struct rte_eth_dev *dev);
1014 void mlx5_os_stats_init(struct rte_eth_dev *dev);
1018 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
1019 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
1020 uint32_t index, uint32_t vmdq);
1021 int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr);
1022 int mlx5_set_mc_addr_list(struct rte_eth_dev *dev,
1023 struct rte_ether_addr *mc_addr_set,
1024 uint32_t nb_mc_addr);
1028 int mlx5_rss_hash_update(struct rte_eth_dev *dev,
1029 struct rte_eth_rss_conf *rss_conf);
1030 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev,
1031 struct rte_eth_rss_conf *rss_conf);
1032 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size);
1033 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev,
1034 struct rte_eth_rss_reta_entry64 *reta_conf,
1035 uint16_t reta_size);
1036 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev,
1037 struct rte_eth_rss_reta_entry64 *reta_conf,
1038 uint16_t reta_size);
1042 int mlx5_promiscuous_enable(struct rte_eth_dev *dev);
1043 int mlx5_promiscuous_disable(struct rte_eth_dev *dev);
1044 int mlx5_allmulticast_enable(struct rte_eth_dev *dev);
1045 int mlx5_allmulticast_disable(struct rte_eth_dev *dev);
1049 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
1050 int mlx5_stats_reset(struct rte_eth_dev *dev);
1051 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats,
1053 int mlx5_xstats_reset(struct rte_eth_dev *dev);
1054 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
1055 struct rte_eth_xstat_name *xstats_names,
1060 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
1061 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on);
1062 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask);
1064 /* mlx5_vlan_os.c */
1066 void mlx5_vlan_vmwa_exit(void *ctx);
1067 void mlx5_vlan_vmwa_release(struct rte_eth_dev *dev,
1068 struct mlx5_vf_vlan *vf_vlan);
1069 void mlx5_vlan_vmwa_acquire(struct rte_eth_dev *dev,
1070 struct mlx5_vf_vlan *vf_vlan);
1071 void *mlx5_vlan_vmwa_init(struct rte_eth_dev *dev, uint32_t ifindex);
1073 /* mlx5_trigger.c */
1075 int mlx5_dev_start(struct rte_eth_dev *dev);
1076 int mlx5_dev_stop(struct rte_eth_dev *dev);
1077 int mlx5_traffic_enable(struct rte_eth_dev *dev);
1078 void mlx5_traffic_disable(struct rte_eth_dev *dev);
1079 int mlx5_traffic_restart(struct rte_eth_dev *dev);
1080 int mlx5_hairpin_queue_peer_update(struct rte_eth_dev *dev, uint16_t peer_queue,
1081 struct rte_hairpin_peer_info *current_info,
1082 struct rte_hairpin_peer_info *peer_info,
1083 uint32_t direction);
1084 int mlx5_hairpin_queue_peer_bind(struct rte_eth_dev *dev, uint16_t cur_queue,
1085 struct rte_hairpin_peer_info *peer_info,
1086 uint32_t direction);
1087 int mlx5_hairpin_queue_peer_unbind(struct rte_eth_dev *dev, uint16_t cur_queue,
1088 uint32_t direction);
1089 int mlx5_hairpin_bind(struct rte_eth_dev *dev, uint16_t rx_port);
1090 int mlx5_hairpin_unbind(struct rte_eth_dev *dev, uint16_t rx_port);
1091 int mlx5_hairpin_get_peer_ports(struct rte_eth_dev *dev, uint16_t *peer_ports,
1092 size_t len, uint32_t direction);
1096 int mlx5_flow_discover_mreg_c(struct rte_eth_dev *eth_dev);
1097 bool mlx5_flow_ext_mreg_supported(struct rte_eth_dev *dev);
1098 void mlx5_flow_print(struct rte_flow *flow);
1099 int mlx5_flow_validate(struct rte_eth_dev *dev,
1100 const struct rte_flow_attr *attr,
1101 const struct rte_flow_item items[],
1102 const struct rte_flow_action actions[],
1103 struct rte_flow_error *error);
1104 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev,
1105 const struct rte_flow_attr *attr,
1106 const struct rte_flow_item items[],
1107 const struct rte_flow_action actions[],
1108 struct rte_flow_error *error);
1109 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow,
1110 struct rte_flow_error *error);
1111 void mlx5_flow_list_flush(struct rte_eth_dev *dev, uint32_t *list, bool active);
1112 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error);
1113 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow,
1114 const struct rte_flow_action *action, void *data,
1115 struct rte_flow_error *error);
1116 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable,
1117 struct rte_flow_error *error);
1118 int mlx5_dev_filter_ctrl(struct rte_eth_dev *dev,
1119 enum rte_filter_type filter_type,
1120 enum rte_filter_op filter_op,
1122 int mlx5_flow_start_default(struct rte_eth_dev *dev);
1123 void mlx5_flow_stop_default(struct rte_eth_dev *dev);
1124 int mlx5_flow_verify(struct rte_eth_dev *dev);
1125 int mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, uint32_t queue);
1126 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev,
1127 struct rte_flow_item_eth *eth_spec,
1128 struct rte_flow_item_eth *eth_mask,
1129 struct rte_flow_item_vlan *vlan_spec,
1130 struct rte_flow_item_vlan *vlan_mask);
1131 int mlx5_ctrl_flow(struct rte_eth_dev *dev,
1132 struct rte_flow_item_eth *eth_spec,
1133 struct rte_flow_item_eth *eth_mask);
1134 int mlx5_flow_lacp_miss(struct rte_eth_dev *dev);
1135 struct rte_flow *mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev);
1136 int mlx5_flow_create_drop_queue(struct rte_eth_dev *dev);
1137 void mlx5_flow_delete_drop_queue(struct rte_eth_dev *dev);
1138 void mlx5_flow_async_pool_query_handle(struct mlx5_dev_ctx_shared *sh,
1139 uint64_t async_id, int status);
1140 void mlx5_set_query_alarm(struct mlx5_dev_ctx_shared *sh);
1141 void mlx5_flow_query_alarm(void *arg);
1142 uint32_t mlx5_counter_alloc(struct rte_eth_dev *dev);
1143 void mlx5_counter_free(struct rte_eth_dev *dev, uint32_t cnt);
1144 int mlx5_counter_query(struct rte_eth_dev *dev, uint32_t cnt,
1145 bool clear, uint64_t *pkts, uint64_t *bytes);
1146 int mlx5_flow_dev_dump(struct rte_eth_dev *dev, FILE *file,
1147 struct rte_flow_error *error);
1148 void mlx5_flow_rxq_dynf_metadata_set(struct rte_eth_dev *dev);
1149 int mlx5_flow_get_aged_flows(struct rte_eth_dev *dev, void **contexts,
1150 uint32_t nb_contexts, struct rte_flow_error *error);
1154 int mlx5_mp_os_primary_handle(const struct rte_mp_msg *mp_msg,
1156 int mlx5_mp_os_secondary_handle(const struct rte_mp_msg *mp_msg,
1158 void mlx5_mp_os_req_start_rxtx(struct rte_eth_dev *dev);
1159 void mlx5_mp_os_req_stop_rxtx(struct rte_eth_dev *dev);
1160 int mlx5_mp_os_req_queue_control(struct rte_eth_dev *dev, uint16_t queue_id,
1161 enum mlx5_mp_req_type req_type);
1165 int mlx5_pmd_socket_init(void);
1167 /* mlx5_flow_meter.c */
1169 int mlx5_flow_meter_ops_get(struct rte_eth_dev *dev, void *arg);
1170 struct mlx5_flow_meter *mlx5_flow_meter_find(struct mlx5_priv *priv,
1172 struct mlx5_flow_meter *mlx5_flow_meter_attach
1173 (struct mlx5_priv *priv,
1175 const struct rte_flow_attr *attr,
1176 struct rte_flow_error *error);
1177 void mlx5_flow_meter_detach(struct mlx5_flow_meter *fm);
1180 struct rte_pci_driver;
1181 int mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *dev_attr);
1182 void mlx5_os_free_shared_dr(struct mlx5_priv *priv);
1183 int mlx5_os_open_device(const struct mlx5_dev_spawn_data *spawn,
1184 const struct mlx5_dev_config *config,
1185 struct mlx5_dev_ctx_shared *sh);
1186 int mlx5_os_get_pdn(void *pd, uint32_t *pdn);
1187 int mlx5_os_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1188 struct rte_pci_device *pci_dev);
1189 void mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh);
1190 void mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh);
1191 void mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb,
1192 mlx5_dereg_mr_t *dereg_mr_cb);
1193 void mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
1194 int mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
1196 int mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv, unsigned int iface_idx,
1197 struct rte_ether_addr *mac_addr,
1199 int mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable);
1200 int mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable);
1201 int mlx5_os_set_nonblock_channel_fd(int fd);
1202 void mlx5_os_mac_addr_flush(struct rte_eth_dev *dev);
1206 int mlx5_txpp_start(struct rte_eth_dev *dev);
1207 void mlx5_txpp_stop(struct rte_eth_dev *dev);
1208 int mlx5_txpp_read_clock(struct rte_eth_dev *dev, uint64_t *timestamp);
1209 int mlx5_txpp_xstats_get(struct rte_eth_dev *dev,
1210 struct rte_eth_xstat *stats,
1211 unsigned int n, unsigned int n_used);
1212 int mlx5_txpp_xstats_reset(struct rte_eth_dev *dev);
1213 int mlx5_txpp_xstats_get_names(struct rte_eth_dev *dev,
1214 struct rte_eth_xstat_name *xstats_names,
1215 unsigned int n, unsigned int n_used);
1216 void mlx5_txpp_interrupt_handler(void *cb_arg);
1220 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev);
1222 #endif /* RTE_PMD_MLX5_H_ */