1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_H_
7 #define RTE_PMD_MLX5_H_
14 #include <netinet/in.h>
15 #include <sys/queue.h>
18 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
20 #pragma GCC diagnostic ignored "-Wpedantic"
22 #include <infiniband/verbs.h>
24 #pragma GCC diagnostic error "-Wpedantic"
28 #include <rte_ether.h>
29 #include <rte_ethdev_driver.h>
30 #include <rte_rwlock.h>
31 #include <rte_interrupts.h>
32 #include <rte_errno.h>
35 #include "mlx5_utils.h"
37 #include "mlx5_autoconf.h"
38 #include "mlx5_defs.h"
39 #include "mlx5_glue.h"
42 PCI_VENDOR_ID_MELLANOX = 0x15b3,
46 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013,
47 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014,
48 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015,
49 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016,
50 PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017,
51 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018,
52 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019,
53 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a,
54 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF = 0xa2d2,
55 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF = 0xa2d3,
56 PCI_DEVICE_ID_MELLANOX_CONNECTX6 = 0x101b,
57 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF = 0x101c,
60 /* Request types for IPC. */
61 enum mlx5_mp_req_type {
62 MLX5_MP_REQ_VERBS_CMD_FD = 1,
63 MLX5_MP_REQ_CREATE_MR,
64 MLX5_MP_REQ_START_RXTX,
65 MLX5_MP_REQ_STOP_RXTX,
66 MLX5_MP_REQ_QUEUE_STATE_MODIFY,
69 struct mlx5_mp_arg_queue_state_modify {
70 uint8_t is_wq; /* Set if WQ. */
71 uint16_t queue_id; /* DPDK queue ID. */
72 enum ibv_wq_state state; /* WQ requested state. */
75 /* Pameters for IPC. */
76 struct mlx5_mp_param {
77 enum mlx5_mp_req_type type;
82 uintptr_t addr; /* MLX5_MP_REQ_CREATE_MR */
83 struct mlx5_mp_arg_queue_state_modify state_modify;
84 /* MLX5_MP_REQ_QUEUE_STATE_MODIFY */
88 /** Request timeout for IPC. */
89 #define MLX5_MP_REQ_TIMEOUT_SEC 5
91 /** Key string for IPC. */
92 #define MLX5_MP_NAME "net_mlx5_mp"
94 /* Recognized Infiniband device physical port name types. */
95 enum mlx5_phys_port_name_type {
96 MLX5_PHYS_PORT_NAME_TYPE_NOTSET = 0, /* Not set. */
97 MLX5_PHYS_PORT_NAME_TYPE_LEGACY, /* before kernel ver < 5.0 */
98 MLX5_PHYS_PORT_NAME_TYPE_UPLINK, /* p0, kernel ver >= 5.0 */
99 MLX5_PHYS_PORT_NAME_TYPE_PFVF, /* pf0vf0, kernel ver >= 5.0 */
100 MLX5_PHYS_PORT_NAME_TYPE_UNKNOWN, /* Unrecognized. */
103 /** Switch information returned by mlx5_nl_switch_info(). */
104 struct mlx5_switch_info {
105 uint32_t master:1; /**< Master device. */
106 uint32_t representor:1; /**< Representor device. */
107 enum mlx5_phys_port_name_type name_type; /** < Port name type. */
108 int32_t pf_num; /**< PF number (valid for pfxvfx format only). */
109 int32_t port_name; /**< Representor port name. */
110 uint64_t switch_id; /**< Switch identifier. */
113 LIST_HEAD(mlx5_dev_list, mlx5_ibv_shared);
115 /* Shared data between primary and secondary processes. */
116 struct mlx5_shared_data {
118 /* Global spinlock for primary and secondary processes. */
119 int init_done; /* Whether primary has done initialization. */
120 unsigned int secondary_cnt; /* Number of secondary processes init'd. */
121 struct mlx5_dev_list mem_event_cb_list;
122 rte_rwlock_t mem_event_rwlock;
125 /* Per-process data structure, not visible to other processes. */
126 struct mlx5_local_data {
127 int init_done; /* Whether a secondary has done initialization. */
130 extern struct mlx5_shared_data *mlx5_shared_data;
132 struct mlx5_counter_ctrl {
133 /* Name of the counter. */
134 char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE];
135 /* Name of the counter on the device table. */
136 char ctr_name[RTE_ETH_XSTATS_NAME_SIZE];
137 uint32_t ib:1; /**< Nonzero for IB counters. */
140 struct mlx5_xstats_ctrl {
141 /* Number of device stats. */
143 /* Number of device stats identified by PMD. */
144 uint16_t mlx5_stats_n;
145 /* Index in the device counters table. */
146 uint16_t dev_table_idx[MLX5_MAX_XSTATS];
147 uint64_t base[MLX5_MAX_XSTATS];
148 struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS];
151 struct mlx5_stats_ctrl {
152 /* Base for imissed counter. */
153 uint64_t imissed_base;
156 /* devX creation object */
157 struct mlx5_devx_obj {
158 struct mlx5dv_devx_obj *obj; /* The DV object. */
159 int id; /* The object ID. */
162 struct mlx5_devx_mkey_attr {
169 /* HCA supports this number of time periods for LRO. */
170 #define MLX5_LRO_NUM_SUPP_PERIODS 4
172 /* HCA attributes. */
173 struct mlx5_hca_attr {
174 uint32_t eswitch_manager:1;
175 uint32_t flow_counters_dump:1;
176 uint8_t flow_counter_bulk_alloc_bitmap;
177 uint32_t eth_net_offloads:1;
179 uint32_t wqe_vlan_insert:1;
180 uint32_t wqe_inline_mode:2;
181 uint32_t vport_inline_mode:3;
183 uint32_t tunnel_lro_gre:1;
184 uint32_t tunnel_lro_vxlan:1;
185 uint32_t lro_max_msg_sz_mode:2;
186 uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS];
190 TAILQ_HEAD(mlx5_flows, rte_flow);
192 /* Default PMD specific parameter value. */
193 #define MLX5_ARG_UNSET (-1)
195 #define MLX5_LRO_SUPPORTED(dev) \
196 (((struct mlx5_priv *)((dev)->data->dev_private))->config.lro.supported)
198 /* LRO configurations structure. */
199 struct mlx5_lro_config {
200 uint32_t supported:1; /* Whether LRO is supported. */
201 uint32_t timeout; /* User configuration. */
205 * Device configuration structure.
207 * Merged configuration from:
209 * - Device capabilities,
210 * - User device parameters disabled features.
212 struct mlx5_dev_config {
213 unsigned int hw_csum:1; /* Checksum offload is supported. */
214 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */
215 unsigned int hw_vlan_insert:1; /* VLAN insertion in WQE is supported. */
216 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */
217 unsigned int hw_padding:1; /* End alignment padding is supported. */
218 unsigned int vf:1; /* This is a VF. */
219 unsigned int tunnel_en:1;
220 /* Whether tunnel stateless offloads are supported. */
221 unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */
222 unsigned int cqe_comp:1; /* CQE compression is enabled. */
223 unsigned int cqe_pad:1; /* CQE padding is enabled. */
224 unsigned int tso:1; /* Whether TSO is supported. */
225 unsigned int rx_vec_en:1; /* Rx vector is enabled. */
226 unsigned int mr_ext_memseg_en:1;
227 /* Whether memseg should be extended for MR creation. */
228 unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */
229 unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */
230 unsigned int dv_esw_en:1; /* Enable E-Switch DV flow. */
231 unsigned int dv_flow_en:1; /* Enable DV flow. */
232 unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */
233 unsigned int devx:1; /* Whether devx interface is available or not. */
234 unsigned int dest_tir:1; /* Whether advanced DR API is available. */
236 unsigned int enabled:1; /* Whether MPRQ is enabled. */
237 unsigned int stride_num_n; /* Number of strides. */
238 unsigned int min_stride_size_n; /* Min size of a stride. */
239 unsigned int max_stride_size_n; /* Max size of a stride. */
240 unsigned int max_memcpy_len;
241 /* Maximum packet size to memcpy Rx packets. */
242 unsigned int min_rxqs_num;
243 /* Rx queue count threshold to enable MPRQ. */
244 } mprq; /* Configurations for Multi-Packet RQ. */
245 int mps; /* Multi-packet send supported mode. */
246 unsigned int flow_prio; /* Number of flow priorities. */
247 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */
248 unsigned int ind_table_max_size; /* Maximum indirection table size. */
249 unsigned int max_dump_files_num; /* Maximum dump files per queue. */
250 int txqs_inline; /* Queue number threshold for inlining. */
251 int txq_inline_min; /* Minimal amount of data bytes to inline. */
252 int txq_inline_max; /* Max packet size for inlining with SEND. */
253 int txq_inline_mpw; /* Max packet size for inlining with eMPW. */
254 struct mlx5_hca_attr hca_attr; /* HCA attributes. */
255 struct mlx5_lro_config lro; /* LRO configuration. */
258 struct mlx5_devx_wq_attr {
260 uint32_t wq_signature:1;
261 uint32_t end_padding_mode:2;
263 uint32_t hds_skip_first_sge:1;
264 uint32_t log2_hds_buf_size:3;
265 uint32_t page_offset:5;
268 uint32_t uar_page:24;
272 uint32_t log_wq_stride:4;
273 uint32_t log_wq_pg_sz:5;
274 uint32_t log_wq_sz:5;
275 uint32_t dbr_umem_valid:1;
276 uint32_t wq_umem_valid:1;
277 uint32_t log_hairpin_num_packets:5;
278 uint32_t log_hairpin_data_sz:5;
279 uint32_t single_wqe_log_num_of_strides:4;
280 uint32_t two_byte_shift_en:1;
281 uint32_t single_stride_log_num_of_bytes:3;
282 uint32_t dbr_umem_id;
284 uint64_t wq_umem_offset;
287 /* Create RQ attributes structure, used by create RQ operation. */
288 struct mlx5_devx_create_rq_attr {
290 uint32_t delay_drop_en:1;
291 uint32_t scatter_fcs:1;
293 uint32_t mem_rq_type:4;
295 uint32_t flush_in_error_en:1;
297 uint32_t user_index:24;
299 uint32_t counter_set_id:8;
301 struct mlx5_devx_wq_attr wq_attr;
304 /* Modify RQ attributes structure, used by modify RQ operation. */
305 struct mlx5_devx_modify_rq_attr {
307 uint32_t rq_state:4; /* Current RQ state. */
308 uint32_t state:4; /* Required RQ state. */
309 uint32_t scatter_fcs:1;
311 uint32_t counter_set_id:8;
312 uint32_t hairpin_peer_sq:24;
313 uint32_t hairpin_peer_vhca:16;
314 uint64_t modify_bitmask;
315 uint32_t lwm:16; /* Contained WQ lwm. */
318 struct mlx5_rx_hash_field_select {
319 uint32_t l3_prot_type:1;
320 uint32_t l4_prot_type:1;
321 uint32_t selected_fields:30;
324 /* TIR attributes structure, used by TIR operations. */
325 struct mlx5_devx_tir_attr {
326 uint32_t disp_type:4;
327 uint32_t lro_timeout_period_usecs:16;
328 uint32_t lro_enable_mask:4;
329 uint32_t lro_max_msg_sz:8;
330 uint32_t inline_rqn:24;
331 uint32_t rx_hash_symmetric:1;
332 uint32_t tunneled_offload_en:1;
333 uint32_t indirect_table:24;
334 uint32_t rx_hash_fn:4;
335 uint32_t self_lb_block:2;
336 uint32_t transport_domain:24;
337 uint32_t rx_hash_toeplitz_key[10];
338 struct mlx5_rx_hash_field_select rx_hash_field_selector_outer;
339 struct mlx5_rx_hash_field_select rx_hash_field_selector_inner;
342 /* RQT attributes structure, used by RQT operations. */
343 struct mlx5_devx_rqt_attr {
344 uint32_t rqt_max_size:16;
345 uint32_t rqt_actual_size:16;
350 * Type of object being allocated.
352 enum mlx5_verbs_alloc_type {
353 MLX5_VERBS_ALLOC_TYPE_NONE,
354 MLX5_VERBS_ALLOC_TYPE_TX_QUEUE,
355 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE,
358 /* VLAN netdev for VLAN workaround. */
359 struct mlx5_vlan_dev {
361 uint32_t ifindex; /**< Own interface index. */
364 /* Structure for VF VLAN workaround. */
365 struct mlx5_vf_vlan {
371 * Array of VLAN devices created on the base of VF
372 * used for workaround in virtual environments.
374 struct mlx5_vlan_vmwa_context {
378 struct rte_eth_dev *dev;
379 struct mlx5_vlan_dev vlan_dev[4096];
383 * Verbs allocator needs a context to know in the callback which kind of
384 * resources it is allocating.
386 struct mlx5_verbs_alloc_ctx {
387 enum mlx5_verbs_alloc_type type; /* Kind of object being allocated. */
388 const void *obj; /* Pointer to the DPDK object. */
391 LIST_HEAD(mlx5_mr_list, mlx5_mr);
393 /* Flow drop context necessary due to Verbs API. */
395 struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */
396 struct mlx5_rxq_obj *rxq; /* Rx queue object. */
399 #define MLX5_COUNTERS_PER_POOL 512
400 #define MLX5_MAX_PENDING_QUERIES 4
402 struct mlx5_flow_counter_pool;
404 struct flow_counter_stats {
409 /* Counters information. */
410 struct mlx5_flow_counter {
411 TAILQ_ENTRY(mlx5_flow_counter) next;
412 /**< Pointer to the next flow counter structure. */
413 uint32_t shared:1; /**< Share counter ID with other flow rules. */
415 /**< Whether the counter was allocated by batch command. */
416 uint32_t ref_cnt:30; /**< Reference counter. */
417 uint32_t id; /**< Counter ID. */
418 union { /**< Holds the counters for the rule. */
419 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42)
420 struct ibv_counter_set *cs;
421 #elif defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
422 struct ibv_counters *cs;
424 struct mlx5_devx_obj *dcs; /**< Counter Devx object. */
425 struct mlx5_flow_counter_pool *pool; /**< The counter pool. */
428 uint64_t hits; /**< Reset value of hits packets. */
429 int64_t query_gen; /**< Generation of the last release. */
431 uint64_t bytes; /**< Reset value of bytes. */
432 void *action; /**< Pointer to the dv action. */
435 TAILQ_HEAD(mlx5_counters, mlx5_flow_counter);
437 /* Counter pool structure - query is in pool resolution. */
438 struct mlx5_flow_counter_pool {
439 TAILQ_ENTRY(mlx5_flow_counter_pool) next;
440 struct mlx5_counters counters; /* Free counter list. */
442 struct mlx5_devx_obj *min_dcs;
443 rte_atomic64_t a64_dcs;
445 /* The devx object of the minimum counter ID. */
446 rte_atomic64_t query_gen;
447 uint32_t n_counters: 16; /* Number of devx allocated counters. */
448 rte_spinlock_t sl; /* The pool lock. */
449 struct mlx5_counter_stats_raw *raw;
450 struct mlx5_counter_stats_raw *raw_hw; /* The raw on HW working. */
451 struct mlx5_flow_counter counters_raw[]; /* The pool counters memory. */
454 struct mlx5_counter_stats_raw;
456 /* Memory management structure for group of counter statistics raws. */
457 struct mlx5_counter_stats_mem_mng {
458 LIST_ENTRY(mlx5_counter_stats_mem_mng) next;
459 struct mlx5_counter_stats_raw *raws;
460 struct mlx5_devx_obj *dm;
461 struct mlx5dv_devx_umem *umem;
464 /* Raw memory structure for the counter statistics values of a pool. */
465 struct mlx5_counter_stats_raw {
466 LIST_ENTRY(mlx5_counter_stats_raw) next;
468 struct mlx5_counter_stats_mem_mng *mem_mng;
469 volatile struct flow_counter_stats *data;
472 TAILQ_HEAD(mlx5_counter_pools, mlx5_flow_counter_pool);
474 /* Container structure for counter pools. */
475 struct mlx5_pools_container {
476 rte_atomic16_t n_valid; /* Number of valid pools. */
477 uint16_t n; /* Number of pools. */
478 struct mlx5_counter_pools pool_list; /* Counter pool list. */
479 struct mlx5_flow_counter_pool **pools; /* Counter pool array. */
480 struct mlx5_counter_stats_mem_mng *init_mem_mng;
481 /* Hold the memory management for the next allocated pools raws. */
484 /* Counter global management structure. */
485 struct mlx5_flow_counter_mng {
486 uint8_t mhi[2]; /* master \ host container index. */
487 struct mlx5_pools_container ccont[2 * 2];
488 /* 2 containers for single and for batch for double-buffer. */
489 struct mlx5_counters flow_counters; /* Legacy flow counter list. */
490 uint8_t pending_queries;
493 uint8_t query_thread_on;
494 LIST_HEAD(mem_mngs, mlx5_counter_stats_mem_mng) mem_mngs;
495 LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws;
498 /* Per port data of shared IB device. */
499 struct mlx5_ibv_shared_port {
502 * Interrupt handler port_id. Used by shared interrupt
503 * handler to find the corresponding rte_eth device
504 * by IB port index. If value is equal or greater
505 * RTE_MAX_ETHPORTS it means there is no subhandler
506 * installed for specified IB port index.
510 /* Table structure. */
511 struct mlx5_flow_tbl_resource {
512 void *obj; /**< Pointer to DR table object. */
513 rte_atomic32_t refcnt; /**< Reference counter. */
516 #define MLX5_MAX_TABLES UINT16_MAX
517 #define MLX5_MAX_TABLES_FDB UINT16_MAX
519 #define MLX5_DBR_PAGE_SIZE 4096 /* Must be >= 512. */
520 #define MLX5_DBR_SIZE 8
521 #define MLX5_DBR_PER_PAGE (MLX5_DBR_PAGE_SIZE / MLX5_DBR_SIZE)
522 #define MLX5_DBR_BITMAP_SIZE (MLX5_DBR_PER_PAGE / 64)
524 struct mlx5_devx_dbr_page {
525 /* Door-bell records, must be first member in structure. */
526 uint8_t dbrs[MLX5_DBR_PAGE_SIZE];
527 LIST_ENTRY(mlx5_devx_dbr_page) next; /* Pointer to the next element. */
528 struct mlx5dv_devx_umem *umem;
529 uint32_t dbr_count; /* Number of door-bell records in use. */
530 /* 1 bit marks matching door-bell is in use. */
531 uint64_t dbr_bitmap[MLX5_DBR_BITMAP_SIZE];
535 * Shared Infiniband device context for Master/Representors
536 * which belong to same IB device with multiple IB ports.
538 struct mlx5_ibv_shared {
539 LIST_ENTRY(mlx5_ibv_shared) next;
541 uint32_t devx:1; /* Opened with DV. */
542 uint32_t max_port; /* Maximal IB device port index. */
543 struct ibv_context *ctx; /* Verbs/DV context. */
544 struct ibv_pd *pd; /* Protection Domain. */
545 uint32_t pdn; /* Protection Domain number. */
546 uint32_t tdn; /* Transport Domain number. */
547 char ibdev_name[IBV_SYSFS_NAME_MAX]; /* IB device name. */
548 char ibdev_path[IBV_SYSFS_PATH_MAX]; /* IB device path for secondary */
549 struct ibv_device_attr_ex device_attr; /* Device properties. */
550 LIST_ENTRY(mlx5_ibv_shared) mem_event_cb;
551 /**< Called by memory event callback. */
553 uint32_t dev_gen; /* Generation number to flush local caches. */
554 rte_rwlock_t rwlock; /* MR Lock. */
555 struct mlx5_mr_btree cache; /* Global MR cache table. */
556 struct mlx5_mr_list mr_list; /* Registered MR list. */
557 struct mlx5_mr_list mr_free_list; /* Freed MR list. */
559 /* Shared DV/DR flow data section. */
560 pthread_mutex_t dv_mutex; /* DV context mutex. */
561 uint32_t dv_refcnt; /* DV/DR data reference counter. */
562 void *fdb_domain; /* FDB Direct Rules name space handle. */
563 struct mlx5_flow_tbl_resource fdb_tbl[MLX5_MAX_TABLES_FDB];
564 /* FDB Direct Rules tables. */
565 void *rx_domain; /* RX Direct Rules name space handle. */
566 struct mlx5_flow_tbl_resource rx_tbl[MLX5_MAX_TABLES];
567 /* RX Direct Rules tables. */
568 void *tx_domain; /* TX Direct Rules name space handle. */
569 struct mlx5_flow_tbl_resource tx_tbl[MLX5_MAX_TABLES];
570 /* TX Direct Rules tables. */
571 void *esw_drop_action; /* Pointer to DR E-Switch drop action. */
572 void *pop_vlan_action; /* Pointer to DR pop VLAN action. */
573 /* TX Direct Rules tables/ */
574 LIST_HEAD(matchers, mlx5_flow_dv_matcher) matchers;
575 LIST_HEAD(encap_decap, mlx5_flow_dv_encap_decap_resource) encaps_decaps;
576 LIST_HEAD(modify_cmd, mlx5_flow_dv_modify_hdr_resource) modify_cmds;
577 LIST_HEAD(tag, mlx5_flow_dv_tag_resource) tags;
578 LIST_HEAD(jump, mlx5_flow_dv_jump_tbl_resource) jump_tbl;
579 LIST_HEAD(port_id_action_list, mlx5_flow_dv_port_id_action_resource)
580 port_id_action_list; /* List of port ID actions. */
581 LIST_HEAD(push_vlan_action_list, mlx5_flow_dv_push_vlan_action_resource)
582 push_vlan_action_list; /* List of push VLAN actions. */
583 struct mlx5_flow_counter_mng cmng; /* Counters management structure. */
584 /* Shared interrupt handler section. */
585 pthread_mutex_t intr_mutex; /* Interrupt config mutex. */
586 uint32_t intr_cnt; /* Interrupt handler reference counter. */
587 struct rte_intr_handle intr_handle; /* Interrupt handler for device. */
588 struct rte_intr_handle intr_handle_devx; /* DEVX interrupt handler. */
589 struct mlx5dv_devx_cmd_comp *devx_comp; /* DEVX async comp obj. */
590 struct mlx5_ibv_shared_port port[]; /* per device port data array. */
593 /* Per-process private structure. */
594 struct mlx5_proc_priv {
596 /* Size of UAR register table. */
598 /* Table of UAR registers for each process. */
601 #define MLX5_PROC_PRIV(port_id) \
602 ((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private)
605 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */
606 struct mlx5_ibv_shared *sh; /* Shared IB device context. */
607 uint32_t ibv_port; /* IB device port number. */
608 struct rte_pci_device *pci_dev; /* Backend PCI device. */
609 struct rte_ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */
610 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES);
611 /* Bit-field of MAC addresses owned by the PMD. */
612 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */
613 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */
614 /* Device properties. */
615 uint16_t mtu; /* Configured MTU. */
616 unsigned int isolated:1; /* Whether isolated mode is enabled. */
617 unsigned int representor:1; /* Device is a port representor. */
618 unsigned int master:1; /* Device is a E-Switch master. */
619 unsigned int dr_shared:1; /* DV/DR data is shared. */
620 unsigned int counter_fallback:1; /* Use counter fallback management. */
621 uint16_t domain_id; /* Switch domain identifier. */
622 uint16_t vport_id; /* Associated VF vport index (if any). */
623 uint32_t vport_meta_tag; /* Used for vport index match ove VF LAG. */
624 uint32_t vport_meta_mask; /* Used for vport index field match mask. */
625 int32_t representor_id; /* Port representor identifier. */
626 int32_t pf_bond; /* >=0 means PF index in bonding configuration. */
627 unsigned int if_index; /* Associated kernel network device index. */
629 unsigned int rxqs_n; /* RX queues array size. */
630 unsigned int txqs_n; /* TX queues array size. */
631 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */
632 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */
633 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
634 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */
635 unsigned int (*reta_idx)[]; /* RETA index table. */
636 unsigned int reta_idx_n; /* RETA index size. */
637 struct mlx5_drop drop_queue; /* Flow drop queues. */
638 struct mlx5_flows flows; /* RTE Flow rules. */
639 struct mlx5_flows ctrl_flows; /* Control flow rules. */
640 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */
641 LIST_HEAD(rxqobj, mlx5_rxq_obj) rxqsobj; /* Verbs/DevX Rx queues. */
642 LIST_HEAD(hrxq, mlx5_hrxq) hrxqs; /* Verbs Hash Rx queues. */
643 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */
644 LIST_HEAD(txqibv, mlx5_txq_ibv) txqsibv; /* Verbs Tx queues. */
645 /* Indirection tables. */
646 LIST_HEAD(ind_tables, mlx5_ind_table_obj) ind_tbls;
647 /* Pointer to next element. */
648 rte_atomic32_t refcnt; /**< Reference counter. */
649 struct ibv_flow_action *verbs_action;
650 /**< Verbs modify header action object. */
651 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
652 uint8_t max_lro_msg_size;
653 /* Tags resources cache. */
654 uint32_t link_speed_capa; /* Link speed capabilities. */
655 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */
656 struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */
657 struct mlx5_dev_config config; /* Device configuration. */
658 struct mlx5_verbs_alloc_ctx verbs_alloc_ctx;
659 /* Context for Verbs allocator. */
660 int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */
661 int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */
662 uint32_t nl_sn; /* Netlink message sequence number. */
663 LIST_HEAD(dbrpage, mlx5_devx_dbr_page) dbrpgs; /* Door-bell pages. */
664 struct mlx5_vlan_vmwa_context *vmwa_context; /* VLAN WA context. */
666 rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */
667 rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX];
668 /* UAR same-page access control required in 32bit implementations. */
672 #define PORT_ID(priv) ((priv)->dev_data->port_id)
673 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)])
677 int mlx5_getenv_int(const char *);
678 int mlx5_proc_priv_init(struct rte_eth_dev *dev);
679 int64_t mlx5_get_dbr(struct rte_eth_dev *dev,
680 struct mlx5_devx_dbr_page **dbr_page);
681 int32_t mlx5_release_dbr(struct rte_eth_dev *dev, uint32_t umem_id,
683 int mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev,
684 struct rte_eth_udp_tunnel *udp_tunnel);
685 uint16_t mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev);
687 /* Macro to iterate over all valid ports for mlx5 driver. */
688 #define MLX5_ETH_FOREACH_DEV(port_id, pci_dev) \
689 for (port_id = mlx5_eth_find_next(0, pci_dev); \
690 port_id < RTE_MAX_ETHPORTS; \
691 port_id = mlx5_eth_find_next(port_id + 1, pci_dev))
695 int mlx5_get_ifname(const struct rte_eth_dev *dev, char (*ifname)[IF_NAMESIZE]);
696 int mlx5_get_master_ifname(const char *ibdev_path, char (*ifname)[IF_NAMESIZE]);
697 unsigned int mlx5_ifindex(const struct rte_eth_dev *dev);
698 int mlx5_ifreq(const struct rte_eth_dev *dev, int req, struct ifreq *ifr);
699 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu);
700 int mlx5_set_flags(struct rte_eth_dev *dev, unsigned int keep,
702 int mlx5_dev_configure(struct rte_eth_dev *dev);
703 int mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info);
704 int mlx5_read_clock(struct rte_eth_dev *dev, uint64_t *clock);
705 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size);
706 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev);
707 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete);
708 int mlx5_force_link_status_change(struct rte_eth_dev *dev, int status);
709 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
710 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev,
711 struct rte_eth_fc_conf *fc_conf);
712 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev,
713 struct rte_eth_fc_conf *fc_conf);
714 int mlx5_dev_to_pci_addr(const char *dev_path,
715 struct rte_pci_addr *pci_addr);
716 void mlx5_dev_link_status_handler(void *arg);
717 void mlx5_dev_interrupt_handler(void *arg);
718 void mlx5_dev_interrupt_handler_devx(void *arg);
719 void mlx5_dev_interrupt_handler_uninstall(struct rte_eth_dev *dev);
720 void mlx5_dev_interrupt_handler_install(struct rte_eth_dev *dev);
721 int mlx5_set_link_down(struct rte_eth_dev *dev);
722 int mlx5_set_link_up(struct rte_eth_dev *dev);
723 int mlx5_is_removed(struct rte_eth_dev *dev);
724 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev);
725 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev);
726 struct mlx5_priv *mlx5_port_to_eswitch_info(uint16_t port);
727 struct mlx5_priv *mlx5_dev_to_eswitch_info(struct rte_eth_dev *dev);
728 int mlx5_sysfs_switch_info(unsigned int ifindex,
729 struct mlx5_switch_info *info);
730 void mlx5_sysfs_check_switch_info(bool device_dir,
731 struct mlx5_switch_info *switch_info);
732 void mlx5_nl_check_switch_info(bool nun_vf_set,
733 struct mlx5_switch_info *switch_info);
734 void mlx5_translate_port_name(const char *port_name_in,
735 struct mlx5_switch_info *port_info_out);
736 void mlx5_intr_callback_unregister(const struct rte_intr_handle *handle,
737 rte_intr_callback_fn cb_fn, void *cb_arg);
738 int mlx5_get_module_info(struct rte_eth_dev *dev,
739 struct rte_eth_dev_module_info *modinfo);
740 int mlx5_get_module_eeprom(struct rte_eth_dev *dev,
741 struct rte_dev_eeprom_info *info);
745 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]);
746 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
747 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
748 uint32_t index, uint32_t vmdq);
749 int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr);
750 int mlx5_set_mc_addr_list(struct rte_eth_dev *dev,
751 struct rte_ether_addr *mc_addr_set,
752 uint32_t nb_mc_addr);
756 int mlx5_rss_hash_update(struct rte_eth_dev *dev,
757 struct rte_eth_rss_conf *rss_conf);
758 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev,
759 struct rte_eth_rss_conf *rss_conf);
760 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size);
761 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev,
762 struct rte_eth_rss_reta_entry64 *reta_conf,
764 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev,
765 struct rte_eth_rss_reta_entry64 *reta_conf,
770 int mlx5_promiscuous_enable(struct rte_eth_dev *dev);
771 int mlx5_promiscuous_disable(struct rte_eth_dev *dev);
772 int mlx5_allmulticast_enable(struct rte_eth_dev *dev);
773 int mlx5_allmulticast_disable(struct rte_eth_dev *dev);
777 void mlx5_stats_init(struct rte_eth_dev *dev);
778 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
779 int mlx5_stats_reset(struct rte_eth_dev *dev);
780 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats,
782 int mlx5_xstats_reset(struct rte_eth_dev *dev);
783 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
784 struct rte_eth_xstat_name *xstats_names,
789 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
790 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on);
791 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask);
795 int mlx5_dev_start(struct rte_eth_dev *dev);
796 void mlx5_dev_stop(struct rte_eth_dev *dev);
797 int mlx5_traffic_enable(struct rte_eth_dev *dev);
798 void mlx5_traffic_disable(struct rte_eth_dev *dev);
799 int mlx5_traffic_restart(struct rte_eth_dev *dev);
803 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
804 void mlx5_flow_print(struct rte_flow *flow);
805 int mlx5_flow_validate(struct rte_eth_dev *dev,
806 const struct rte_flow_attr *attr,
807 const struct rte_flow_item items[],
808 const struct rte_flow_action actions[],
809 struct rte_flow_error *error);
810 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev,
811 const struct rte_flow_attr *attr,
812 const struct rte_flow_item items[],
813 const struct rte_flow_action actions[],
814 struct rte_flow_error *error);
815 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow,
816 struct rte_flow_error *error);
817 void mlx5_flow_list_flush(struct rte_eth_dev *dev, struct mlx5_flows *list);
818 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error);
819 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow,
820 const struct rte_flow_action *action, void *data,
821 struct rte_flow_error *error);
822 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable,
823 struct rte_flow_error *error);
824 int mlx5_dev_filter_ctrl(struct rte_eth_dev *dev,
825 enum rte_filter_type filter_type,
826 enum rte_filter_op filter_op,
828 int mlx5_flow_start(struct rte_eth_dev *dev, struct mlx5_flows *list);
829 void mlx5_flow_stop(struct rte_eth_dev *dev, struct mlx5_flows *list);
830 int mlx5_flow_verify(struct rte_eth_dev *dev);
831 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev,
832 struct rte_flow_item_eth *eth_spec,
833 struct rte_flow_item_eth *eth_mask,
834 struct rte_flow_item_vlan *vlan_spec,
835 struct rte_flow_item_vlan *vlan_mask);
836 int mlx5_ctrl_flow(struct rte_eth_dev *dev,
837 struct rte_flow_item_eth *eth_spec,
838 struct rte_flow_item_eth *eth_mask);
839 struct rte_flow *mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev);
840 int mlx5_flow_create_drop_queue(struct rte_eth_dev *dev);
841 void mlx5_flow_delete_drop_queue(struct rte_eth_dev *dev);
842 void mlx5_flow_async_pool_query_handle(struct mlx5_ibv_shared *sh,
843 uint64_t async_id, int status);
844 void mlx5_set_query_alarm(struct mlx5_ibv_shared *sh);
845 void mlx5_flow_query_alarm(void *arg);
848 void mlx5_mp_req_start_rxtx(struct rte_eth_dev *dev);
849 void mlx5_mp_req_stop_rxtx(struct rte_eth_dev *dev);
850 int mlx5_mp_req_mr_create(struct rte_eth_dev *dev, uintptr_t addr);
851 int mlx5_mp_req_verbs_cmd_fd(struct rte_eth_dev *dev);
852 int mlx5_mp_req_queue_state_modify(struct rte_eth_dev *dev,
853 struct mlx5_mp_arg_queue_state_modify *sm);
854 int mlx5_mp_init_primary(void);
855 void mlx5_mp_uninit_primary(void);
856 int mlx5_mp_init_secondary(void);
857 void mlx5_mp_uninit_secondary(void);
861 int mlx5_nl_init(int protocol);
862 int mlx5_nl_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
864 int mlx5_nl_mac_addr_remove(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
866 void mlx5_nl_mac_addr_sync(struct rte_eth_dev *dev);
867 void mlx5_nl_mac_addr_flush(struct rte_eth_dev *dev);
868 int mlx5_nl_promisc(struct rte_eth_dev *dev, int enable);
869 int mlx5_nl_allmulti(struct rte_eth_dev *dev, int enable);
870 unsigned int mlx5_nl_portnum(int nl, const char *name);
871 unsigned int mlx5_nl_ifindex(int nl, const char *name, uint32_t pindex);
872 int mlx5_nl_switch_info(int nl, unsigned int ifindex,
873 struct mlx5_switch_info *info);
875 struct mlx5_vlan_vmwa_context *mlx5_vlan_vmwa_init(struct rte_eth_dev *dev,
877 void mlx5_vlan_vmwa_exit(struct mlx5_vlan_vmwa_context *ctx);
878 void mlx5_vlan_vmwa_release(struct rte_eth_dev *dev,
879 struct mlx5_vf_vlan *vf_vlan);
880 void mlx5_vlan_vmwa_acquire(struct rte_eth_dev *dev,
881 struct mlx5_vf_vlan *vf_vlan);
883 /* mlx5_devx_cmds.c */
885 struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(struct ibv_context *ctx,
887 int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj);
888 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
889 int clear, uint32_t n_counters,
890 uint64_t *pkts, uint64_t *bytes,
891 uint32_t mkey, void *addr,
892 struct mlx5dv_devx_cmd_comp *cmd_comp,
894 int mlx5_devx_cmd_query_hca_attr(struct ibv_context *ctx,
895 struct mlx5_hca_attr *attr);
896 struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(struct ibv_context *ctx,
897 struct mlx5_devx_mkey_attr *attr);
898 int mlx5_devx_get_out_command_status(void *out);
899 int mlx5_devx_cmd_qp_query_tis_td(struct ibv_qp *qp, uint32_t tis_num,
901 struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(struct ibv_context *ctx,
902 struct mlx5_devx_create_rq_attr *rq_attr,
904 int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
905 struct mlx5_devx_modify_rq_attr *rq_attr);
906 struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(struct ibv_context *ctx,
907 struct mlx5_devx_tir_attr *tir_attr);
908 struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(struct ibv_context *ctx,
909 struct mlx5_devx_rqt_attr *rqt_attr);
911 #endif /* RTE_PMD_MLX5_H_ */