4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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34 #ifndef RTE_PMD_MLX5_H_
35 #define RTE_PMD_MLX5_H_
41 #include <netinet/in.h>
44 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
46 #pragma GCC diagnostic ignored "-Wpedantic"
48 #include <infiniband/verbs.h>
50 #pragma GCC diagnostic error "-Wpedantic"
53 /* DPDK headers don't like -pedantic. */
55 #pragma GCC diagnostic ignored "-Wpedantic"
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_spinlock.h>
60 #include <rte_interrupts.h>
61 #include <rte_errno.h>
64 #pragma GCC diagnostic error "-Wpedantic"
67 #include "mlx5_utils.h"
68 #include "mlx5_rxtx.h"
69 #include "mlx5_autoconf.h"
70 #include "mlx5_defs.h"
72 #if !defined(HAVE_VERBS_IBV_EXP_CQ_COMPRESSED_CQE) || \
73 !defined(HAVE_VERBS_MLX5_ETH_VLAN_INLINE_HEADER_SIZE)
74 #error Mellanox OFED >= 3.3 is required, please refer to the documentation.
78 PCI_VENDOR_ID_MELLANOX = 0x15b3,
82 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013,
83 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014,
84 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015,
85 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016,
89 struct rte_eth_dev *dev; /* Ethernet device. */
90 struct ibv_context *ctx; /* Verbs context. */
91 struct ibv_device_attr device_attr; /* Device properties. */
92 struct ibv_pd *pd; /* Protection Domain. */
94 * MAC addresses array and configuration bit-field.
95 * An extra entry that cannot be modified by the DPDK is reserved
96 * for broadcast frames (destination MAC address ff:ff:ff:ff:ff:ff).
98 struct ether_addr mac[MLX5_MAX_MAC_ADDRESSES];
99 BITFIELD_DECLARE(mac_configured, uint32_t, MLX5_MAX_MAC_ADDRESSES);
100 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */
101 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */
102 /* Device properties. */
103 uint16_t mtu; /* Configured MTU. */
104 uint8_t port; /* Physical port number. */
105 unsigned int started:1; /* Device started, flows enabled. */
106 unsigned int promisc_req:1; /* Promiscuous mode requested. */
107 unsigned int allmulti_req:1; /* All multicast mode requested. */
108 unsigned int hw_csum:1; /* Checksum offload is supported. */
109 unsigned int hw_csum_l2tun:1; /* Same for L2 tunnels. */
110 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */
111 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */
112 unsigned int hw_padding:1; /* End alignment padding is supported. */
113 unsigned int sriov:1; /* This is a VF or PF with VF devices. */
114 unsigned int mps:1; /* Whether multi-packet send is supported. */
115 unsigned int cqe_comp:1; /* Whether CQE compression is enabled. */
116 unsigned int pending_alarm:1; /* An alarm is pending. */
117 unsigned int txq_inline; /* Maximum packet size for inlining. */
118 unsigned int txqs_inline; /* Queue number threshold for inlining. */
120 unsigned int rxqs_n; /* RX queues array size. */
121 unsigned int txqs_n; /* TX queues array size. */
122 struct rxq *(*rxqs)[]; /* RX queues. */
123 struct txq *(*txqs)[]; /* TX queues. */
124 /* Indirection tables referencing all RX WQs. */
125 struct ibv_exp_rwq_ind_table *(*ind_tables)[];
126 unsigned int ind_tables_n; /* Number of indirection tables. */
127 unsigned int ind_table_max_size; /* Maximum indirection table size. */
128 /* Hash RX QPs feeding the indirection table. */
129 struct hash_rxq (*hash_rxqs)[];
130 unsigned int hash_rxqs_n; /* Hash RX QPs array size. */
131 /* RSS configuration array indexed by hash RX queue type. */
132 struct rte_eth_rss_conf *(*rss_conf)[];
133 uint64_t rss_hf; /* RSS DPDK bit field of active RSS. */
134 struct rte_intr_handle intr_handle; /* Interrupt handler. */
135 unsigned int (*reta_idx)[]; /* RETA index table. */
136 unsigned int reta_idx_n; /* RETA index size. */
137 struct fdir_filter_list *fdir_filter_list; /* Flow director rules. */
138 struct fdir_queue *fdir_drop_queue; /* Flow director drop queue. */
139 LIST_HEAD(mlx5_flows, rte_flow) flows; /* RTE Flow rules. */
140 uint32_t link_speed_capa; /* Link speed capabilities. */
141 rte_spinlock_t lock; /* Lock for control functions. */
144 /* Local storage for secondary process data. */
145 struct mlx5_secondary_data {
146 struct rte_eth_dev_data data; /* Local device data. */
147 struct priv *primary_priv; /* Private structure from primary. */
148 struct rte_eth_dev_data *shared_dev_data; /* Shared device data. */
149 rte_spinlock_t lock; /* Port configuration lock. */
150 } mlx5_secondary_data[RTE_MAX_ETHPORTS];
153 * Lock private structure to protect it from concurrent access in the
157 * Pointer to private structure.
160 priv_lock(struct priv *priv)
162 rte_spinlock_lock(&priv->lock);
166 * Unlock private structure.
169 * Pointer to private structure.
172 priv_unlock(struct priv *priv)
174 rte_spinlock_unlock(&priv->lock);
179 int mlx5_getenv_int(const char *);
183 struct priv *mlx5_get_priv(struct rte_eth_dev *dev);
184 int mlx5_is_secondary(void);
185 int priv_get_ifname(const struct priv *, char (*)[IF_NAMESIZE]);
186 int priv_ifreq(const struct priv *, int req, struct ifreq *);
187 int priv_get_num_vfs(struct priv *, uint16_t *);
188 int priv_get_mtu(struct priv *, uint16_t *);
189 int priv_set_flags(struct priv *, unsigned int, unsigned int);
190 int mlx5_dev_configure(struct rte_eth_dev *);
191 void mlx5_dev_infos_get(struct rte_eth_dev *, struct rte_eth_dev_info *);
192 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev);
193 int mlx5_link_update_unlocked(struct rte_eth_dev *, int);
194 int mlx5_link_update(struct rte_eth_dev *, int);
195 int mlx5_dev_set_mtu(struct rte_eth_dev *, uint16_t);
196 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *, struct rte_eth_fc_conf *);
197 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *, struct rte_eth_fc_conf *);
198 int mlx5_ibv_device_to_pci_addr(const struct ibv_device *,
199 struct rte_pci_addr *);
200 void mlx5_dev_link_status_handler(void *);
201 void mlx5_dev_interrupt_handler(struct rte_intr_handle *, void *);
202 void priv_dev_interrupt_handler_uninstall(struct priv *, struct rte_eth_dev *);
203 void priv_dev_interrupt_handler_install(struct priv *, struct rte_eth_dev *);
204 int mlx5_set_link_down(struct rte_eth_dev *dev);
205 int mlx5_set_link_up(struct rte_eth_dev *dev);
206 struct priv *mlx5_secondary_data_setup(struct priv *priv);
207 void priv_select_tx_function(struct priv *);
208 void priv_select_rx_function(struct priv *);
212 int priv_get_mac(struct priv *, uint8_t (*)[ETHER_ADDR_LEN]);
213 void hash_rxq_mac_addrs_del(struct hash_rxq *);
214 void priv_mac_addrs_disable(struct priv *);
215 void mlx5_mac_addr_remove(struct rte_eth_dev *, uint32_t);
216 int hash_rxq_mac_addrs_add(struct hash_rxq *);
217 int priv_mac_addr_add(struct priv *, unsigned int,
218 const uint8_t (*)[ETHER_ADDR_LEN]);
219 int priv_mac_addrs_enable(struct priv *);
220 void mlx5_mac_addr_add(struct rte_eth_dev *, struct ether_addr *, uint32_t,
222 void mlx5_mac_addr_set(struct rte_eth_dev *, struct ether_addr *);
226 int rss_hash_rss_conf_new_key(struct priv *, const uint8_t *, unsigned int,
228 int mlx5_rss_hash_update(struct rte_eth_dev *, struct rte_eth_rss_conf *);
229 int mlx5_rss_hash_conf_get(struct rte_eth_dev *, struct rte_eth_rss_conf *);
230 int priv_rss_reta_index_resize(struct priv *, unsigned int);
231 int mlx5_dev_rss_reta_query(struct rte_eth_dev *,
232 struct rte_eth_rss_reta_entry64 *, uint16_t);
233 int mlx5_dev_rss_reta_update(struct rte_eth_dev *,
234 struct rte_eth_rss_reta_entry64 *, uint16_t);
238 int priv_special_flow_enable(struct priv *, enum hash_rxq_flow_type);
239 void priv_special_flow_disable(struct priv *, enum hash_rxq_flow_type);
240 int priv_special_flow_enable_all(struct priv *);
241 void priv_special_flow_disable_all(struct priv *);
242 void mlx5_promiscuous_enable(struct rte_eth_dev *);
243 void mlx5_promiscuous_disable(struct rte_eth_dev *);
244 void mlx5_allmulticast_enable(struct rte_eth_dev *);
245 void mlx5_allmulticast_disable(struct rte_eth_dev *);
249 void mlx5_stats_get(struct rte_eth_dev *, struct rte_eth_stats *);
250 void mlx5_stats_reset(struct rte_eth_dev *);
254 int mlx5_vlan_filter_set(struct rte_eth_dev *, uint16_t, int);
255 void mlx5_vlan_offload_set(struct rte_eth_dev *, int);
256 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *, uint16_t, int);
260 int mlx5_dev_start(struct rte_eth_dev *);
261 void mlx5_dev_stop(struct rte_eth_dev *);
265 void priv_fdir_queue_destroy(struct priv *, struct fdir_queue *);
266 int fdir_init_filters_list(struct priv *);
267 void priv_fdir_delete_filters_list(struct priv *);
268 void priv_fdir_disable(struct priv *);
269 void priv_fdir_enable(struct priv *);
270 int mlx5_dev_filter_ctrl(struct rte_eth_dev *, enum rte_filter_type,
271 enum rte_filter_op, void *);
275 int mlx5_flow_validate(struct rte_eth_dev *, const struct rte_flow_attr *,
276 const struct rte_flow_item [],
277 const struct rte_flow_action [],
278 struct rte_flow_error *);
279 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *,
280 const struct rte_flow_attr *,
281 const struct rte_flow_item [],
282 const struct rte_flow_action [],
283 struct rte_flow_error *);
284 int mlx5_flow_destroy(struct rte_eth_dev *, struct rte_flow *,
285 struct rte_flow_error *);
286 int mlx5_flow_flush(struct rte_eth_dev *, struct rte_flow_error *);
287 int priv_flow_start(struct priv *);
288 void priv_flow_stop(struct priv *);
290 #endif /* RTE_PMD_MLX5_H_ */