1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_H_
7 #define RTE_PMD_MLX5_H_
13 #include <netinet/in.h>
14 #include <sys/queue.h>
17 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
19 #pragma GCC diagnostic ignored "-Wpedantic"
21 #include <infiniband/verbs.h>
23 #pragma GCC diagnostic error "-Wpedantic"
27 #include <rte_ether.h>
28 #include <rte_ethdev_driver.h>
29 #include <rte_rwlock.h>
30 #include <rte_interrupts.h>
31 #include <rte_errno.h>
34 #include "mlx5_utils.h"
36 #include "mlx5_rxtx.h"
37 #include "mlx5_autoconf.h"
38 #include "mlx5_defs.h"
41 PCI_VENDOR_ID_MELLANOX = 0x15b3,
45 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013,
46 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014,
47 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015,
48 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016,
49 PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017,
50 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018,
51 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019,
52 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a,
55 LIST_HEAD(mlx5_dev_list, priv);
57 /* Shared memory between primary and secondary processes. */
58 struct mlx5_shared_data {
59 struct mlx5_dev_list mem_event_cb_list;
60 rte_rwlock_t mem_event_rwlock;
63 extern struct mlx5_shared_data *mlx5_shared_data;
65 struct mlx5_xstats_ctrl {
66 /* Number of device stats. */
68 /* Index in the device counters table. */
69 uint16_t dev_table_idx[MLX5_MAX_XSTATS];
70 uint64_t base[MLX5_MAX_XSTATS];
74 TAILQ_HEAD(mlx5_flows, rte_flow);
76 /* Default PMD specific parameter value. */
77 #define MLX5_ARG_UNSET (-1)
80 * Device configuration structure.
82 * Merged configuration from:
84 * - Device capabilities,
85 * - User device parameters disabled features.
87 struct mlx5_dev_config {
88 unsigned int hw_csum:1; /* Checksum offload is supported. */
89 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */
90 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */
91 unsigned int hw_padding:1; /* End alignment padding is supported. */
92 unsigned int vf:1; /* This is a VF. */
93 unsigned int mps:2; /* Multi-packet send supported mode. */
94 unsigned int tunnel_en:1;
95 /* Whether tunnel stateless offloads are supported. */
96 unsigned int flow_counter_en:1; /* Whether flow counter is supported. */
97 unsigned int cqe_comp:1; /* CQE compression is enabled. */
98 unsigned int tso:1; /* Whether TSO is supported. */
99 unsigned int tx_vec_en:1; /* Tx vector is enabled. */
100 unsigned int rx_vec_en:1; /* Rx vector is enabled. */
101 unsigned int mpw_hdr_dseg:1; /* Enable DSEGs in the title WQEBB. */
102 unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */
103 unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */
104 unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */
106 unsigned int enabled:1; /* Whether MPRQ is enabled. */
107 unsigned int stride_num_n; /* Number of strides. */
108 unsigned int min_stride_size_n; /* Min size of a stride. */
109 unsigned int max_stride_size_n; /* Max size of a stride. */
110 unsigned int max_memcpy_len;
111 /* Maximum packet size to memcpy Rx packets. */
112 unsigned int min_rxqs_num;
113 /* Rx queue count threshold to enable MPRQ. */
114 } mprq; /* Configurations for Multi-Packet RQ. */
115 unsigned int max_verbs_prio; /* Number of Verb flow priorities. */
116 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */
117 unsigned int ind_table_max_size; /* Maximum indirection table size. */
118 int txq_inline; /* Maximum packet size for inlining. */
119 int txqs_inline; /* Queue number threshold for inlining. */
120 int inline_max_packet_sz; /* Max packet size for inlining. */
124 * Type of objet being allocated.
126 enum mlx5_verbs_alloc_type {
127 MLX5_VERBS_ALLOC_TYPE_NONE,
128 MLX5_VERBS_ALLOC_TYPE_TX_QUEUE,
129 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE,
132 /* 8 Verbs priorities. */
133 #define MLX5_VERBS_FLOW_PRIO_8 8
136 * Verbs allocator needs a context to know in the callback which kind of
137 * resources it is allocating.
139 struct mlx5_verbs_alloc_ctx {
140 enum mlx5_verbs_alloc_type type; /* Kind of object being allocated. */
141 const void *obj; /* Pointer to the DPDK object. */
144 LIST_HEAD(mlx5_mr_list, mlx5_mr);
147 LIST_ENTRY(priv) mem_event_cb; /* Called by memory event callback. */
148 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */
149 struct ibv_context *ctx; /* Verbs context. */
150 struct ibv_device_attr_ex device_attr; /* Device properties. */
151 struct ibv_pd *pd; /* Protection Domain. */
152 char ibdev_path[IBV_SYSFS_PATH_MAX]; /* IB device path for secondary */
153 struct ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */
154 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES);
155 /* Bit-field of MAC addresses owned by the PMD. */
156 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */
157 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */
158 /* Device properties. */
159 uint16_t mtu; /* Configured MTU. */
160 uint8_t port; /* Physical port number. */
161 unsigned int isolated:1; /* Whether isolated mode is enabled. */
163 unsigned int rxqs_n; /* RX queues array size. */
164 unsigned int txqs_n; /* TX queues array size. */
165 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */
166 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */
167 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
168 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */
169 struct rte_intr_handle intr_handle; /* Interrupt handler. */
170 unsigned int (*reta_idx)[]; /* RETA index table. */
171 unsigned int reta_idx_n; /* RETA index size. */
172 struct mlx5_hrxq_drop *flow_drop_queue; /* Flow drop queue. */
173 struct mlx5_flows flows; /* RTE Flow rules. */
174 struct mlx5_flows ctrl_flows; /* Control flow rules. */
176 uint32_t dev_gen; /* Generation number to flush local caches. */
177 rte_rwlock_t rwlock; /* MR Lock. */
178 struct mlx5_mr_btree cache; /* Global MR cache table. */
179 struct mlx5_mr_list mr_list; /* Registered MR list. */
180 struct mlx5_mr_list mr_free_list; /* Freed MR list. */
182 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */
183 LIST_HEAD(rxqibv, mlx5_rxq_ibv) rxqsibv; /* Verbs Rx queues. */
184 LIST_HEAD(hrxq, mlx5_hrxq) hrxqs; /* Verbs Hash Rx queues. */
185 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */
186 LIST_HEAD(txqibv, mlx5_txq_ibv) txqsibv; /* Verbs Tx queues. */
187 /* Verbs Indirection tables. */
188 LIST_HEAD(ind_tables, mlx5_ind_table_ibv) ind_tbls;
189 uint32_t link_speed_capa; /* Link speed capabilities. */
190 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */
191 int primary_socket; /* Unix socket for primary process. */
192 void *uar_base; /* Reserved address space for UAR mapping */
193 struct rte_intr_handle intr_handle_socket; /* Interrupt handler. */
194 struct mlx5_dev_config config; /* Device configuration. */
195 struct mlx5_verbs_alloc_ctx verbs_alloc_ctx;
196 /* Context for Verbs allocator. */
197 int nl_socket; /* Netlink socket. */
198 uint32_t nl_sn; /* Netlink message sequence number. */
201 #define PORT_ID(priv) ((priv)->dev_data->port_id)
202 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)])
206 int mlx5_getenv_int(const char *);
210 int mlx5_get_ifname(const struct rte_eth_dev *dev, char (*ifname)[IF_NAMESIZE]);
211 int mlx5_ifindex(const struct rte_eth_dev *dev);
212 int mlx5_ifreq(const struct rte_eth_dev *dev, int req, struct ifreq *ifr);
213 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu);
214 int mlx5_set_flags(struct rte_eth_dev *dev, unsigned int keep,
216 int mlx5_dev_configure(struct rte_eth_dev *dev);
217 void mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info);
218 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev);
219 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete);
220 int mlx5_force_link_status_change(struct rte_eth_dev *dev, int status);
221 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
222 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev,
223 struct rte_eth_fc_conf *fc_conf);
224 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev,
225 struct rte_eth_fc_conf *fc_conf);
226 int mlx5_ibv_device_to_pci_addr(const struct ibv_device *device,
227 struct rte_pci_addr *pci_addr);
228 void mlx5_dev_link_status_handler(void *arg);
229 void mlx5_dev_interrupt_handler(void *arg);
230 void mlx5_dev_interrupt_handler_uninstall(struct rte_eth_dev *dev);
231 void mlx5_dev_interrupt_handler_install(struct rte_eth_dev *dev);
232 int mlx5_set_link_down(struct rte_eth_dev *dev);
233 int mlx5_set_link_up(struct rte_eth_dev *dev);
234 int mlx5_is_removed(struct rte_eth_dev *dev);
235 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev);
236 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev);
240 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[ETHER_ADDR_LEN]);
241 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
242 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac,
243 uint32_t index, uint32_t vmdq);
244 int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr);
245 int mlx5_set_mc_addr_list(struct rte_eth_dev *dev,
246 struct ether_addr *mc_addr_set, uint32_t nb_mc_addr);
250 int mlx5_rss_hash_update(struct rte_eth_dev *dev,
251 struct rte_eth_rss_conf *rss_conf);
252 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev,
253 struct rte_eth_rss_conf *rss_conf);
254 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size);
255 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev,
256 struct rte_eth_rss_reta_entry64 *reta_conf,
258 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev,
259 struct rte_eth_rss_reta_entry64 *reta_conf,
264 void mlx5_promiscuous_enable(struct rte_eth_dev *dev);
265 void mlx5_promiscuous_disable(struct rte_eth_dev *dev);
266 void mlx5_allmulticast_enable(struct rte_eth_dev *dev);
267 void mlx5_allmulticast_disable(struct rte_eth_dev *dev);
271 void mlx5_xstats_init(struct rte_eth_dev *dev);
272 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
273 void mlx5_stats_reset(struct rte_eth_dev *dev);
274 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats,
276 void mlx5_xstats_reset(struct rte_eth_dev *dev);
277 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
278 struct rte_eth_xstat_name *xstats_names,
283 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
284 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on);
285 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask);
289 int mlx5_dev_start(struct rte_eth_dev *dev);
290 void mlx5_dev_stop(struct rte_eth_dev *dev);
291 int mlx5_traffic_enable(struct rte_eth_dev *dev);
292 void mlx5_traffic_disable(struct rte_eth_dev *dev);
293 int mlx5_traffic_restart(struct rte_eth_dev *dev);
297 unsigned int mlx5_get_max_verbs_prio(struct rte_eth_dev *dev);
298 int mlx5_flow_validate(struct rte_eth_dev *dev,
299 const struct rte_flow_attr *attr,
300 const struct rte_flow_item items[],
301 const struct rte_flow_action actions[],
302 struct rte_flow_error *error);
303 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev,
304 const struct rte_flow_attr *attr,
305 const struct rte_flow_item items[],
306 const struct rte_flow_action actions[],
307 struct rte_flow_error *error);
308 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow,
309 struct rte_flow_error *error);
310 void mlx5_flow_list_flush(struct rte_eth_dev *dev, struct mlx5_flows *list);
311 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error);
312 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow,
313 const struct rte_flow_action *action, void *data,
314 struct rte_flow_error *error);
315 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable,
316 struct rte_flow_error *error);
317 int mlx5_dev_filter_ctrl(struct rte_eth_dev *dev,
318 enum rte_filter_type filter_type,
319 enum rte_filter_op filter_op,
321 int mlx5_flow_start(struct rte_eth_dev *dev, struct mlx5_flows *list);
322 void mlx5_flow_stop(struct rte_eth_dev *dev, struct mlx5_flows *list);
323 int mlx5_flow_verify(struct rte_eth_dev *dev);
324 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev,
325 struct rte_flow_item_eth *eth_spec,
326 struct rte_flow_item_eth *eth_mask,
327 struct rte_flow_item_vlan *vlan_spec,
328 struct rte_flow_item_vlan *vlan_mask);
329 int mlx5_ctrl_flow(struct rte_eth_dev *dev,
330 struct rte_flow_item_eth *eth_spec,
331 struct rte_flow_item_eth *eth_mask);
332 int mlx5_flow_create_drop_queue(struct rte_eth_dev *dev);
333 void mlx5_flow_delete_drop_queue(struct rte_eth_dev *dev);
337 int mlx5_socket_init(struct rte_eth_dev *priv);
338 void mlx5_socket_uninit(struct rte_eth_dev *priv);
339 void mlx5_socket_handle(struct rte_eth_dev *priv);
340 int mlx5_socket_connect(struct rte_eth_dev *priv);
344 int mlx5_nl_init(uint32_t nlgroups);
345 int mlx5_nl_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac,
347 int mlx5_nl_mac_addr_remove(struct rte_eth_dev *dev, struct ether_addr *mac,
349 void mlx5_nl_mac_addr_sync(struct rte_eth_dev *dev);
350 void mlx5_nl_mac_addr_flush(struct rte_eth_dev *dev);
351 int mlx5_nl_promisc(struct rte_eth_dev *dev, int enable);
352 int mlx5_nl_allmulti(struct rte_eth_dev *dev, int enable);
354 #endif /* RTE_PMD_MLX5_H_ */