1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_H_
7 #define RTE_PMD_MLX5_H_
13 #include <netinet/in.h>
14 #include <sys/queue.h>
17 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
19 #pragma GCC diagnostic ignored "-Wpedantic"
21 #include <infiniband/verbs.h>
23 #pragma GCC diagnostic error "-Wpedantic"
27 #include <rte_ether.h>
28 #include <rte_ethdev_driver.h>
29 #include <rte_rwlock.h>
30 #include <rte_interrupts.h>
31 #include <rte_errno.h>
34 #include "mlx5_utils.h"
36 #include "mlx5_rxtx.h"
37 #include "mlx5_autoconf.h"
38 #include "mlx5_defs.h"
41 PCI_VENDOR_ID_MELLANOX = 0x15b3,
45 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013,
46 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014,
47 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015,
48 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016,
49 PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017,
50 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018,
51 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019,
52 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a,
53 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF = 0xa2d2,
54 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF = 0xa2d3,
55 PCI_DEVICE_ID_MELLANOX_CONNECTX6 = 0x101b,
56 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF = 0x101c,
59 /* Request types for IPC. */
60 enum mlx5_mp_req_type {
61 MLX5_MP_REQ_VERBS_CMD_FD = 1,
62 MLX5_MP_REQ_CREATE_MR,
63 MLX5_MP_REQ_START_RXTX,
64 MLX5_MP_REQ_STOP_RXTX,
67 /* Pameters for IPC. */
68 struct mlx5_mp_param {
69 enum mlx5_mp_req_type type;
74 uintptr_t addr; /* MLX5_MP_REQ_CREATE_MR */
78 /** Request timeout for IPC. */
79 #define MLX5_MP_REQ_TIMEOUT_SEC 5
81 /** Key string for IPC. */
82 #define MLX5_MP_NAME "net_mlx5_mp"
84 /** Switch information returned by mlx5_nl_switch_info(). */
85 struct mlx5_switch_info {
86 uint32_t master:1; /**< Master device. */
87 uint32_t representor:1; /**< Representor device. */
88 uint32_t port_name_new:1; /**< Rep. port name is in new format. */
89 int32_t port_name; /**< Representor port name. */
90 uint64_t switch_id; /**< Switch identifier. */
93 LIST_HEAD(mlx5_dev_list, mlx5_priv);
95 /* Shared data between primary and secondary processes. */
96 struct mlx5_shared_data {
98 /* Global spinlock for primary and secondary processes. */
99 int init_done; /* Whether primary has done initialization. */
100 unsigned int secondary_cnt; /* Number of secondary processes init'd. */
102 /* Reserved UAR address space for TXQ UAR(hw doorbell) mapping. */
103 struct mlx5_dev_list mem_event_cb_list;
104 rte_rwlock_t mem_event_rwlock;
107 /* Per-process data structure, not visible to other processes. */
108 struct mlx5_local_data {
109 int init_done; /* Whether a secondary has done initialization. */
111 /* Reserved UAR address space for TXQ UAR(hw doorbell) mapping. */
114 extern struct mlx5_shared_data *mlx5_shared_data;
116 struct mlx5_counter_ctrl {
117 /* Name of the counter. */
118 char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE];
119 /* Name of the counter on the device table. */
120 char ctr_name[RTE_ETH_XSTATS_NAME_SIZE];
121 uint32_t ib:1; /**< Nonzero for IB counters. */
124 struct mlx5_xstats_ctrl {
125 /* Number of device stats. */
127 /* Number of device stats identified by PMD. */
128 uint16_t mlx5_stats_n;
129 /* Index in the device counters table. */
130 uint16_t dev_table_idx[MLX5_MAX_XSTATS];
131 uint64_t base[MLX5_MAX_XSTATS];
132 struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS];
135 struct mlx5_stats_ctrl {
136 /* Base for imissed counter. */
137 uint64_t imissed_base;
140 /* devx counter object */
141 struct mlx5_devx_counter_set {
142 struct mlx5dv_devx_obj *obj;
143 int id; /* Flow counter ID */
147 TAILQ_HEAD(mlx5_flows, rte_flow);
149 /* Default PMD specific parameter value. */
150 #define MLX5_ARG_UNSET (-1)
153 * Device configuration structure.
155 * Merged configuration from:
157 * - Device capabilities,
158 * - User device parameters disabled features.
160 struct mlx5_dev_config {
161 unsigned int hw_csum:1; /* Checksum offload is supported. */
162 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */
163 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */
164 unsigned int hw_padding:1; /* End alignment padding is supported. */
165 unsigned int vf:1; /* This is a VF. */
166 unsigned int tunnel_en:1;
167 /* Whether tunnel stateless offloads are supported. */
168 unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */
169 unsigned int cqe_comp:1; /* CQE compression is enabled. */
170 unsigned int cqe_pad:1; /* CQE padding is enabled. */
171 unsigned int tso:1; /* Whether TSO is supported. */
172 unsigned int tx_vec_en:1; /* Tx vector is enabled. */
173 unsigned int rx_vec_en:1; /* Rx vector is enabled. */
174 unsigned int mpw_hdr_dseg:1; /* Enable DSEGs in the title WQEBB. */
175 unsigned int mr_ext_memseg_en:1;
176 /* Whether memseg should be extended for MR creation. */
177 unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */
178 unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */
179 unsigned int dv_flow_en:1; /* Enable DV flow. */
180 unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */
181 unsigned int devx:1; /* Whether devx interface is available or not. */
183 unsigned int enabled:1; /* Whether MPRQ is enabled. */
184 unsigned int stride_num_n; /* Number of strides. */
185 unsigned int min_stride_size_n; /* Min size of a stride. */
186 unsigned int max_stride_size_n; /* Max size of a stride. */
187 unsigned int max_memcpy_len;
188 /* Maximum packet size to memcpy Rx packets. */
189 unsigned int min_rxqs_num;
190 /* Rx queue count threshold to enable MPRQ. */
191 } mprq; /* Configurations for Multi-Packet RQ. */
192 int mps; /* Multi-packet send supported mode. */
193 unsigned int flow_prio; /* Number of flow priorities. */
194 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */
195 unsigned int ind_table_max_size; /* Maximum indirection table size. */
196 int txq_inline; /* Maximum packet size for inlining. */
197 int txqs_inline; /* Queue number threshold for inlining. */
198 int txqs_vec; /* Queue number threshold for vectorized Tx. */
199 int inline_max_packet_sz; /* Max packet size for inlining. */
203 * Type of objet being allocated.
205 enum mlx5_verbs_alloc_type {
206 MLX5_VERBS_ALLOC_TYPE_NONE,
207 MLX5_VERBS_ALLOC_TYPE_TX_QUEUE,
208 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE,
212 * Verbs allocator needs a context to know in the callback which kind of
213 * resources it is allocating.
215 struct mlx5_verbs_alloc_ctx {
216 enum mlx5_verbs_alloc_type type; /* Kind of object being allocated. */
217 const void *obj; /* Pointer to the DPDK object. */
220 LIST_HEAD(mlx5_mr_list, mlx5_mr);
222 /* Flow drop context necessary due to Verbs API. */
224 struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */
225 struct mlx5_rxq_ibv *rxq; /* Verbs Rx queue. */
228 struct mlx5_flow_tcf_context;
230 /* Per port data of shared IB device. */
231 struct mlx5_ibv_shared_port {
234 * Interrupt handler port_id. Used by shared interrupt
235 * handler to find the corresponding rte_eth device
236 * by IB port index. If value is equal or greater
237 * RTE_MAX_ETHPORTS it means there is no subhandler
238 * installed for specified IB port index.
243 * Shared Infiniband device context for Master/Representors
244 * which belong to same IB device with multiple IB ports.
246 struct mlx5_ibv_shared {
247 LIST_ENTRY(mlx5_ibv_shared) next;
249 uint32_t devx:1; /* Opened with DV. */
250 uint32_t max_port; /* Maximal IB device port index. */
251 struct ibv_context *ctx; /* Verbs/DV context. */
252 struct ibv_pd *pd; /* Protection Domain. */
253 char ibdev_name[IBV_SYSFS_NAME_MAX]; /* IB device name. */
254 char ibdev_path[IBV_SYSFS_PATH_MAX]; /* IB device path for secondary */
255 struct ibv_device_attr_ex device_attr; /* Device properties. */
256 pthread_mutex_t intr_mutex; /* Interrupt config mutex. */
257 uint32_t intr_cnt; /* Interrupt handler reference counter. */
258 struct rte_intr_handle intr_handle; /* Interrupt handler for device. */
259 struct mlx5_ibv_shared_port port[]; /* per device port data array. */
262 /* Table structure. */
263 struct mlx5_flow_tbl_resource {
264 void *obj; /**< Pointer to DR table object. */
265 rte_atomic32_t refcnt; /**< Reference counter. */
268 #define MLX5_MAX_TABLES 1024
269 #define MLX5_GROUP_FACTOR 1
272 LIST_ENTRY(mlx5_priv) mem_event_cb;
273 /**< Called by memory event callback. */
274 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */
275 struct mlx5_ibv_shared *sh; /* Shared IB device context. */
276 uint32_t ibv_port; /* IB device port number. */
277 struct ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */
278 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES);
279 /* Bit-field of MAC addresses owned by the PMD. */
280 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */
281 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */
282 /* Device properties. */
283 uint16_t mtu; /* Configured MTU. */
284 unsigned int isolated:1; /* Whether isolated mode is enabled. */
285 unsigned int representor:1; /* Device is a port representor. */
286 unsigned int master:1; /* Device is a E-Switch master. */
287 uint16_t domain_id; /* Switch domain identifier. */
288 uint16_t vport_id; /* Associated VF vport index (if any). */
289 int32_t representor_id; /* Port representor identifier. */
291 unsigned int rxqs_n; /* RX queues array size. */
292 unsigned int txqs_n; /* TX queues array size. */
293 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */
294 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */
295 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
296 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */
297 unsigned int (*reta_idx)[]; /* RETA index table. */
298 unsigned int reta_idx_n; /* RETA index size. */
299 struct mlx5_drop drop_queue; /* Flow drop queues. */
300 struct mlx5_flows flows; /* RTE Flow rules. */
301 struct mlx5_flows ctrl_flows; /* Control flow rules. */
302 LIST_HEAD(counters, mlx5_flow_counter) flow_counters;
305 uint32_t dev_gen; /* Generation number to flush local caches. */
306 rte_rwlock_t rwlock; /* MR Lock. */
307 struct mlx5_mr_btree cache; /* Global MR cache table. */
308 struct mlx5_mr_list mr_list; /* Registered MR list. */
309 struct mlx5_mr_list mr_free_list; /* Freed MR list. */
311 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */
312 LIST_HEAD(rxqibv, mlx5_rxq_ibv) rxqsibv; /* Verbs Rx queues. */
313 LIST_HEAD(hrxq, mlx5_hrxq) hrxqs; /* Verbs Hash Rx queues. */
314 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */
315 LIST_HEAD(txqibv, mlx5_txq_ibv) txqsibv; /* Verbs Tx queues. */
316 /* Verbs Indirection tables. */
317 LIST_HEAD(ind_tables, mlx5_ind_table_ibv) ind_tbls;
318 LIST_HEAD(matchers, mlx5_flow_dv_matcher) matchers;
319 LIST_HEAD(encap_decap, mlx5_flow_dv_encap_decap_resource) encaps_decaps;
320 LIST_HEAD(modify_cmd, mlx5_flow_dv_modify_hdr_resource) modify_cmds;
321 LIST_HEAD(tag, mlx5_flow_dv_tag_resource) tags;
322 /* Tags resources cache. */
323 uint32_t link_speed_capa; /* Link speed capabilities. */
324 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */
325 struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */
326 struct mlx5_dev_config config; /* Device configuration. */
327 struct mlx5_verbs_alloc_ctx verbs_alloc_ctx;
328 /* Context for Verbs allocator. */
329 int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */
330 int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */
331 uint32_t nl_sn; /* Netlink message sequence number. */
333 rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */
334 rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX];
335 /* UAR same-page access control required in 32bit implementations. */
337 struct mlx5_flow_tcf_context *tcf_context; /* TC flower context. */
338 void *rx_ns; /* RX Direct Rules name space handle. */
339 struct mlx5_flow_tbl_resource rx_tbl[MLX5_MAX_TABLES];
340 /* RX Direct Rules tables. */
341 void *tx_ns; /* TX Direct Rules name space handle. */
342 struct mlx5_flow_tbl_resource tx_tbl[MLX5_MAX_TABLES];
343 /* TX Direct Rules tables/ */
346 #define PORT_ID(priv) ((priv)->dev_data->port_id)
347 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)])
351 int mlx5_getenv_int(const char *);
355 int mlx5_get_ifname(const struct rte_eth_dev *dev, char (*ifname)[IF_NAMESIZE]);
356 unsigned int mlx5_ifindex(const struct rte_eth_dev *dev);
357 int mlx5_ifreq(const struct rte_eth_dev *dev, int req, struct ifreq *ifr);
358 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu);
359 int mlx5_set_flags(struct rte_eth_dev *dev, unsigned int keep,
361 int mlx5_dev_configure(struct rte_eth_dev *dev);
362 void mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info);
363 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size);
364 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev);
365 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete);
366 int mlx5_force_link_status_change(struct rte_eth_dev *dev, int status);
367 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
368 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev,
369 struct rte_eth_fc_conf *fc_conf);
370 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev,
371 struct rte_eth_fc_conf *fc_conf);
372 int mlx5_ibv_device_to_pci_addr(const struct ibv_device *device,
373 struct rte_pci_addr *pci_addr);
374 void mlx5_dev_link_status_handler(void *arg);
375 void mlx5_dev_interrupt_handler(void *arg);
376 void mlx5_dev_interrupt_handler_uninstall(struct rte_eth_dev *dev);
377 void mlx5_dev_interrupt_handler_install(struct rte_eth_dev *dev);
378 int mlx5_set_link_down(struct rte_eth_dev *dev);
379 int mlx5_set_link_up(struct rte_eth_dev *dev);
380 int mlx5_is_removed(struct rte_eth_dev *dev);
381 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev);
382 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev);
383 unsigned int mlx5_dev_to_port_id(const struct rte_device *dev,
385 unsigned int port_list_n);
386 int mlx5_sysfs_switch_info(unsigned int ifindex,
387 struct mlx5_switch_info *info);
388 bool mlx5_translate_port_name(const char *port_name_in,
389 struct mlx5_switch_info *port_info_out);
393 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[ETHER_ADDR_LEN]);
394 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
395 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac,
396 uint32_t index, uint32_t vmdq);
397 int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr);
398 int mlx5_set_mc_addr_list(struct rte_eth_dev *dev,
399 struct ether_addr *mc_addr_set, uint32_t nb_mc_addr);
403 int mlx5_rss_hash_update(struct rte_eth_dev *dev,
404 struct rte_eth_rss_conf *rss_conf);
405 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev,
406 struct rte_eth_rss_conf *rss_conf);
407 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size);
408 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev,
409 struct rte_eth_rss_reta_entry64 *reta_conf,
411 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev,
412 struct rte_eth_rss_reta_entry64 *reta_conf,
417 void mlx5_promiscuous_enable(struct rte_eth_dev *dev);
418 void mlx5_promiscuous_disable(struct rte_eth_dev *dev);
419 void mlx5_allmulticast_enable(struct rte_eth_dev *dev);
420 void mlx5_allmulticast_disable(struct rte_eth_dev *dev);
424 void mlx5_stats_init(struct rte_eth_dev *dev);
425 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
426 void mlx5_stats_reset(struct rte_eth_dev *dev);
427 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats,
429 void mlx5_xstats_reset(struct rte_eth_dev *dev);
430 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
431 struct rte_eth_xstat_name *xstats_names,
436 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
437 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on);
438 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask);
442 int mlx5_dev_start(struct rte_eth_dev *dev);
443 void mlx5_dev_stop(struct rte_eth_dev *dev);
444 int mlx5_traffic_enable(struct rte_eth_dev *dev);
445 void mlx5_traffic_disable(struct rte_eth_dev *dev);
446 int mlx5_traffic_restart(struct rte_eth_dev *dev);
450 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
451 void mlx5_flow_print(struct rte_flow *flow);
452 int mlx5_flow_validate(struct rte_eth_dev *dev,
453 const struct rte_flow_attr *attr,
454 const struct rte_flow_item items[],
455 const struct rte_flow_action actions[],
456 struct rte_flow_error *error);
457 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev,
458 const struct rte_flow_attr *attr,
459 const struct rte_flow_item items[],
460 const struct rte_flow_action actions[],
461 struct rte_flow_error *error);
462 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow,
463 struct rte_flow_error *error);
464 void mlx5_flow_list_flush(struct rte_eth_dev *dev, struct mlx5_flows *list);
465 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error);
466 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow,
467 const struct rte_flow_action *action, void *data,
468 struct rte_flow_error *error);
469 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable,
470 struct rte_flow_error *error);
471 int mlx5_dev_filter_ctrl(struct rte_eth_dev *dev,
472 enum rte_filter_type filter_type,
473 enum rte_filter_op filter_op,
475 int mlx5_flow_start(struct rte_eth_dev *dev, struct mlx5_flows *list);
476 void mlx5_flow_stop(struct rte_eth_dev *dev, struct mlx5_flows *list);
477 int mlx5_flow_verify(struct rte_eth_dev *dev);
478 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev,
479 struct rte_flow_item_eth *eth_spec,
480 struct rte_flow_item_eth *eth_mask,
481 struct rte_flow_item_vlan *vlan_spec,
482 struct rte_flow_item_vlan *vlan_mask);
483 int mlx5_ctrl_flow(struct rte_eth_dev *dev,
484 struct rte_flow_item_eth *eth_spec,
485 struct rte_flow_item_eth *eth_mask);
486 int mlx5_flow_create_drop_queue(struct rte_eth_dev *dev);
487 void mlx5_flow_delete_drop_queue(struct rte_eth_dev *dev);
490 void mlx5_mp_req_start_rxtx(struct rte_eth_dev *dev);
491 void mlx5_mp_req_stop_rxtx(struct rte_eth_dev *dev);
492 int mlx5_mp_req_mr_create(struct rte_eth_dev *dev, uintptr_t addr);
493 int mlx5_mp_req_verbs_cmd_fd(struct rte_eth_dev *dev);
494 void mlx5_mp_init_primary(void);
495 void mlx5_mp_uninit_primary(void);
496 void mlx5_mp_init_secondary(void);
497 void mlx5_mp_uninit_secondary(void);
501 int mlx5_nl_init(int protocol);
502 int mlx5_nl_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac,
504 int mlx5_nl_mac_addr_remove(struct rte_eth_dev *dev, struct ether_addr *mac,
506 void mlx5_nl_mac_addr_sync(struct rte_eth_dev *dev);
507 void mlx5_nl_mac_addr_flush(struct rte_eth_dev *dev);
508 int mlx5_nl_promisc(struct rte_eth_dev *dev, int enable);
509 int mlx5_nl_allmulti(struct rte_eth_dev *dev, int enable);
510 unsigned int mlx5_nl_portnum(int nl, const char *name);
511 unsigned int mlx5_nl_ifindex(int nl, const char *name, uint32_t pindex);
512 int mlx5_nl_switch_info(int nl, unsigned int ifindex,
513 struct mlx5_switch_info *info);
515 /* mlx5_devx_cmds.c */
517 int mlx5_devx_cmd_flow_counter_alloc(struct ibv_context *ctx,
518 struct mlx5_devx_counter_set *dcx);
519 int mlx5_devx_cmd_flow_counter_free(struct mlx5dv_devx_obj *obj);
520 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_counter_set *dcx,
522 uint64_t *pkts, uint64_t *bytes);
523 #endif /* RTE_PMD_MLX5_H_ */