1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_H_
7 #define RTE_PMD_MLX5_H_
13 #include <sys/queue.h>
16 #include <rte_ether.h>
17 #include <ethdev_driver.h>
18 #include <rte_rwlock.h>
19 #include <rte_interrupts.h>
20 #include <rte_errno.h>
24 #include <mlx5_glue.h>
25 #include <mlx5_devx_cmds.h>
27 #include <mlx5_common_mp.h>
28 #include <mlx5_common_mr.h>
29 #include <mlx5_common_devx.h>
31 #include "mlx5_defs.h"
32 #include "mlx5_utils.h"
34 #include "mlx5_autoconf.h"
37 #define MLX5_SH(dev) (((struct mlx5_priv *)(dev)->data->dev_private)->sh)
39 enum mlx5_ipool_index {
40 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
41 MLX5_IPOOL_DECAP_ENCAP = 0, /* Pool for encap/decap resource. */
42 MLX5_IPOOL_PUSH_VLAN, /* Pool for push vlan resource. */
43 MLX5_IPOOL_TAG, /* Pool for tag resource. */
44 MLX5_IPOOL_PORT_ID, /* Pool for port id resource. */
45 MLX5_IPOOL_JUMP, /* Pool for jump resource. */
46 MLX5_IPOOL_SAMPLE, /* Pool for sample resource. */
47 MLX5_IPOOL_DEST_ARRAY, /* Pool for destination array resource. */
48 MLX5_IPOOL_TUNNEL_ID, /* Pool for tunnel offload context */
49 MLX5_IPOOL_TNL_TBL_ID, /* Pool for tunnel table ID. */
51 MLX5_IPOOL_MTR, /* Pool for meter resource. */
52 MLX5_IPOOL_MCP, /* Pool for metadata resource. */
53 MLX5_IPOOL_HRXQ, /* Pool for hrxq resource. */
54 MLX5_IPOOL_MLX5_FLOW, /* Pool for mlx5 flow handle. */
55 MLX5_IPOOL_RTE_FLOW, /* Pool for rte_flow. */
56 MLX5_IPOOL_RSS_EXPANTION_FLOW_ID, /* Pool for Queue/RSS flow ID. */
57 MLX5_IPOOL_RSS_SHARED_ACTIONS, /* Pool for RSS shared actions. */
58 MLX5_IPOOL_MTR_POLICY, /* Pool for meter policy resource. */
63 * There are three reclaim memory mode supported.
64 * 0(none) means no memory reclaim.
65 * 1(light) means only PMD level reclaim.
66 * 2(aggressive) means both PMD and rdma-core level reclaim.
68 enum mlx5_reclaim_mem_mode {
69 MLX5_RCM_NONE, /* Don't reclaim memory. */
70 MLX5_RCM_LIGHT, /* Reclaim PMD level. */
71 MLX5_RCM_AGGR, /* Reclaim PMD and rdma-core level. */
74 /* Hash and cache list callback context. */
75 struct mlx5_flow_cb_ctx {
76 struct rte_eth_dev *dev;
77 struct rte_flow_error *error;
81 /* Device attributes used in mlx5 PMD */
82 struct mlx5_dev_attr {
83 uint64_t device_cap_flags_ex;
93 uint32_t raw_packet_caps;
94 uint32_t max_rwq_indirection_table_size;
96 uint32_t tso_supported_qpts;
99 uint32_t sw_parsing_offloads;
100 uint32_t min_single_stride_log_num_of_bytes;
101 uint32_t max_single_stride_log_num_of_bytes;
102 uint32_t min_single_wqe_log_num_of_strides;
103 uint32_t max_single_wqe_log_num_of_strides;
104 uint32_t stride_supported_qpts;
105 uint32_t tunnel_offloads_caps;
109 /** Data associated with devices to spawn. */
110 struct mlx5_dev_spawn_data {
111 uint32_t ifindex; /**< Network interface index. */
112 uint32_t max_port; /**< Device maximal port index. */
113 uint32_t phys_port; /**< Device physical port index. */
114 int pf_bond; /**< bonding device PF index. < 0 - no bonding */
115 struct mlx5_switch_info info; /**< Switch information. */
116 void *phys_dev; /**< Associated physical device. */
117 struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */
118 struct rte_pci_device *pci_dev; /**< Backend PCI device. */
119 struct mlx5_bond_info *bond_info;
122 /** Data associated with socket messages. */
123 struct mlx5_flow_dump_req {
124 uint32_t port_id; /**< There are plans in DPDK to extend port_id. */
128 struct mlx5_flow_dump_ack {
129 int rc; /**< Return code. */
132 /** Key string for IPC. */
133 #define MLX5_MP_NAME "net_mlx5_mp"
136 LIST_HEAD(mlx5_dev_list, mlx5_dev_ctx_shared);
138 /* Shared data between primary and secondary processes. */
139 struct mlx5_shared_data {
141 /* Global spinlock for primary and secondary processes. */
142 int init_done; /* Whether primary has done initialization. */
143 unsigned int secondary_cnt; /* Number of secondary processes init'd. */
144 struct mlx5_dev_list mem_event_cb_list;
145 rte_rwlock_t mem_event_rwlock;
148 /* Per-process data structure, not visible to other processes. */
149 struct mlx5_local_data {
150 int init_done; /* Whether a secondary has done initialization. */
153 extern struct mlx5_shared_data *mlx5_shared_data;
155 /* Dev ops structs */
156 extern const struct eth_dev_ops mlx5_dev_ops;
157 extern const struct eth_dev_ops mlx5_dev_sec_ops;
158 extern const struct eth_dev_ops mlx5_dev_ops_isolate;
160 struct mlx5_counter_ctrl {
161 /* Name of the counter. */
162 char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE];
163 /* Name of the counter on the device table. */
164 char ctr_name[RTE_ETH_XSTATS_NAME_SIZE];
165 uint32_t dev:1; /**< Nonzero for dev counters. */
168 struct mlx5_xstats_ctrl {
169 /* Number of device stats. */
171 /* Number of device stats identified by PMD. */
172 uint16_t mlx5_stats_n;
173 /* Index in the device counters table. */
174 uint16_t dev_table_idx[MLX5_MAX_XSTATS];
175 uint64_t base[MLX5_MAX_XSTATS];
176 uint64_t xstats[MLX5_MAX_XSTATS];
177 uint64_t hw_stats[MLX5_MAX_XSTATS];
178 struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS];
181 struct mlx5_stats_ctrl {
182 /* Base for imissed counter. */
183 uint64_t imissed_base;
187 /* Default PMD specific parameter value. */
188 #define MLX5_ARG_UNSET (-1)
190 #define MLX5_LRO_SUPPORTED(dev) \
191 (((struct mlx5_priv *)((dev)->data->dev_private))->config.lro.supported)
193 /* Maximal size of coalesced segment for LRO is set in chunks of 256 Bytes. */
194 #define MLX5_LRO_SEG_CHUNK_SIZE 256u
196 /* Maximal size of aggregated LRO packet. */
197 #define MLX5_MAX_LRO_SIZE (UINT8_MAX * MLX5_LRO_SEG_CHUNK_SIZE)
199 /* Maximal number of segments to split. */
200 #define MLX5_MAX_RXQ_NSEG (1u << MLX5_MAX_LOG_RQ_SEGS)
202 /* LRO configurations structure. */
203 struct mlx5_lro_config {
204 uint32_t supported:1; /* Whether LRO is supported. */
205 uint32_t timeout; /* User configuration. */
209 * Device configuration structure.
211 * Merged configuration from:
213 * - Device capabilities,
214 * - User device parameters disabled features.
216 struct mlx5_dev_config {
217 unsigned int hw_csum:1; /* Checksum offload is supported. */
218 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */
219 unsigned int hw_vlan_insert:1; /* VLAN insertion in WQE is supported. */
220 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */
221 unsigned int hw_padding:1; /* End alignment padding is supported. */
222 unsigned int vf:1; /* This is a VF. */
223 unsigned int tunnel_en:1;
224 /* Whether tunnel stateless offloads are supported. */
225 unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */
226 unsigned int cqe_comp:1; /* CQE compression is enabled. */
227 unsigned int cqe_comp_fmt:3; /* CQE compression format. */
228 unsigned int tso:1; /* Whether TSO is supported. */
229 unsigned int rx_vec_en:1; /* Rx vector is enabled. */
230 unsigned int mr_ext_memseg_en:1;
231 /* Whether memseg should be extended for MR creation. */
232 unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */
233 unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */
234 unsigned int dv_esw_en:1; /* Enable E-Switch DV flow. */
235 unsigned int dv_flow_en:1; /* Enable DV flow. */
236 unsigned int dv_xmeta_en:2; /* Enable extensive flow metadata. */
237 unsigned int lacp_by_user:1;
238 /* Enable user to manage LACP traffic. */
239 unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */
240 unsigned int devx:1; /* Whether devx interface is available or not. */
241 unsigned int dest_tir:1; /* Whether advanced DR API is available. */
242 unsigned int reclaim_mode:2; /* Memory reclaim mode. */
243 unsigned int rt_timestamp:1; /* realtime timestamp format. */
244 unsigned int sys_mem_en:1; /* The default memory allocator. */
245 unsigned int decap_en:1; /* Whether decap will be used or not. */
246 unsigned int dv_miss_info:1; /* restore packet after partial hw miss */
247 unsigned int allow_duplicate_pattern:1;
248 /* Allow/Prevent the duplicate rules pattern. */
250 unsigned int enabled:1; /* Whether MPRQ is enabled. */
251 unsigned int stride_num_n; /* Number of strides. */
252 unsigned int stride_size_n; /* Size of a stride. */
253 unsigned int min_stride_size_n; /* Min size of a stride. */
254 unsigned int max_stride_size_n; /* Max size of a stride. */
255 unsigned int max_memcpy_len;
256 /* Maximum packet size to memcpy Rx packets. */
257 unsigned int min_rxqs_num;
258 /* Rx queue count threshold to enable MPRQ. */
259 } mprq; /* Configurations for Multi-Packet RQ. */
260 int mps; /* Multi-packet send supported mode. */
261 int dbnc; /* Skip doorbell register write barrier. */
262 unsigned int flow_prio; /* Number of flow priorities. */
263 enum modify_reg flow_mreg_c[MLX5_MREG_C_NUM];
264 /* Availibility of mreg_c's. */
265 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */
266 unsigned int ind_table_max_size; /* Maximum indirection table size. */
267 unsigned int max_dump_files_num; /* Maximum dump files per queue. */
268 unsigned int log_hp_size; /* Single hairpin queue data size in total. */
269 int txqs_inline; /* Queue number threshold for inlining. */
270 int txq_inline_min; /* Minimal amount of data bytes to inline. */
271 int txq_inline_max; /* Max packet size for inlining with SEND. */
272 int txq_inline_mpw; /* Max packet size for inlining with eMPW. */
273 int tx_pp; /* Timestamp scheduling granularity in nanoseconds. */
274 int tx_skew; /* Tx scheduling skew between WQE and data on wire. */
275 struct mlx5_hca_attr hca_attr; /* HCA attributes. */
276 struct mlx5_lro_config lro; /* LRO configuration. */
280 /* Structure for VF VLAN workaround. */
281 struct mlx5_vf_vlan {
286 /* Flow drop context necessary due to Verbs API. */
288 struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */
289 struct mlx5_rxq_obj *rxq; /* Rx queue object. */
292 /* Loopback dummy queue resources required due to Verbs API. */
294 struct ibv_qp *qp; /* QP object. */
295 void *ibv_cq; /* Completion queue. */
296 uint16_t refcnt; /* Reference count for representors. */
299 #define MLX5_COUNTERS_PER_POOL 512
300 #define MLX5_MAX_PENDING_QUERIES 4
301 #define MLX5_CNT_CONTAINER_RESIZE 64
302 #define MLX5_CNT_SHARED_OFFSET 0x80000000
303 #define IS_LEGACY_SHARED_CNT(cnt) (!!((cnt) & MLX5_CNT_SHARED_OFFSET))
304 #define IS_BATCH_CNT(cnt) (((cnt) & (MLX5_CNT_SHARED_OFFSET - 1)) >= \
305 MLX5_CNT_BATCH_OFFSET)
306 #define MLX5_CNT_SIZE (sizeof(struct mlx5_flow_counter))
307 #define MLX5_AGE_SIZE (sizeof(struct mlx5_age_param))
309 #define MLX5_CNT_LEN(pool) \
311 ((pool)->is_aged ? MLX5_AGE_SIZE : 0))
312 #define MLX5_POOL_GET_CNT(pool, index) \
313 ((struct mlx5_flow_counter *) \
314 ((uint8_t *)((pool) + 1) + (index) * (MLX5_CNT_LEN(pool))))
315 #define MLX5_CNT_ARRAY_IDX(pool, cnt) \
316 ((int)(((uint8_t *)(cnt) - (uint8_t *)((pool) + 1)) / \
319 * The pool index and offset of counter in the pool array makes up the
320 * counter index. In case the counter is from pool 0 and offset 0, it
321 * should plus 1 to avoid index 0, since 0 means invalid counter index
324 #define MLX5_MAKE_CNT_IDX(pi, offset) \
325 ((pi) * MLX5_COUNTERS_PER_POOL + (offset) + 1)
326 #define MLX5_CNT_TO_AGE(cnt) \
327 ((struct mlx5_age_param *)((cnt) + 1))
329 * The maximum single counter is 0x800000 as MLX5_CNT_BATCH_OFFSET
330 * defines. The pool size is 512, pool index should never reach
333 #define POOL_IDX_INVALID UINT16_MAX
337 AGE_FREE, /* Initialized state. */
338 AGE_CANDIDATE, /* Counter assigned to flows. */
339 AGE_TMOUT, /* Timeout, wait for rte_flow_get_aged_flows and destroy. */
342 enum mlx5_counter_type {
343 MLX5_COUNTER_TYPE_ORIGIN,
344 MLX5_COUNTER_TYPE_AGE,
345 MLX5_COUNTER_TYPE_MAX,
348 /* Counter age parameter. */
349 struct mlx5_age_param {
350 uint16_t state; /**< Age state (atomically accessed). */
351 uint16_t port_id; /**< Port id of the counter. */
352 uint32_t timeout:24; /**< Aging timeout in seconds. */
353 uint32_t sec_since_last_hit;
354 /**< Time in seconds since last hit (atomically accessed). */
355 void *context; /**< Flow counter age context. */
358 struct flow_counter_stats {
363 /* Shared counters information for counters. */
364 struct mlx5_flow_counter_shared {
366 uint32_t refcnt; /* Only for shared action management. */
367 uint32_t id; /* User counter ID for legacy sharing. */
371 /* Shared counter configuration. */
372 struct mlx5_shared_counter_conf {
373 struct rte_eth_dev *dev; /* The device shared counter belongs to. */
374 uint32_t id; /* The shared counter ID. */
377 struct mlx5_flow_counter_pool;
378 /* Generic counters information. */
379 struct mlx5_flow_counter {
382 * User-defined counter shared info is only used during
383 * counter active time. And aging counter sharing is not
384 * supported, so active shared counter will not be chained
385 * to the aging list. For shared counter, only when it is
386 * released, the TAILQ entry memory will be used, at that
387 * time, shared memory is not used anymore.
389 * Similarly to none-batch counter dcs, since it doesn't
390 * support aging, while counter is allocated, the entry
391 * memory is not used anymore. In this case, as bytes
392 * memory is used only when counter is allocated, and
393 * entry memory is used only when counter is free. The
394 * dcs pointer can be saved to these two different place
395 * at different stage. It will eliminate the individual
396 * counter extend struct.
398 TAILQ_ENTRY(mlx5_flow_counter) next;
399 /**< Pointer to the next flow counter structure. */
401 struct mlx5_flow_counter_shared shared_info;
402 /**< Shared counter information. */
403 void *dcs_when_active;
405 * For non-batch mode, the dcs will be saved
406 * here when the counter is free.
411 uint64_t hits; /**< Reset value of hits packets. */
412 struct mlx5_flow_counter_pool *pool; /**< Counter pool. */
415 uint64_t bytes; /**< Reset value of bytes. */
418 * For non-batch mode, the dcs will be saved here
419 * when the counter is free.
422 void *action; /**< Pointer to the dv action. */
425 TAILQ_HEAD(mlx5_counters, mlx5_flow_counter);
427 /* Generic counter pool structure - query is in pool resolution. */
428 struct mlx5_flow_counter_pool {
429 TAILQ_ENTRY(mlx5_flow_counter_pool) next;
430 struct mlx5_counters counters[2]; /* Free counter list. */
431 struct mlx5_devx_obj *min_dcs;
432 /* The devx object of the minimum counter ID. */
433 uint64_t time_of_last_age_check;
434 /* System time (from rte_rdtsc()) read in the last aging check. */
435 uint32_t index:30; /* Pool index in container. */
436 uint32_t is_aged:1; /* Pool with aging counter. */
437 volatile uint32_t query_gen:1; /* Query round. */
438 rte_spinlock_t sl; /* The pool lock. */
439 rte_spinlock_t csl; /* The pool counter free list lock. */
440 struct mlx5_counter_stats_raw *raw;
441 struct mlx5_counter_stats_raw *raw_hw;
442 /* The raw on HW working. */
445 /* Memory management structure for group of counter statistics raws. */
446 struct mlx5_counter_stats_mem_mng {
447 LIST_ENTRY(mlx5_counter_stats_mem_mng) next;
448 struct mlx5_counter_stats_raw *raws;
449 struct mlx5_devx_obj *dm;
453 /* Raw memory structure for the counter statistics values of a pool. */
454 struct mlx5_counter_stats_raw {
455 LIST_ENTRY(mlx5_counter_stats_raw) next;
456 struct mlx5_counter_stats_mem_mng *mem_mng;
457 volatile struct flow_counter_stats *data;
460 TAILQ_HEAD(mlx5_counter_pools, mlx5_flow_counter_pool);
462 /* Counter global management structure. */
463 struct mlx5_flow_counter_mng {
464 volatile uint16_t n_valid; /* Number of valid pools. */
465 uint16_t n; /* Number of pools. */
466 uint16_t last_pool_idx; /* Last used pool index */
467 int min_id; /* The minimum counter ID in the pools. */
468 int max_id; /* The maximum counter ID in the pools. */
469 rte_spinlock_t pool_update_sl; /* The pool update lock. */
470 rte_spinlock_t csl[MLX5_COUNTER_TYPE_MAX];
471 /* The counter free list lock. */
472 struct mlx5_counters counters[MLX5_COUNTER_TYPE_MAX];
473 /* Free counter list. */
474 struct mlx5_flow_counter_pool **pools; /* Counter pool array. */
475 struct mlx5_counter_stats_mem_mng *mem_mng;
476 /* Hold the memory management for the next allocated pools raws. */
477 struct mlx5_counters flow_counters; /* Legacy flow counter list. */
478 uint8_t pending_queries;
480 uint8_t query_thread_on;
481 bool relaxed_ordering_read;
482 bool relaxed_ordering_write;
483 bool counter_fallback; /* Use counter fallback management. */
484 LIST_HEAD(mem_mngs, mlx5_counter_stats_mem_mng) mem_mngs;
485 LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws;
488 /* ASO structures. */
489 #define MLX5_ASO_QUEUE_LOG_DESC 10
494 struct mlx5_devx_cq cq_obj;
498 struct mlx5_aso_sq_elem {
501 struct mlx5_aso_age_pool *pool;
504 struct mlx5_aso_mtr *mtr;
506 struct mlx5_aso_ct_action *ct;
515 struct mlx5_aso_cq cq;
516 struct mlx5_devx_sq sq_obj;
517 volatile uint64_t *uar_addr;
518 struct mlx5_pmd_mr mr;
523 struct mlx5_aso_sq_elem elts[1 << MLX5_ASO_QUEUE_LOG_DESC];
524 uint16_t next; /* Pool index of the next pool to query. */
527 struct mlx5_aso_age_action {
528 LIST_ENTRY(mlx5_aso_age_action) next;
531 /* Following fields relevant only when action is active. */
532 uint16_t offset; /* Offset of ASO Flow Hit flag in DevX object. */
533 struct mlx5_age_param age_params;
536 #define MLX5_ASO_AGE_ACTIONS_PER_POOL 512
538 struct mlx5_aso_age_pool {
539 struct mlx5_devx_obj *flow_hit_aso_obj;
540 uint16_t index; /* Pool index in pools array. */
541 uint64_t time_of_last_age_check; /* In seconds. */
542 struct mlx5_aso_age_action actions[MLX5_ASO_AGE_ACTIONS_PER_POOL];
545 LIST_HEAD(aso_age_list, mlx5_aso_age_action);
547 struct mlx5_aso_age_mng {
548 struct mlx5_aso_age_pool **pools;
549 uint16_t n; /* Total number of pools. */
550 uint16_t next; /* Number of pools in use, index of next free pool. */
551 rte_spinlock_t resize_sl; /* Lock for resize objects. */
552 rte_spinlock_t free_sl; /* Lock for free list access. */
553 struct aso_age_list free; /* Free age actions list - ready to use. */
554 struct mlx5_aso_sq aso_sq; /* ASO queue objects. */
557 /* Management structure for geneve tlv option */
558 struct mlx5_geneve_tlv_option_resource {
559 struct mlx5_devx_obj *obj; /* Pointer to the geneve tlv opt object. */
560 rte_be16_t option_class; /* geneve tlv opt class.*/
561 uint8_t option_type; /* geneve tlv opt type.*/
562 uint8_t length; /* geneve tlv opt length. */
563 uint32_t refcnt; /* geneve tlv object reference counter */
567 #define MLX5_AGE_EVENT_NEW 1
568 #define MLX5_AGE_TRIGGER 2
569 #define MLX5_AGE_SET(age_info, BIT) \
570 ((age_info)->flags |= (1 << (BIT)))
571 #define MLX5_AGE_UNSET(age_info, BIT) \
572 ((age_info)->flags &= ~(1 << (BIT)))
573 #define MLX5_AGE_GET(age_info, BIT) \
574 ((age_info)->flags & (1 << (BIT)))
575 #define GET_PORT_AGE_INFO(priv) \
576 (&((priv)->sh->port[(priv)->dev_port - 1].age_info))
577 /* Current time in seconds. */
578 #define MLX5_CURR_TIME_SEC (rte_rdtsc() / rte_get_tsc_hz())
580 /* Aging information for per port. */
581 struct mlx5_age_info {
582 uint8_t flags; /* Indicate if is new event or need to be triggered. */
583 struct mlx5_counters aged_counters; /* Aged counter list. */
584 struct aso_age_list aged_aso; /* Aged ASO actions list. */
585 rte_spinlock_t aged_sl; /* Aged flow list lock. */
588 /* Per port data of shared IB device. */
589 struct mlx5_dev_shared_port {
591 uint32_t devx_ih_port_id;
593 * Interrupt handler port_id. Used by shared interrupt
594 * handler to find the corresponding rte_eth device
595 * by IB port index. If value is equal or greater
596 * RTE_MAX_ETHPORTS it means there is no subhandler
597 * installed for specified IB port index.
599 struct mlx5_age_info age_info;
600 /* Aging information for per port. */
604 * Max number of actions per DV flow.
605 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED
606 * in rdma-core file providers/mlx5/verbs.c.
608 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8
610 /*ASO flow meter structures*/
611 /* Modify this value if enum rte_mtr_color changes. */
612 #define RTE_MTR_DROPPED RTE_COLORS
613 /* Yellow is not supported. */
614 #define MLX5_MTR_RTE_COLORS (RTE_COLOR_GREEN + 1)
615 /* table_id 22 bits in mlx5_flow_tbl_key so limit policy number. */
616 #define MLX5_MAX_SUB_POLICY_TBL_NUM 0x3FFFFF
617 #define MLX5_INVALID_POLICY_ID UINT32_MAX
618 /* Suffix table_id on MLX5_FLOW_TABLE_LEVEL_METER. */
619 #define MLX5_MTR_TABLE_ID_SUFFIX 1
620 /* Drop table_id on MLX5_FLOW_TABLE_LEVEL_METER. */
621 #define MLX5_MTR_TABLE_ID_DROP 2
623 enum mlx5_meter_domain {
624 MLX5_MTR_DOMAIN_INGRESS,
625 MLX5_MTR_DOMAIN_EGRESS,
626 MLX5_MTR_DOMAIN_TRANSFER,
629 #define MLX5_MTR_DOMAIN_INGRESS_BIT (1 << MLX5_MTR_DOMAIN_INGRESS)
630 #define MLX5_MTR_DOMAIN_EGRESS_BIT (1 << MLX5_MTR_DOMAIN_EGRESS)
631 #define MLX5_MTR_DOMAIN_TRANSFER_BIT (1 << MLX5_MTR_DOMAIN_TRANSFER)
632 #define MLX5_MTR_ALL_DOMAIN_BIT (MLX5_MTR_DOMAIN_INGRESS_BIT | \
633 MLX5_MTR_DOMAIN_EGRESS_BIT | \
634 MLX5_MTR_DOMAIN_TRANSFER_BIT)
636 /* The color tag rule structure. */
637 struct mlx5_sub_policy_color_rule {
639 /* The color rule. */
640 struct mlx5_flow_dv_matcher *matcher;
641 /* The color matcher. */
642 TAILQ_ENTRY(mlx5_sub_policy_color_rule) next_port;
643 /**< Pointer to the next color rule structure. */
645 /* On which src port this rule applied. */
648 TAILQ_HEAD(mlx5_sub_policy_color_rules, mlx5_sub_policy_color_rule);
651 * Meter sub-policy structure.
652 * Each RSS TIR in meter policy need its own sub-policy resource.
654 struct mlx5_flow_meter_sub_policy {
655 uint32_t main_policy_id:1;
656 /* Main policy id is same as this sub_policy id. */
658 /* Index to sub_policy ipool entity. */
660 /* Point to struct mlx5_flow_meter_policy. */
661 struct mlx5_flow_tbl_resource *tbl_rsc;
662 /* The sub-policy table resource. */
663 uint32_t rix_hrxq[MLX5_MTR_RTE_COLORS];
664 /* Index to TIR resource. */
665 struct mlx5_flow_tbl_resource *jump_tbl[MLX5_MTR_RTE_COLORS];
666 /* Meter jump/drop table. */
667 struct mlx5_sub_policy_color_rules color_rules[RTE_COLORS];
668 /* List for the color rules. */
671 struct mlx5_meter_policy_acts {
673 /* Number of actions. */
674 void *dv_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS];
678 struct mlx5_meter_policy_action_container {
680 /* Index to the mark action. */
681 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
682 /* Pointer to modify header resource in cache. */
684 /* Fate action type. */
686 struct rte_flow_action *rss;
687 /* Rss action configuration. */
688 uint32_t rix_port_id_action;
689 /* Index to port ID action resource. */
690 void *dr_jump_action[MLX5_MTR_DOMAIN_MAX];
691 /* Jump/drop action per color. */
693 /* Queue action configuration. */
695 uint32_t next_mtr_id;
696 /* The next meter id. */
697 void *next_sub_policy;
698 /* Next meter's sub-policy. */
703 /* Flow meter policy parameter structure. */
704 struct mlx5_flow_meter_policy {
705 struct rte_eth_dev *dev;
706 /* The port dev on which policy is created. */
708 /* Is RSS policy table. */
710 /* Rule applies to ingress domain. */
712 /* Rule applies to egress domain. */
714 /* Rule applies to transfer domain. */
716 /* Is queue action in policy table. */
717 uint32_t is_hierarchy:1;
718 /* Is meter action in policy table. */
722 struct mlx5_meter_policy_action_container act_cnt[MLX5_MTR_RTE_COLORS];
723 /* Policy actions container. */
724 void *dr_drop_action[MLX5_MTR_DOMAIN_MAX];
725 /* drop action for red color. */
726 uint16_t sub_policy_num;
727 /* Count sub policy tables, 3 bits per domain. */
728 struct mlx5_flow_meter_sub_policy **sub_policys[MLX5_MTR_DOMAIN_MAX];
729 /* Sub policy table array must be the end of struct. */
732 /* The maximum sub policy is relate to struct mlx5_rss_hash_fields[]. */
733 #define MLX5_MTR_RSS_MAX_SUB_POLICY 7
734 #define MLX5_MTR_SUB_POLICY_NUM_SHIFT 3
735 #define MLX5_MTR_SUB_POLICY_NUM_MASK 0x7
736 #define MLX5_MTRS_DEFAULT_RULE_PRIORITY 0xFFFF
737 #define MLX5_MTR_CHAIN_MAX_NUM 8
739 /* Flow meter default policy parameter structure.
740 * Policy index 0 is reserved by default policy table.
741 * Action per color as below:
742 * green - do nothing, yellow - do nothing, red - drop
744 struct mlx5_flow_meter_def_policy {
745 struct mlx5_flow_meter_sub_policy sub_policy;
746 /* Policy rules jump to other tables. */
747 void *dr_jump_action[RTE_COLORS];
748 /* Jump action per color. */
751 /* Meter parameter structure. */
752 struct mlx5_flow_meter_info {
756 /* Policy id, the first sub_policy idx. */
757 struct mlx5_flow_meter_profile *profile;
758 /**< Meter profile parameters. */
759 rte_spinlock_t sl; /**< Meter action spinlock. */
760 /** Set of stats counters to be enabled.
761 * @see enum rte_mtr_stats_type
763 uint32_t bytes_dropped:1;
764 /** Set bytes dropped stats to be enabled. */
765 uint32_t pkts_dropped:1;
766 /** Set packets dropped stats to be enabled. */
767 uint32_t active_state:1;
768 /**< Meter hw active state. */
770 /**< Meter shared or not. */
771 uint32_t is_enable:1;
772 /**< Meter disable/enable state. */
774 /**< Rule applies to egress traffic. */
777 * Instead of simply matching the properties of traffic as it would
778 * appear on a given DPDK port ID, enabling this attribute transfers
779 * a flow rule to the lowest possible level of any device endpoints
780 * found in the pattern.
782 * When supported, this effectively enables an application to
783 * re-route traffic not necessarily intended for it (e.g. coming
784 * from or addressed to different physical ports, VFs or
785 * applications) at the device level.
787 * It complements the behavior of some pattern items such as
788 * RTE_FLOW_ITEM_TYPE_PHY_PORT and is meaningless without them.
790 * When transferring flow rules, ingress and egress attributes keep
791 * their original meaning, as if processing traffic emitted or
792 * received by the application.
795 uint32_t def_policy:1;
796 /* Meter points to default policy. */
797 void *drop_rule[MLX5_MTR_DOMAIN_MAX];
798 /* Meter drop rule in drop table. */
800 /**< Color counter for drop. */
803 struct mlx5_indexed_pool *flow_ipool;
804 /**< Index pool for flow id. */
806 /**< Flow meter action. */
809 /* PPS(packets per second) map to BPS(Bytes per second).
810 * HW treat packet as 128bytes in PPS mode
812 #define MLX5_MTRS_PPS_MAP_BPS_SHIFT 7
814 /* RFC2697 parameter structure. */
815 struct mlx5_flow_meter_srtcm_rfc2697_prm {
818 * bit 24-28: cbs_exponent, bit 16-23 cbs_mantissa,
819 * bit 8-12: cir_exponent, bit 0-7 cir_mantissa.
823 * bit 24-28: ebs_exponent, bit 16-23 ebs_mantissa,
824 * bit 8-12: eir_exponent, bit 0-7 eir_mantissa.
828 /* Flow meter profile structure. */
829 struct mlx5_flow_meter_profile {
830 TAILQ_ENTRY(mlx5_flow_meter_profile) next;
831 /**< Pointer to the next flow meter structure. */
832 uint32_t id; /**< Profile id. */
833 struct rte_mtr_meter_profile profile; /**< Profile detail. */
835 struct mlx5_flow_meter_srtcm_rfc2697_prm srtcm_prm;
836 /**< srtcm_rfc2697 struct. */
838 uint32_t ref_cnt; /**< Use count. */
841 /* 2 meters in each ASO cache line */
842 #define MLX5_MTRS_CONTAINER_RESIZE 64
844 * The pool index and offset of meter in the pool array makes up the
845 * meter index. In case the meter is from pool 0 and offset 0, it
846 * should plus 1 to avoid index 0, since 0 means invalid meter index
849 #define MLX5_MAKE_MTR_IDX(pi, offset) \
850 ((pi) * MLX5_ASO_MTRS_PER_POOL + (offset) + 1)
852 /*aso flow meter state*/
853 enum mlx5_aso_mtr_state {
854 ASO_METER_FREE, /* In free list. */
855 ASO_METER_WAIT, /* ACCESS_ASO WQE in progress. */
856 ASO_METER_READY, /* CQE received. */
859 /* Generic aso_flow_meter information. */
860 struct mlx5_aso_mtr {
861 LIST_ENTRY(mlx5_aso_mtr) next;
862 struct mlx5_flow_meter_info fm;
863 /**< Pointer to the next aso flow meter structure. */
864 uint8_t state; /**< ASO flow meter state. */
868 /* Generic aso_flow_meter pool structure. */
869 struct mlx5_aso_mtr_pool {
870 struct mlx5_aso_mtr mtrs[MLX5_ASO_MTRS_PER_POOL];
871 /*Must be the first in pool*/
872 struct mlx5_devx_obj *devx_obj;
873 /* The devx object of the minimum aso flow meter ID. */
874 uint32_t index; /* Pool index in management structure. */
877 LIST_HEAD(aso_meter_list, mlx5_aso_mtr);
878 /* Pools management structure for ASO flow meter pools. */
879 struct mlx5_aso_mtr_pools_mng {
880 volatile uint16_t n_valid; /* Number of valid pools. */
881 uint16_t n; /* Number of pools. */
882 rte_spinlock_t mtrsl; /* The ASO flow meter free list lock. */
883 struct aso_meter_list meters; /* Free ASO flow meter list. */
884 struct mlx5_aso_sq sq; /*SQ using by ASO flow meter. */
885 struct mlx5_aso_mtr_pool **pools; /* ASO flow meter pool array. */
888 /* Meter management structure for global flow meter resource. */
889 struct mlx5_flow_mtr_mng {
890 struct mlx5_aso_mtr_pools_mng pools_mng;
891 /* Pools management structure for ASO flow meter pools. */
892 struct mlx5_flow_meter_def_policy *def_policy[MLX5_MTR_DOMAIN_MAX];
893 /* Default policy table. */
894 uint32_t def_policy_id;
895 /* Default policy id. */
896 uint32_t def_policy_ref_cnt;
897 /** def_policy meter use count. */
898 struct mlx5_flow_tbl_resource *drop_tbl[MLX5_MTR_DOMAIN_MAX];
899 /* Meter drop table. */
900 struct mlx5_flow_dv_matcher *
901 drop_matcher[MLX5_MTR_DOMAIN_MAX][MLX5_REG_BITS];
902 /* Matcher meter in drop table. */
903 struct mlx5_flow_dv_matcher *def_matcher[MLX5_MTR_DOMAIN_MAX];
904 /* Default matcher in drop table. */
905 void *def_rule[MLX5_MTR_DOMAIN_MAX];
906 /* Default rule in drop table. */
907 uint8_t max_mtr_bits;
908 /* Indicate how many bits are used by meter id at the most. */
909 uint8_t max_mtr_flow_bits;
910 /* Indicate how many bits are used by meter flow id at the most. */
913 /* Table key of the hash organization. */
914 union mlx5_flow_tbl_key {
916 /* Table ID should be at the lowest address. */
917 uint32_t level; /**< Level of the table. */
918 uint32_t id:22; /**< ID of the table. */
919 uint32_t dummy:1; /**< Dummy table for DV API. */
920 uint32_t is_fdb:1; /**< 1 - FDB, 0 - NIC TX/RX. */
921 uint32_t is_egress:1; /**< 1 - egress, 0 - ingress. */
922 uint32_t reserved:7; /**< must be zero for comparison. */
924 uint64_t v64; /**< full 64bits value of key */
927 /* Table structure. */
928 struct mlx5_flow_tbl_resource {
929 void *obj; /**< Pointer to DR table object. */
930 uint32_t refcnt; /**< Reference counter. */
933 #define MLX5_MAX_TABLES UINT16_MAX
934 #define MLX5_HAIRPIN_TX_TABLE (UINT16_MAX - 1)
935 /* Reserve the last two tables for metadata register copy. */
936 #define MLX5_FLOW_MREG_ACT_TABLE_GROUP (MLX5_MAX_TABLES - 1)
937 #define MLX5_FLOW_MREG_CP_TABLE_GROUP (MLX5_MAX_TABLES - 2)
938 /* Tables for metering splits should be added here. */
939 #define MLX5_FLOW_TABLE_LEVEL_METER (MLX5_MAX_TABLES - 3)
940 #define MLX5_FLOW_TABLE_LEVEL_POLICY (MLX5_MAX_TABLES - 4)
941 #define MLX5_MAX_TABLES_EXTERNAL MLX5_FLOW_TABLE_LEVEL_POLICY
942 #define MLX5_MAX_TABLES_FDB UINT16_MAX
943 #define MLX5_FLOW_TABLE_FACTOR 10
945 /* ID generation structure. */
946 struct mlx5_flow_id_pool {
947 uint32_t *free_arr; /**< Pointer to the a array of free values. */
949 /**< The next index that can be used without any free elements. */
950 uint32_t *curr; /**< Pointer to the index to pop. */
951 uint32_t *last; /**< Pointer to the last element in the empty arrray. */
952 uint32_t max_id; /**< Maximum id can be allocated from the pool. */
955 /* Tx pacing queue structure - for Clock and Rearm queues. */
956 struct mlx5_txpp_wq {
957 /* Completion Queue related data.*/
958 struct mlx5_devx_cq cq_obj;
961 /* Send Queue related data.*/
962 struct mlx5_devx_sq sq_obj;
963 uint16_t sq_size; /* Number of WQEs in the queue. */
964 uint16_t sq_ci; /* Next WQE to execute. */
967 /* Tx packet pacing internal timestamp. */
968 struct mlx5_txpp_ts {
973 /* Tx packet pacing structure. */
974 struct mlx5_dev_txpp {
975 pthread_mutex_t mutex; /* Pacing create/destroy mutex. */
976 uint32_t refcnt; /* Pacing reference counter. */
977 uint32_t freq; /* Timestamp frequency, Hz. */
978 uint32_t tick; /* Completion tick duration in nanoseconds. */
979 uint32_t test; /* Packet pacing test mode. */
980 int32_t skew; /* Scheduling skew. */
981 struct rte_intr_handle intr_handle; /* Periodic interrupt. */
982 void *echan; /* Event Channel. */
983 struct mlx5_txpp_wq clock_queue; /* Clock Queue. */
984 struct mlx5_txpp_wq rearm_queue; /* Clock Queue. */
985 void *pp; /* Packet pacing context. */
986 uint16_t pp_id; /* Packet pacing context index. */
987 uint16_t ts_n; /* Number of captured timestamps. */
988 uint16_t ts_p; /* Pointer to statisticks timestamp. */
989 struct mlx5_txpp_ts *tsa; /* Timestamps sliding window stats. */
990 struct mlx5_txpp_ts ts; /* Cached completion id/timestamp. */
991 uint32_t sync_lost:1; /* ci/timestamp synchronization lost. */
992 /* Statistics counters. */
993 uint64_t err_miss_int; /* Missed service interrupt. */
994 uint64_t err_rearm_queue; /* Rearm Queue errors. */
995 uint64_t err_clock_queue; /* Clock Queue errors. */
996 uint64_t err_ts_past; /* Timestamp in the past. */
997 uint64_t err_ts_future; /* Timestamp in the distant future. */
1000 /* Supported flex parser profile ID. */
1001 enum mlx5_flex_parser_profile_id {
1002 MLX5_FLEX_PARSER_ECPRI_0 = 0,
1003 MLX5_FLEX_PARSER_MAX = 8,
1006 /* Sample ID information of flex parser structure. */
1007 struct mlx5_flex_parser_profiles {
1008 uint32_t num; /* Actual number of samples. */
1009 uint32_t ids[8]; /* Sample IDs for this profile. */
1010 uint8_t offset[8]; /* Bytes offset of each parser. */
1011 void *obj; /* Flex parser node object. */
1014 /* Max member ports per bonding device. */
1015 #define MLX5_BOND_MAX_PORTS 2
1017 /* Bonding device information. */
1018 struct mlx5_bond_info {
1019 int n_port; /* Number of bond member ports. */
1021 char ifname[MLX5_NAMESIZE + 1];
1023 char ifname[MLX5_NAMESIZE + 1];
1025 struct rte_pci_addr pci_addr;
1026 } ports[MLX5_BOND_MAX_PORTS];
1029 /* Number of connection tracking objects per pool: must be a power of 2. */
1030 #define MLX5_ASO_CT_ACTIONS_PER_POOL 64
1032 /* Generate incremental and unique CT index from pool and offset. */
1033 #define MLX5_MAKE_CT_IDX(pool, offset) \
1034 ((pool) * MLX5_ASO_CT_ACTIONS_PER_POOL + (offset) + 1)
1036 /* ASO Conntrack state. */
1037 enum mlx5_aso_ct_state {
1038 ASO_CONNTRACK_FREE, /* Inactive, in the free list. */
1039 ASO_CONNTRACK_WAIT, /* WQE sent in the SQ. */
1040 ASO_CONNTRACK_READY, /* CQE received w/o error. */
1041 ASO_CONNTRACK_QUERY, /* WQE for query sent. */
1042 ASO_CONNTRACK_MAX, /* Guard. */
1045 /* Generic ASO connection tracking structure. */
1046 struct mlx5_aso_ct_action {
1047 LIST_ENTRY(mlx5_aso_ct_action) next; /* Pointer to the next ASO CT. */
1048 void *dr_action_orig; /* General action object for original dir. */
1049 void *dr_action_rply; /* General action object for reply dir. */
1050 uint32_t refcnt; /* Action used count in device flows. */
1051 uint16_t offset; /* Offset of ASO CT in DevX objects bulk. */
1052 uint16_t peer; /* The only peer port index could also use this CT. */
1053 enum mlx5_aso_ct_state state; /* ASO CT state. */
1054 bool is_original; /* The direction of the DR action to be used. */
1057 /* CT action object state update. */
1058 #define MLX5_ASO_CT_UPDATE_STATE(c, s) \
1059 __atomic_store_n(&((c)->state), (s), __ATOMIC_RELAXED)
1061 /* ASO connection tracking software pool definition. */
1062 struct mlx5_aso_ct_pool {
1063 uint16_t index; /* Pool index in pools array. */
1064 struct mlx5_devx_obj *devx_obj;
1065 /* The first devx object in the bulk, used for freeing (not yet). */
1066 struct mlx5_aso_ct_action actions[MLX5_ASO_CT_ACTIONS_PER_POOL];
1067 /* CT action structures bulk. */
1070 LIST_HEAD(aso_ct_list, mlx5_aso_ct_action);
1072 /* Pools management structure for ASO connection tracking pools. */
1073 struct mlx5_aso_ct_pools_mng {
1074 struct mlx5_aso_ct_pool **pools;
1075 uint16_t n; /* Total number of pools. */
1076 uint16_t next; /* Number of pools in use, index of next free pool. */
1077 rte_spinlock_t ct_sl; /* The ASO CT free list lock. */
1078 rte_rwlock_t resize_rwl; /* The ASO CT pool resize lock. */
1079 struct aso_ct_list free_cts; /* Free ASO CT objects list. */
1080 struct mlx5_aso_sq aso_sq; /* ASO queue objects. */
1084 * Shared Infiniband device context for Master/Representors
1085 * which belong to same IB device with multiple IB ports.
1087 struct mlx5_dev_ctx_shared {
1088 LIST_ENTRY(mlx5_dev_ctx_shared) next;
1090 uint32_t devx:1; /* Opened with DV. */
1091 uint32_t flow_hit_aso_en:1; /* Flow Hit ASO is supported. */
1092 uint32_t rq_ts_format:2; /* RQ timestamp formats supported. */
1093 uint32_t sq_ts_format:2; /* SQ timestamp formats supported. */
1094 uint32_t qp_ts_format:2; /* QP timestamp formats supported. */
1095 uint32_t meter_aso_en:1; /* Flow Meter ASO is supported. */
1096 uint32_t ct_aso_en:1; /* Connection Tracking ASO is supported. */
1097 uint32_t max_port; /* Maximal IB device port index. */
1098 struct mlx5_bond_info bond; /* Bonding information. */
1099 void *ctx; /* Verbs/DV/DevX context. */
1100 void *pd; /* Protection Domain. */
1101 uint32_t pdn; /* Protection Domain number. */
1102 uint32_t tdn; /* Transport Domain number. */
1103 char ibdev_name[MLX5_FS_NAME_MAX]; /* SYSFS dev name. */
1104 char ibdev_path[MLX5_FS_PATH_MAX]; /* SYSFS dev path for secondary */
1105 struct mlx5_dev_attr device_attr; /* Device properties. */
1106 int numa_node; /* Numa node of backing physical device. */
1107 LIST_ENTRY(mlx5_dev_ctx_shared) mem_event_cb;
1108 /**< Called by memory event callback. */
1109 struct mlx5_mr_share_cache share_cache;
1110 /* Packet pacing related structure. */
1111 struct mlx5_dev_txpp txpp;
1112 /* Shared DV/DR flow data section. */
1113 uint32_t dv_meta_mask; /* flow META metadata supported mask. */
1114 uint32_t dv_mark_mask; /* flow MARK metadata supported mask. */
1115 uint32_t dv_regc0_mask; /* available bits of metatada reg_c[0]. */
1116 void *fdb_domain; /* FDB Direct Rules name space handle. */
1117 void *rx_domain; /* RX Direct Rules name space handle. */
1118 void *tx_domain; /* TX Direct Rules name space handle. */
1120 rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */
1121 rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX];
1122 /* UAR same-page access control required in 32bit implementations. */
1124 struct mlx5_hlist *flow_tbls;
1125 struct mlx5_flow_tunnel_hub *tunnel_hub;
1126 /* Direct Rules tables for FDB, NIC TX+RX */
1127 void *dr_drop_action; /* Pointer to DR drop action, any domain. */
1128 void *pop_vlan_action; /* Pointer to DR pop VLAN action. */
1129 struct mlx5_hlist *encaps_decaps; /* Encap/decap action hash list. */
1130 struct mlx5_hlist *modify_cmds;
1131 struct mlx5_hlist *tag_table;
1132 struct mlx5_cache_list port_id_action_list; /* Port ID action cache. */
1133 struct mlx5_cache_list push_vlan_action_list; /* Push VLAN actions. */
1134 struct mlx5_cache_list sample_action_list; /* List of sample actions. */
1135 struct mlx5_cache_list dest_array_list;
1136 /* List of destination array actions. */
1137 struct mlx5_flow_counter_mng cmng; /* Counters management structure. */
1138 void *default_miss_action; /* Default miss action. */
1139 struct mlx5_indexed_pool *ipool[MLX5_IPOOL_MAX];
1140 /* Memory Pool for mlx5 flow resources. */
1141 struct mlx5_l3t_tbl *cnt_id_tbl; /* Shared counter lookup table. */
1142 /* Shared interrupt handler section. */
1143 struct rte_intr_handle intr_handle; /* Interrupt handler for device. */
1144 struct rte_intr_handle intr_handle_devx; /* DEVX interrupt handler. */
1145 void *devx_comp; /* DEVX async comp obj. */
1146 struct mlx5_devx_obj *tis; /* TIS object. */
1147 struct mlx5_devx_obj *td; /* Transport domain. */
1148 void *tx_uar; /* Tx/packet pacing shared UAR. */
1149 struct mlx5_flex_parser_profiles fp[MLX5_FLEX_PARSER_MAX];
1150 /* Flex parser profiles information. */
1151 void *devx_rx_uar; /* DevX UAR for Rx. */
1152 struct mlx5_aso_age_mng *aso_age_mng;
1153 /* Management data for aging mechanism using ASO Flow Hit. */
1154 struct mlx5_geneve_tlv_option_resource *geneve_tlv_option_resource;
1155 /* Management structure for geneve tlv option */
1156 rte_spinlock_t geneve_tlv_opt_sl; /* Lock for geneve tlv resource */
1157 struct mlx5_flow_mtr_mng *mtrmng;
1158 /* Meter management structure. */
1159 struct mlx5_aso_ct_pools_mng *ct_mng;
1160 /* Management data for ASO connection tracking. */
1161 struct mlx5_lb_ctx self_lb; /* QP to enable self loopback for Devx. */
1162 struct mlx5_dev_shared_port port[]; /* per device port data array. */
1166 * Per-process private structure.
1167 * Caution, secondary process may rebuild the struct during port start.
1169 struct mlx5_proc_priv {
1170 size_t uar_table_sz;
1171 /* Size of UAR register table. */
1173 /* Table of UAR registers for each process. */
1176 /* MTR profile list. */
1177 TAILQ_HEAD(mlx5_mtr_profiles, mlx5_flow_meter_profile);
1179 TAILQ_HEAD(mlx5_legacy_flow_meters, mlx5_legacy_flow_meter);
1181 /* RSS description. */
1182 struct mlx5_flow_rss_desc {
1184 uint32_t queue_num; /**< Number of entries in @p queue. */
1185 uint64_t types; /**< Specific RSS hash types (see ETH_RSS_*). */
1186 uint64_t hash_fields; /* Verbs Hash fields. */
1187 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
1188 uint32_t key_len; /**< RSS hash key len. */
1189 uint32_t tunnel; /**< Queue in tunnel. */
1190 uint32_t shared_rss; /**< Shared RSS index. */
1191 struct mlx5_ind_table_obj *ind_tbl;
1192 /**< Indirection table for shared RSS hash RX queues. */
1194 uint16_t *queue; /**< Destination queues. */
1195 const uint16_t *const_q; /**< Const pointer convert. */
1199 #define MLX5_PROC_PRIV(port_id) \
1200 ((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private)
1202 /* Verbs/DevX Rx queue elements. */
1203 struct mlx5_rxq_obj {
1204 LIST_ENTRY(mlx5_rxq_obj) next; /* Pointer to the next element. */
1205 struct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */
1206 int fd; /* File descriptor for event channel */
1210 void *wq; /* Work Queue. */
1211 void *ibv_cq; /* Completion Queue. */
1214 struct mlx5_devx_obj *rq; /* DevX RQ object for hairpin. */
1216 struct mlx5_devx_rq rq_obj; /* DevX RQ object. */
1217 struct mlx5_devx_cq cq_obj; /* DevX CQ object. */
1223 /* Indirection table. */
1224 struct mlx5_ind_table_obj {
1225 LIST_ENTRY(mlx5_ind_table_obj) next; /* Pointer to the next element. */
1226 uint32_t refcnt; /* Reference counter. */
1229 void *ind_table; /**< Indirection table. */
1230 struct mlx5_devx_obj *rqt; /* DevX RQT object. */
1232 uint32_t queues_n; /**< Number of queues in the list. */
1233 uint16_t *queues; /**< Queue list. */
1236 /* Hash Rx queue. */
1239 struct mlx5_cache_entry entry; /* Cache entry. */
1240 uint32_t standalone:1; /* This object used in shared action. */
1241 struct mlx5_ind_table_obj *ind_table; /* Indirection table. */
1244 void *qp; /* Verbs queue pair. */
1245 struct mlx5_devx_obj *tir; /* DevX TIR object. */
1247 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
1248 void *action; /* DV QP action pointer. */
1250 uint64_t hash_fields; /* Verbs Hash fields. */
1251 uint32_t rss_key_len; /* Hash key length in bytes. */
1252 uint32_t idx; /* Hash Rx queue index. */
1253 uint8_t rss_key[]; /* Hash key. */
1256 /* Verbs/DevX Tx queue elements. */
1257 struct mlx5_txq_obj {
1258 LIST_ENTRY(mlx5_txq_obj) next; /* Pointer to the next element. */
1259 struct mlx5_txq_ctrl *txq_ctrl; /* Pointer to the control queue. */
1263 void *cq; /* Completion Queue. */
1264 void *qp; /* Queue Pair. */
1267 struct mlx5_devx_obj *sq;
1268 /* DevX object for Sx queue. */
1269 struct mlx5_devx_obj *tis; /* The TIS object. */
1272 struct rte_eth_dev *dev;
1273 struct mlx5_devx_cq cq_obj;
1274 /* DevX CQ object and its resources. */
1275 struct mlx5_devx_sq sq_obj;
1276 /* DevX SQ object and its resources. */
1281 enum mlx5_rxq_modify_type {
1282 MLX5_RXQ_MOD_ERR2RST, /* modify state from error to reset. */
1283 MLX5_RXQ_MOD_RST2RDY, /* modify state from reset to ready. */
1284 MLX5_RXQ_MOD_RDY2ERR, /* modify state from ready to error. */
1285 MLX5_RXQ_MOD_RDY2RST, /* modify state from ready to reset. */
1288 enum mlx5_txq_modify_type {
1289 MLX5_TXQ_MOD_RST2RDY, /* modify state from reset to ready. */
1290 MLX5_TXQ_MOD_RDY2RST, /* modify state from ready to reset. */
1291 MLX5_TXQ_MOD_ERR2RDY, /* modify state from error to ready. */
1294 /* HW objects operations structure. */
1295 struct mlx5_obj_ops {
1296 int (*rxq_obj_modify_vlan_strip)(struct mlx5_rxq_obj *rxq_obj, int on);
1297 int (*rxq_obj_new)(struct rte_eth_dev *dev, uint16_t idx);
1298 int (*rxq_event_get)(struct mlx5_rxq_obj *rxq_obj);
1299 int (*rxq_obj_modify)(struct mlx5_rxq_obj *rxq_obj, uint8_t type);
1300 void (*rxq_obj_release)(struct mlx5_rxq_obj *rxq_obj);
1301 int (*ind_table_new)(struct rte_eth_dev *dev, const unsigned int log_n,
1302 struct mlx5_ind_table_obj *ind_tbl);
1303 int (*ind_table_modify)(struct rte_eth_dev *dev,
1304 const unsigned int log_n,
1305 const uint16_t *queues, const uint32_t queues_n,
1306 struct mlx5_ind_table_obj *ind_tbl);
1307 void (*ind_table_destroy)(struct mlx5_ind_table_obj *ind_tbl);
1308 int (*hrxq_new)(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq,
1309 int tunnel __rte_unused);
1310 int (*hrxq_modify)(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq,
1311 const uint8_t *rss_key,
1312 uint64_t hash_fields,
1313 const struct mlx5_ind_table_obj *ind_tbl);
1314 void (*hrxq_destroy)(struct mlx5_hrxq *hrxq);
1315 int (*drop_action_create)(struct rte_eth_dev *dev);
1316 void (*drop_action_destroy)(struct rte_eth_dev *dev);
1317 int (*txq_obj_new)(struct rte_eth_dev *dev, uint16_t idx);
1318 int (*txq_obj_modify)(struct mlx5_txq_obj *obj,
1319 enum mlx5_txq_modify_type type, uint8_t dev_port);
1320 void (*txq_obj_release)(struct mlx5_txq_obj *txq_obj);
1321 int (*lb_dummy_queue_create)(struct rte_eth_dev *dev);
1322 void (*lb_dummy_queue_release)(struct rte_eth_dev *dev);
1325 #define MLX5_RSS_HASH_FIELDS_LEN RTE_DIM(mlx5_rss_hash_fields)
1327 /* MR operations structure. */
1328 struct mlx5_mr_ops {
1329 mlx5_reg_mr_t reg_mr;
1330 mlx5_dereg_mr_t dereg_mr;
1334 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */
1335 struct mlx5_dev_ctx_shared *sh; /* Shared device context. */
1336 uint32_t dev_port; /* Device port number. */
1337 struct rte_pci_device *pci_dev; /* Backend PCI device. */
1338 struct rte_ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */
1339 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES);
1340 /* Bit-field of MAC addresses owned by the PMD. */
1341 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */
1342 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */
1343 /* Device properties. */
1344 uint16_t mtu; /* Configured MTU. */
1345 unsigned int isolated:1; /* Whether isolated mode is enabled. */
1346 unsigned int representor:1; /* Device is a port representor. */
1347 unsigned int master:1; /* Device is a E-Switch master. */
1348 unsigned int txpp_en:1; /* Tx packet pacing enabled. */
1349 unsigned int sampler_en:1; /* Whether support sampler. */
1350 unsigned int mtr_en:1; /* Whether support meter. */
1351 unsigned int mtr_reg_share:1; /* Whether support meter REG_C share. */
1352 unsigned int lb_used:1; /* Loopback queue is referred to. */
1353 uint16_t domain_id; /* Switch domain identifier. */
1354 uint16_t vport_id; /* Associated VF vport index (if any). */
1355 uint32_t vport_meta_tag; /* Used for vport index match ove VF LAG. */
1356 uint32_t vport_meta_mask; /* Used for vport index field match mask. */
1357 uint16_t representor_id; /* UINT16_MAX if not a representor. */
1358 int32_t pf_bond; /* >=0, representor owner PF index in bonding. */
1359 unsigned int if_index; /* Associated kernel network device index. */
1361 unsigned int rxqs_n; /* RX queues array size. */
1362 unsigned int txqs_n; /* TX queues array size. */
1363 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */
1364 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */
1365 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
1366 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */
1367 unsigned int (*reta_idx)[]; /* RETA index table. */
1368 unsigned int reta_idx_n; /* RETA index size. */
1369 struct mlx5_drop drop_queue; /* Flow drop queues. */
1370 uint32_t flows; /* RTE Flow rules. */
1371 uint32_t ctrl_flows; /* Control flow rules. */
1372 rte_spinlock_t flow_list_lock;
1373 struct mlx5_obj_ops obj_ops; /* HW objects operations. */
1374 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */
1375 LIST_HEAD(rxqobj, mlx5_rxq_obj) rxqsobj; /* Verbs/DevX Rx queues. */
1376 struct mlx5_cache_list hrxqs; /* Hash Rx queues. */
1377 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */
1378 LIST_HEAD(txqobj, mlx5_txq_obj) txqsobj; /* Verbs/DevX Tx queues. */
1379 /* Indirection tables. */
1380 LIST_HEAD(ind_tables, mlx5_ind_table_obj) ind_tbls;
1381 /* Pointer to next element. */
1382 uint32_t refcnt; /**< Reference counter. */
1383 /**< Verbs modify header action object. */
1384 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
1385 uint8_t max_lro_msg_size;
1386 /* Tags resources cache. */
1387 uint32_t link_speed_capa; /* Link speed capabilities. */
1388 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */
1389 struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */
1390 struct mlx5_dev_config config; /* Device configuration. */
1391 /* Context for Verbs allocator. */
1392 int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */
1393 int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */
1394 struct mlx5_nl_vlan_vmwa_context *vmwa_context; /* VLAN WA context. */
1395 struct mlx5_hlist *mreg_cp_tbl;
1396 /* Hash table of Rx metadata register copy table. */
1397 uint8_t mtr_sfx_reg; /* Meter prefix-suffix flow match REG_C. */
1398 uint8_t mtr_color_reg; /* Meter color match REG_C. */
1399 struct mlx5_legacy_flow_meters flow_meters; /* MTR list. */
1400 struct mlx5_l3t_tbl *mtr_profile_tbl; /* Meter index lookup table. */
1401 struct mlx5_l3t_tbl *policy_idx_tbl; /* Policy index lookup table. */
1402 struct mlx5_l3t_tbl *mtr_idx_tbl; /* Meter index lookup table. */
1403 uint8_t skip_default_rss_reta; /* Skip configuration of default reta. */
1404 uint8_t fdb_def_rule; /* Whether fdb jump to table 1 is configured. */
1405 struct mlx5_mp_id mp_id; /* ID of a multi-process process */
1406 LIST_HEAD(fdir, mlx5_fdir_flow) fdir_flows; /* fdir flows. */
1407 rte_spinlock_t shared_act_sl; /* Shared actions spinlock. */
1408 uint32_t rss_shared_actions; /* RSS shared actions. */
1409 struct mlx5_devx_obj *q_counters; /* DevX queue counter object. */
1410 uint32_t counter_set_id; /* Queue counter ID to set in DevX objects. */
1413 #define PORT_ID(priv) ((priv)->dev_data->port_id)
1414 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)])
1416 struct rte_hairpin_peer_info {
1420 uint16_t tx_explicit;
1421 uint16_t manual_bind;
1424 #define BUF_SIZE 1024
1425 enum dr_dump_rec_type {
1426 DR_DUMP_REC_TYPE_PMD_PKT_REFORMAT = 4410,
1427 DR_DUMP_REC_TYPE_PMD_MODIFY_HDR = 4420,
1428 DR_DUMP_REC_TYPE_PMD_COUNTER = 4430,
1433 int mlx5_getenv_int(const char *);
1434 int mlx5_proc_priv_init(struct rte_eth_dev *dev);
1435 void mlx5_proc_priv_uninit(struct rte_eth_dev *dev);
1436 int mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev,
1437 struct rte_eth_udp_tunnel *udp_tunnel);
1438 uint16_t mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev);
1439 int mlx5_dev_close(struct rte_eth_dev *dev);
1440 bool mlx5_is_hpf(struct rte_eth_dev *dev);
1441 void mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh);
1443 /* Macro to iterate over all valid ports for mlx5 driver. */
1444 #define MLX5_ETH_FOREACH_DEV(port_id, pci_dev) \
1445 for (port_id = mlx5_eth_find_next(0, pci_dev); \
1446 port_id < RTE_MAX_ETHPORTS; \
1447 port_id = mlx5_eth_find_next(port_id + 1, pci_dev))
1448 int mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs);
1449 struct mlx5_dev_ctx_shared *
1450 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
1451 const struct mlx5_dev_config *config);
1452 void mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh);
1453 void mlx5_free_table_hash_list(struct mlx5_priv *priv);
1454 int mlx5_alloc_table_hash_list(struct mlx5_priv *priv);
1455 void mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1456 struct mlx5_dev_config *config);
1457 void mlx5_set_metadata_mask(struct rte_eth_dev *dev);
1458 int mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
1459 struct mlx5_dev_config *config);
1460 int mlx5_dev_configure(struct rte_eth_dev *dev);
1461 int mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info);
1462 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size);
1463 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
1464 int mlx5_hairpin_cap_get(struct rte_eth_dev *dev,
1465 struct rte_eth_hairpin_cap *cap);
1466 bool mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev);
1467 int mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev);
1468 int mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh);
1469 int mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh);
1470 int mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh);
1474 int mlx5_dev_configure(struct rte_eth_dev *dev);
1475 int mlx5_representor_info_get(struct rte_eth_dev *dev,
1476 struct rte_eth_representor_info *info);
1477 #define MLX5_REPRESENTOR_ID(pf, type, repr) \
1478 (((pf) << 14) + ((type) << 12) + ((repr) & 0xfff))
1479 #define MLX5_REPRESENTOR_REPR(repr_id) \
1481 #define MLX5_REPRESENTOR_TYPE(repr_id) \
1482 (((repr_id) >> 12) & 3)
1483 uint16_t mlx5_representor_id_encode(const struct mlx5_switch_info *info,
1484 enum rte_eth_representor_type hpf_type);
1485 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver,
1487 int mlx5_dev_infos_get(struct rte_eth_dev *dev,
1488 struct rte_eth_dev_info *info);
1489 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev);
1490 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
1491 int mlx5_hairpin_cap_get(struct rte_eth_dev *dev,
1492 struct rte_eth_hairpin_cap *cap);
1493 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev);
1494 struct mlx5_priv *mlx5_port_to_eswitch_info(uint16_t port, bool valid);
1495 struct mlx5_priv *mlx5_dev_to_eswitch_info(struct rte_eth_dev *dev);
1496 int mlx5_dev_configure_rss_reta(struct rte_eth_dev *dev);
1498 /* mlx5_ethdev_os.c */
1500 int mlx5_get_ifname(const struct rte_eth_dev *dev,
1501 char (*ifname)[MLX5_NAMESIZE]);
1502 unsigned int mlx5_ifindex(const struct rte_eth_dev *dev);
1503 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]);
1504 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu);
1505 int mlx5_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
1506 int mlx5_read_clock(struct rte_eth_dev *dev, uint64_t *clock);
1507 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete);
1508 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev,
1509 struct rte_eth_fc_conf *fc_conf);
1510 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev,
1511 struct rte_eth_fc_conf *fc_conf);
1512 void mlx5_dev_interrupt_handler(void *arg);
1513 void mlx5_dev_interrupt_handler_devx(void *arg);
1514 int mlx5_set_link_down(struct rte_eth_dev *dev);
1515 int mlx5_set_link_up(struct rte_eth_dev *dev);
1516 int mlx5_is_removed(struct rte_eth_dev *dev);
1517 int mlx5_sysfs_switch_info(unsigned int ifindex,
1518 struct mlx5_switch_info *info);
1519 void mlx5_translate_port_name(const char *port_name_in,
1520 struct mlx5_switch_info *port_info_out);
1521 void mlx5_intr_callback_unregister(const struct rte_intr_handle *handle,
1522 rte_intr_callback_fn cb_fn, void *cb_arg);
1523 int mlx5_sysfs_bond_info(unsigned int pf_ifindex, unsigned int *ifindex,
1525 int mlx5_get_module_info(struct rte_eth_dev *dev,
1526 struct rte_eth_dev_module_info *modinfo);
1527 int mlx5_get_module_eeprom(struct rte_eth_dev *dev,
1528 struct rte_dev_eeprom_info *info);
1529 int mlx5_os_read_dev_stat(struct mlx5_priv *priv,
1530 const char *ctr_name, uint64_t *stat);
1531 int mlx5_os_read_dev_counters(struct rte_eth_dev *dev, uint64_t *stats);
1532 int mlx5_os_get_stats_n(struct rte_eth_dev *dev);
1533 void mlx5_os_stats_init(struct rte_eth_dev *dev);
1537 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
1538 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
1539 uint32_t index, uint32_t vmdq);
1540 int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr);
1541 int mlx5_set_mc_addr_list(struct rte_eth_dev *dev,
1542 struct rte_ether_addr *mc_addr_set,
1543 uint32_t nb_mc_addr);
1547 int mlx5_rss_hash_update(struct rte_eth_dev *dev,
1548 struct rte_eth_rss_conf *rss_conf);
1549 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev,
1550 struct rte_eth_rss_conf *rss_conf);
1551 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size);
1552 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev,
1553 struct rte_eth_rss_reta_entry64 *reta_conf,
1554 uint16_t reta_size);
1555 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev,
1556 struct rte_eth_rss_reta_entry64 *reta_conf,
1557 uint16_t reta_size);
1561 int mlx5_promiscuous_enable(struct rte_eth_dev *dev);
1562 int mlx5_promiscuous_disable(struct rte_eth_dev *dev);
1563 int mlx5_allmulticast_enable(struct rte_eth_dev *dev);
1564 int mlx5_allmulticast_disable(struct rte_eth_dev *dev);
1568 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
1569 int mlx5_stats_reset(struct rte_eth_dev *dev);
1570 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats,
1572 int mlx5_xstats_reset(struct rte_eth_dev *dev);
1573 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
1574 struct rte_eth_xstat_name *xstats_names,
1579 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
1580 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on);
1581 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask);
1583 /* mlx5_vlan_os.c */
1585 void mlx5_vlan_vmwa_exit(void *ctx);
1586 void mlx5_vlan_vmwa_release(struct rte_eth_dev *dev,
1587 struct mlx5_vf_vlan *vf_vlan);
1588 void mlx5_vlan_vmwa_acquire(struct rte_eth_dev *dev,
1589 struct mlx5_vf_vlan *vf_vlan);
1590 void *mlx5_vlan_vmwa_init(struct rte_eth_dev *dev, uint32_t ifindex);
1592 /* mlx5_trigger.c */
1594 int mlx5_dev_start(struct rte_eth_dev *dev);
1595 int mlx5_dev_stop(struct rte_eth_dev *dev);
1596 int mlx5_traffic_enable(struct rte_eth_dev *dev);
1597 void mlx5_traffic_disable(struct rte_eth_dev *dev);
1598 int mlx5_traffic_restart(struct rte_eth_dev *dev);
1599 int mlx5_hairpin_queue_peer_update(struct rte_eth_dev *dev, uint16_t peer_queue,
1600 struct rte_hairpin_peer_info *current_info,
1601 struct rte_hairpin_peer_info *peer_info,
1602 uint32_t direction);
1603 int mlx5_hairpin_queue_peer_bind(struct rte_eth_dev *dev, uint16_t cur_queue,
1604 struct rte_hairpin_peer_info *peer_info,
1605 uint32_t direction);
1606 int mlx5_hairpin_queue_peer_unbind(struct rte_eth_dev *dev, uint16_t cur_queue,
1607 uint32_t direction);
1608 int mlx5_hairpin_bind(struct rte_eth_dev *dev, uint16_t rx_port);
1609 int mlx5_hairpin_unbind(struct rte_eth_dev *dev, uint16_t rx_port);
1610 int mlx5_hairpin_get_peer_ports(struct rte_eth_dev *dev, uint16_t *peer_ports,
1611 size_t len, uint32_t direction);
1615 int mlx5_flow_discover_mreg_c(struct rte_eth_dev *eth_dev);
1616 bool mlx5_flow_ext_mreg_supported(struct rte_eth_dev *dev);
1617 void mlx5_flow_print(struct rte_flow *flow);
1618 int mlx5_flow_validate(struct rte_eth_dev *dev,
1619 const struct rte_flow_attr *attr,
1620 const struct rte_flow_item items[],
1621 const struct rte_flow_action actions[],
1622 struct rte_flow_error *error);
1623 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev,
1624 const struct rte_flow_attr *attr,
1625 const struct rte_flow_item items[],
1626 const struct rte_flow_action actions[],
1627 struct rte_flow_error *error);
1628 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow,
1629 struct rte_flow_error *error);
1630 void mlx5_flow_list_flush(struct rte_eth_dev *dev, uint32_t *list, bool active);
1631 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error);
1632 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow,
1633 const struct rte_flow_action *action, void *data,
1634 struct rte_flow_error *error);
1635 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable,
1636 struct rte_flow_error *error);
1637 int mlx5_flow_ops_get(struct rte_eth_dev *dev, const struct rte_flow_ops **ops);
1638 int mlx5_flow_start_default(struct rte_eth_dev *dev);
1639 void mlx5_flow_stop_default(struct rte_eth_dev *dev);
1640 int mlx5_flow_verify(struct rte_eth_dev *dev);
1641 int mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, uint32_t queue);
1642 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev,
1643 struct rte_flow_item_eth *eth_spec,
1644 struct rte_flow_item_eth *eth_mask,
1645 struct rte_flow_item_vlan *vlan_spec,
1646 struct rte_flow_item_vlan *vlan_mask);
1647 int mlx5_ctrl_flow(struct rte_eth_dev *dev,
1648 struct rte_flow_item_eth *eth_spec,
1649 struct rte_flow_item_eth *eth_mask);
1650 int mlx5_flow_lacp_miss(struct rte_eth_dev *dev);
1651 struct rte_flow *mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev);
1652 void mlx5_flow_async_pool_query_handle(struct mlx5_dev_ctx_shared *sh,
1653 uint64_t async_id, int status);
1654 void mlx5_set_query_alarm(struct mlx5_dev_ctx_shared *sh);
1655 void mlx5_flow_query_alarm(void *arg);
1656 uint32_t mlx5_counter_alloc(struct rte_eth_dev *dev);
1657 void mlx5_counter_free(struct rte_eth_dev *dev, uint32_t cnt);
1658 int mlx5_counter_query(struct rte_eth_dev *dev, uint32_t cnt,
1659 bool clear, uint64_t *pkts, uint64_t *bytes);
1660 int mlx5_flow_dev_dump(struct rte_eth_dev *dev, struct rte_flow *flow,
1661 FILE *file, struct rte_flow_error *error);
1662 int save_dump_file(const unsigned char *data, uint32_t size,
1663 uint32_t type, uint32_t id, void *arg, FILE *file);
1664 int mlx5_flow_query_counter(struct rte_eth_dev *dev, struct rte_flow *flow,
1665 struct rte_flow_query_count *count, struct rte_flow_error *error);
1666 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1667 int mlx5_flow_dev_dump_ipool(struct rte_eth_dev *dev, struct rte_flow *flow,
1668 FILE *file, struct rte_flow_error *error);
1670 void mlx5_flow_rxq_dynf_metadata_set(struct rte_eth_dev *dev);
1671 int mlx5_flow_get_aged_flows(struct rte_eth_dev *dev, void **contexts,
1672 uint32_t nb_contexts, struct rte_flow_error *error);
1673 int mlx5_validate_action_ct(struct rte_eth_dev *dev,
1674 const struct rte_flow_action_conntrack *conntrack,
1675 struct rte_flow_error *error);
1680 int mlx5_mp_os_primary_handle(const struct rte_mp_msg *mp_msg,
1682 int mlx5_mp_os_secondary_handle(const struct rte_mp_msg *mp_msg,
1684 void mlx5_mp_os_req_start_rxtx(struct rte_eth_dev *dev);
1685 void mlx5_mp_os_req_stop_rxtx(struct rte_eth_dev *dev);
1686 int mlx5_mp_os_req_queue_control(struct rte_eth_dev *dev, uint16_t queue_id,
1687 enum mlx5_mp_req_type req_type);
1691 int mlx5_pmd_socket_init(void);
1693 /* mlx5_flow_meter.c */
1695 int mlx5_flow_meter_ops_get(struct rte_eth_dev *dev, void *arg);
1696 struct mlx5_flow_meter_info *mlx5_flow_meter_find(struct mlx5_priv *priv,
1697 uint32_t meter_id, uint32_t *mtr_idx);
1698 struct mlx5_flow_meter_info *
1699 flow_dv_meter_find_by_idx(struct mlx5_priv *priv, uint32_t idx);
1700 int mlx5_flow_meter_attach(struct mlx5_priv *priv,
1701 struct mlx5_flow_meter_info *fm,
1702 const struct rte_flow_attr *attr,
1703 struct rte_flow_error *error);
1704 void mlx5_flow_meter_detach(struct mlx5_priv *priv,
1705 struct mlx5_flow_meter_info *fm);
1706 struct mlx5_flow_meter_policy *mlx5_flow_meter_policy_find
1707 (struct rte_eth_dev *dev,
1709 uint32_t *policy_idx);
1710 struct mlx5_flow_meter_policy *
1711 mlx5_flow_meter_hierarchy_get_final_policy(struct rte_eth_dev *dev,
1712 struct mlx5_flow_meter_policy *policy);
1713 int mlx5_flow_meter_flush(struct rte_eth_dev *dev,
1714 struct rte_mtr_error *error);
1715 void mlx5_flow_meter_rxq_flush(struct rte_eth_dev *dev);
1718 struct rte_pci_driver;
1719 int mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *dev_attr);
1720 void mlx5_os_free_shared_dr(struct mlx5_priv *priv);
1721 int mlx5_os_open_device(const struct mlx5_dev_spawn_data *spawn,
1722 const struct mlx5_dev_config *config,
1723 struct mlx5_dev_ctx_shared *sh);
1724 int mlx5_os_get_pdn(void *pd, uint32_t *pdn);
1725 int mlx5_os_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1726 struct rte_pci_device *pci_dev);
1727 void mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh);
1728 void mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh);
1729 void mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb,
1730 mlx5_dereg_mr_t *dereg_mr_cb);
1731 void mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
1732 int mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
1734 int mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv, unsigned int iface_idx,
1735 struct rte_ether_addr *mac_addr,
1737 int mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable);
1738 int mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable);
1739 int mlx5_os_set_nonblock_channel_fd(int fd);
1740 void mlx5_os_mac_addr_flush(struct rte_eth_dev *dev);
1744 int mlx5_txpp_start(struct rte_eth_dev *dev);
1745 void mlx5_txpp_stop(struct rte_eth_dev *dev);
1746 int mlx5_txpp_read_clock(struct rte_eth_dev *dev, uint64_t *timestamp);
1747 int mlx5_txpp_xstats_get(struct rte_eth_dev *dev,
1748 struct rte_eth_xstat *stats,
1749 unsigned int n, unsigned int n_used);
1750 int mlx5_txpp_xstats_reset(struct rte_eth_dev *dev);
1751 int mlx5_txpp_xstats_get_names(struct rte_eth_dev *dev,
1752 struct rte_eth_xstat_name *xstats_names,
1753 unsigned int n, unsigned int n_used);
1754 void mlx5_txpp_interrupt_handler(void *cb_arg);
1758 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev);
1760 /* mlx5_flow_aso.c */
1762 int mlx5_aso_queue_init(struct mlx5_dev_ctx_shared *sh,
1763 enum mlx5_access_aso_opc_mod aso_opc_mod);
1764 int mlx5_aso_flow_hit_queue_poll_start(struct mlx5_dev_ctx_shared *sh);
1765 int mlx5_aso_flow_hit_queue_poll_stop(struct mlx5_dev_ctx_shared *sh);
1766 void mlx5_aso_queue_uninit(struct mlx5_dev_ctx_shared *sh,
1767 enum mlx5_access_aso_opc_mod aso_opc_mod);
1768 int mlx5_aso_meter_update_by_wqe(struct mlx5_dev_ctx_shared *sh,
1769 struct mlx5_aso_mtr *mtr);
1770 int mlx5_aso_mtr_wait(struct mlx5_dev_ctx_shared *sh,
1771 struct mlx5_aso_mtr *mtr);
1772 int mlx5_aso_ct_update_by_wqe(struct mlx5_dev_ctx_shared *sh,
1773 struct mlx5_aso_ct_action *ct,
1774 const struct rte_flow_action_conntrack *profile);
1775 int mlx5_aso_ct_wait_ready(struct mlx5_dev_ctx_shared *sh,
1776 struct mlx5_aso_ct_action *ct);
1777 int mlx5_aso_ct_query_by_wqe(struct mlx5_dev_ctx_shared *sh,
1778 struct mlx5_aso_ct_action *ct,
1779 struct rte_flow_action_conntrack *profile);
1780 int mlx5_aso_ct_available(struct mlx5_dev_ctx_shared *sh,
1781 struct mlx5_aso_ct_action *ct);
1783 #endif /* RTE_PMD_MLX5_H_ */