1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_H_
7 #define RTE_PMD_MLX5_H_
13 #include <netinet/in.h>
14 #include <sys/queue.h>
17 #include <rte_ether.h>
18 #include <rte_ethdev_driver.h>
19 #include <rte_rwlock.h>
20 #include <rte_interrupts.h>
21 #include <rte_errno.h>
24 #include <mlx5_glue.h>
25 #include <mlx5_devx_cmds.h>
27 #include <mlx5_common_mp.h>
28 #include <mlx5_common_mr.h>
30 #include "mlx5_defs.h"
31 #include "mlx5_utils.h"
33 #include "mlx5_autoconf.h"
35 enum mlx5_ipool_index {
36 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
37 MLX5_IPOOL_DECAP_ENCAP = 0, /* Pool for encap/decap resource. */
38 MLX5_IPOOL_PUSH_VLAN, /* Pool for push vlan resource. */
39 MLX5_IPOOL_TAG, /* Pool for tag resource. */
40 MLX5_IPOOL_PORT_ID, /* Pool for port id resource. */
41 MLX5_IPOOL_JUMP, /* Pool for jump resource. */
42 MLX5_IPOOL_SAMPLE, /* Pool for sample resource. */
43 MLX5_IPOOL_DEST_ARRAY, /* Pool for destination array resource. */
45 MLX5_IPOOL_MTR, /* Pool for meter resource. */
46 MLX5_IPOOL_MCP, /* Pool for metadata resource. */
47 MLX5_IPOOL_HRXQ, /* Pool for hrxq resource. */
48 MLX5_IPOOL_MLX5_FLOW, /* Pool for mlx5 flow handle. */
49 MLX5_IPOOL_RTE_FLOW, /* Pool for rte_flow. */
54 * There are three reclaim memory mode supported.
55 * 0(none) means no memory reclaim.
56 * 1(light) means only PMD level reclaim.
57 * 2(aggressive) means both PMD and rdma-core level reclaim.
59 enum mlx5_reclaim_mem_mode {
60 MLX5_RCM_NONE, /* Don't reclaim memory. */
61 MLX5_RCM_LIGHT, /* Reclaim PMD level. */
62 MLX5_RCM_AGGR, /* Reclaim PMD and rdma-core level. */
65 /* Device attributes used in mlx5 PMD */
66 struct mlx5_dev_attr {
67 uint64_t device_cap_flags_ex;
72 uint32_t raw_packet_caps;
73 uint32_t max_rwq_indirection_table_size;
75 uint32_t tso_supported_qpts;
78 uint32_t sw_parsing_offloads;
79 uint32_t min_single_stride_log_num_of_bytes;
80 uint32_t max_single_stride_log_num_of_bytes;
81 uint32_t min_single_wqe_log_num_of_strides;
82 uint32_t max_single_wqe_log_num_of_strides;
83 uint32_t stride_supported_qpts;
84 uint32_t tunnel_offloads_caps;
88 /** Data associated with devices to spawn. */
89 struct mlx5_dev_spawn_data {
90 uint32_t ifindex; /**< Network interface index. */
91 uint32_t max_port; /**< Device maximal port index. */
92 uint32_t phys_port; /**< Device physical port index. */
93 int pf_bond; /**< bonding device PF index. < 0 - no bonding */
94 struct mlx5_switch_info info; /**< Switch information. */
95 void *phys_dev; /**< Associated physical device. */
96 struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */
97 struct rte_pci_device *pci_dev; /**< Backend PCI device. */
100 /** Key string for IPC. */
101 #define MLX5_MP_NAME "net_mlx5_mp"
104 LIST_HEAD(mlx5_dev_list, mlx5_dev_ctx_shared);
106 /* Shared data between primary and secondary processes. */
107 struct mlx5_shared_data {
109 /* Global spinlock for primary and secondary processes. */
110 int init_done; /* Whether primary has done initialization. */
111 unsigned int secondary_cnt; /* Number of secondary processes init'd. */
112 struct mlx5_dev_list mem_event_cb_list;
113 rte_rwlock_t mem_event_rwlock;
116 /* Per-process data structure, not visible to other processes. */
117 struct mlx5_local_data {
118 int init_done; /* Whether a secondary has done initialization. */
121 extern struct mlx5_shared_data *mlx5_shared_data;
123 /* Dev ops structs */
124 extern const struct eth_dev_ops mlx5_os_dev_ops;
125 extern const struct eth_dev_ops mlx5_os_dev_sec_ops;
126 extern const struct eth_dev_ops mlx5_os_dev_ops_isolate;
128 struct mlx5_counter_ctrl {
129 /* Name of the counter. */
130 char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE];
131 /* Name of the counter on the device table. */
132 char ctr_name[RTE_ETH_XSTATS_NAME_SIZE];
133 uint32_t dev:1; /**< Nonzero for dev counters. */
136 struct mlx5_xstats_ctrl {
137 /* Number of device stats. */
139 /* Number of device stats identified by PMD. */
140 uint16_t mlx5_stats_n;
141 /* Index in the device counters table. */
142 uint16_t dev_table_idx[MLX5_MAX_XSTATS];
143 uint64_t base[MLX5_MAX_XSTATS];
144 uint64_t xstats[MLX5_MAX_XSTATS];
145 uint64_t hw_stats[MLX5_MAX_XSTATS];
146 struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS];
149 struct mlx5_stats_ctrl {
150 /* Base for imissed counter. */
151 uint64_t imissed_base;
155 /* Default PMD specific parameter value. */
156 #define MLX5_ARG_UNSET (-1)
158 #define MLX5_LRO_SUPPORTED(dev) \
159 (((struct mlx5_priv *)((dev)->data->dev_private))->config.lro.supported)
161 /* Maximal size of coalesced segment for LRO is set in chunks of 256 Bytes. */
162 #define MLX5_LRO_SEG_CHUNK_SIZE 256u
164 /* Maximal size of aggregated LRO packet. */
165 #define MLX5_MAX_LRO_SIZE (UINT8_MAX * MLX5_LRO_SEG_CHUNK_SIZE)
167 /* LRO configurations structure. */
168 struct mlx5_lro_config {
169 uint32_t supported:1; /* Whether LRO is supported. */
170 uint32_t timeout; /* User configuration. */
174 * Device configuration structure.
176 * Merged configuration from:
178 * - Device capabilities,
179 * - User device parameters disabled features.
181 struct mlx5_dev_config {
182 unsigned int hw_csum:1; /* Checksum offload is supported. */
183 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */
184 unsigned int hw_vlan_insert:1; /* VLAN insertion in WQE is supported. */
185 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */
186 unsigned int hw_padding:1; /* End alignment padding is supported. */
187 unsigned int vf:1; /* This is a VF. */
188 unsigned int tunnel_en:1;
189 /* Whether tunnel stateless offloads are supported. */
190 unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */
191 unsigned int cqe_comp:1; /* CQE compression is enabled. */
192 unsigned int cqe_pad:1; /* CQE padding is enabled. */
193 unsigned int tso:1; /* Whether TSO is supported. */
194 unsigned int rx_vec_en:1; /* Rx vector is enabled. */
195 unsigned int mr_ext_memseg_en:1;
196 /* Whether memseg should be extended for MR creation. */
197 unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */
198 unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */
199 unsigned int dv_esw_en:1; /* Enable E-Switch DV flow. */
200 unsigned int dv_flow_en:1; /* Enable DV flow. */
201 unsigned int dv_xmeta_en:2; /* Enable extensive flow metadata. */
202 unsigned int lacp_by_user:1;
203 /* Enable user to manage LACP traffic. */
204 unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */
205 unsigned int devx:1; /* Whether devx interface is available or not. */
206 unsigned int dest_tir:1; /* Whether advanced DR API is available. */
207 unsigned int reclaim_mode:2; /* Memory reclaim mode. */
208 unsigned int rt_timestamp:1; /* realtime timestamp format. */
209 unsigned int sys_mem_en:1; /* The default memory allocator. */
210 unsigned int decap_en:1; /* Whether decap will be used or not. */
212 unsigned int enabled:1; /* Whether MPRQ is enabled. */
213 unsigned int stride_num_n; /* Number of strides. */
214 unsigned int stride_size_n; /* Size of a stride. */
215 unsigned int min_stride_size_n; /* Min size of a stride. */
216 unsigned int max_stride_size_n; /* Max size of a stride. */
217 unsigned int max_memcpy_len;
218 /* Maximum packet size to memcpy Rx packets. */
219 unsigned int min_rxqs_num;
220 /* Rx queue count threshold to enable MPRQ. */
221 } mprq; /* Configurations for Multi-Packet RQ. */
222 int mps; /* Multi-packet send supported mode. */
223 int dbnc; /* Skip doorbell register write barrier. */
224 unsigned int flow_prio; /* Number of flow priorities. */
225 enum modify_reg flow_mreg_c[MLX5_MREG_C_NUM];
226 /* Availibility of mreg_c's. */
227 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */
228 unsigned int ind_table_max_size; /* Maximum indirection table size. */
229 unsigned int max_dump_files_num; /* Maximum dump files per queue. */
230 unsigned int log_hp_size; /* Single hairpin queue data size in total. */
231 int txqs_inline; /* Queue number threshold for inlining. */
232 int txq_inline_min; /* Minimal amount of data bytes to inline. */
233 int txq_inline_max; /* Max packet size for inlining with SEND. */
234 int txq_inline_mpw; /* Max packet size for inlining with eMPW. */
235 int tx_pp; /* Timestamp scheduling granularity in nanoseconds. */
236 int tx_skew; /* Tx scheduling skew between WQE and data on wire. */
237 struct mlx5_hca_attr hca_attr; /* HCA attributes. */
238 struct mlx5_lro_config lro; /* LRO configuration. */
243 * Type of object being allocated.
245 enum mlx5_verbs_alloc_type {
246 MLX5_VERBS_ALLOC_TYPE_NONE,
247 MLX5_VERBS_ALLOC_TYPE_TX_QUEUE,
248 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE,
251 /* Structure for VF VLAN workaround. */
252 struct mlx5_vf_vlan {
258 * Verbs allocator needs a context to know in the callback which kind of
259 * resources it is allocating.
261 struct mlx5_verbs_alloc_ctx {
262 enum mlx5_verbs_alloc_type type; /* Kind of object being allocated. */
263 const void *obj; /* Pointer to the DPDK object. */
266 /* Flow drop context necessary due to Verbs API. */
268 struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */
269 struct mlx5_rxq_obj *rxq; /* Rx queue object. */
272 #define MLX5_COUNTERS_PER_POOL 512
273 #define MLX5_MAX_PENDING_QUERIES 4
274 #define MLX5_CNT_CONTAINER_RESIZE 64
275 #define MLX5_CNT_SHARED_OFFSET 0x80000000
276 #define IS_SHARED_CNT(cnt) (!!((cnt) & MLX5_CNT_SHARED_OFFSET))
277 #define IS_BATCH_CNT(cnt) (((cnt) & (MLX5_CNT_SHARED_OFFSET - 1)) >= \
278 MLX5_CNT_BATCH_OFFSET)
279 #define MLX5_CNT_SIZE (sizeof(struct mlx5_flow_counter))
280 #define MLX5_AGE_SIZE (sizeof(struct mlx5_age_param))
282 #define MLX5_CNT_LEN(pool) \
284 ((pool)->is_aged ? MLX5_AGE_SIZE : 0))
285 #define MLX5_POOL_GET_CNT(pool, index) \
286 ((struct mlx5_flow_counter *) \
287 ((uint8_t *)((pool) + 1) + (index) * (MLX5_CNT_LEN(pool))))
288 #define MLX5_CNT_ARRAY_IDX(pool, cnt) \
289 ((int)(((uint8_t *)(cnt) - (uint8_t *)((pool) + 1)) / \
292 * The pool index and offset of counter in the pool array makes up the
293 * counter index. In case the counter is from pool 0 and offset 0, it
294 * should plus 1 to avoid index 0, since 0 means invalid counter index
297 #define MLX5_MAKE_CNT_IDX(pi, offset) \
298 ((pi) * MLX5_COUNTERS_PER_POOL + (offset) + 1)
299 #define MLX5_CNT_TO_AGE(cnt) \
300 ((struct mlx5_age_param *)((cnt) + 1))
302 * The maximum single counter is 0x800000 as MLX5_CNT_BATCH_OFFSET
303 * defines. The pool size is 512, pool index should never reach
306 #define POOL_IDX_INVALID UINT16_MAX
310 AGE_FREE, /* Initialized state. */
311 AGE_CANDIDATE, /* Counter assigned to flows. */
312 AGE_TMOUT, /* Timeout, wait for rte_flow_get_aged_flows and destroy. */
315 enum mlx5_counter_type {
316 MLX5_COUNTER_TYPE_ORIGIN,
317 MLX5_COUNTER_TYPE_AGE,
318 MLX5_COUNTER_TYPE_MAX,
321 /* Counter age parameter. */
322 struct mlx5_age_param {
323 uint16_t state; /**< Age state (atomically accessed). */
324 uint16_t port_id; /**< Port id of the counter. */
325 uint32_t timeout:24; /**< Aging timeout in seconds. */
326 uint32_t sec_since_last_hit;
327 /**< Time in seconds since last hit (atomically accessed). */
328 void *context; /**< Flow counter age context. */
331 struct flow_counter_stats {
336 /* Shared counters information for counters. */
337 struct mlx5_flow_counter_shared {
338 uint32_t id; /**< User counter ID. */
341 /* Shared counter configuration. */
342 struct mlx5_shared_counter_conf {
343 struct rte_eth_dev *dev; /* The device shared counter belongs to. */
344 uint32_t id; /* The shared counter ID. */
347 struct mlx5_flow_counter_pool;
348 /* Generic counters information. */
349 struct mlx5_flow_counter {
352 * User-defined counter shared info is only used during
353 * counter active time. And aging counter sharing is not
354 * supported, so active shared counter will not be chained
355 * to the aging list. For shared counter, only when it is
356 * released, the TAILQ entry memory will be used, at that
357 * time, shared memory is not used anymore.
359 * Similarly to none-batch counter dcs, since it doesn't
360 * support aging, while counter is allocated, the entry
361 * memory is not used anymore. In this case, as bytes
362 * memory is used only when counter is allocated, and
363 * entry memory is used only when counter is free. The
364 * dcs pointer can be saved to these two different place
365 * at different stage. It will eliminate the individual
366 * counter extend struct.
368 TAILQ_ENTRY(mlx5_flow_counter) next;
369 /**< Pointer to the next flow counter structure. */
371 struct mlx5_flow_counter_shared shared_info;
372 /**< Shared counter information. */
373 void *dcs_when_active;
375 * For non-batch mode, the dcs will be saved
376 * here when the counter is free.
381 uint64_t hits; /**< Reset value of hits packets. */
382 struct mlx5_flow_counter_pool *pool; /**< Counter pool. */
385 uint64_t bytes; /**< Reset value of bytes. */
388 * For non-batch mode, the dcs will be saved here
389 * when the counter is free.
392 void *action; /**< Pointer to the dv action. */
395 TAILQ_HEAD(mlx5_counters, mlx5_flow_counter);
397 /* Generic counter pool structure - query is in pool resolution. */
398 struct mlx5_flow_counter_pool {
399 TAILQ_ENTRY(mlx5_flow_counter_pool) next;
400 struct mlx5_counters counters[2]; /* Free counter list. */
402 struct mlx5_devx_obj *min_dcs;
403 rte_atomic64_t a64_dcs;
405 /* The devx object of the minimum counter ID. */
406 uint64_t time_of_last_age_check;
407 /* System time (from rte_rdtsc()) read in the last aging check. */
408 uint32_t index:30; /* Pool index in container. */
409 uint32_t is_aged:1; /* Pool with aging counter. */
410 volatile uint32_t query_gen:1; /* Query round. */
411 rte_spinlock_t sl; /* The pool lock. */
412 rte_spinlock_t csl; /* The pool counter free list lock. */
413 struct mlx5_counter_stats_raw *raw;
414 struct mlx5_counter_stats_raw *raw_hw;
415 /* The raw on HW working. */
418 /* Memory management structure for group of counter statistics raws. */
419 struct mlx5_counter_stats_mem_mng {
420 LIST_ENTRY(mlx5_counter_stats_mem_mng) next;
421 struct mlx5_counter_stats_raw *raws;
422 struct mlx5_devx_obj *dm;
426 /* Raw memory structure for the counter statistics values of a pool. */
427 struct mlx5_counter_stats_raw {
428 LIST_ENTRY(mlx5_counter_stats_raw) next;
429 struct mlx5_counter_stats_mem_mng *mem_mng;
430 volatile struct flow_counter_stats *data;
433 TAILQ_HEAD(mlx5_counter_pools, mlx5_flow_counter_pool);
435 /* Counter global management structure. */
436 struct mlx5_flow_counter_mng {
437 volatile uint16_t n_valid; /* Number of valid pools. */
438 uint16_t n; /* Number of pools. */
439 uint16_t last_pool_idx; /* Last used pool index */
440 int min_id; /* The minimum counter ID in the pools. */
441 int max_id; /* The maximum counter ID in the pools. */
442 rte_spinlock_t pool_update_sl; /* The pool update lock. */
443 rte_spinlock_t csl[MLX5_COUNTER_TYPE_MAX];
444 /* The counter free list lock. */
445 struct mlx5_counters counters[MLX5_COUNTER_TYPE_MAX];
446 /* Free counter list. */
447 struct mlx5_flow_counter_pool **pools; /* Counter pool array. */
448 struct mlx5_counter_stats_mem_mng *mem_mng;
449 /* Hold the memory management for the next allocated pools raws. */
450 struct mlx5_counters flow_counters; /* Legacy flow counter list. */
451 uint8_t pending_queries;
453 uint8_t query_thread_on;
454 bool relaxed_ordering;
455 bool counter_fallback; /* Use counter fallback management. */
456 LIST_HEAD(mem_mngs, mlx5_counter_stats_mem_mng) mem_mngs;
457 LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws;
460 /* Default miss action resource structure. */
461 struct mlx5_flow_default_miss_resource {
462 void *action; /* Pointer to the rdma-core action. */
463 rte_atomic32_t refcnt; /* Default miss action reference counter. */
466 #define MLX5_AGE_EVENT_NEW 1
467 #define MLX5_AGE_TRIGGER 2
468 #define MLX5_AGE_SET(age_info, BIT) \
469 ((age_info)->flags |= (1 << (BIT)))
470 #define MLX5_AGE_GET(age_info, BIT) \
471 ((age_info)->flags & (1 << (BIT)))
472 #define GET_PORT_AGE_INFO(priv) \
473 (&((priv)->sh->port[(priv)->dev_port - 1].age_info))
474 /* Current time in seconds. */
475 #define MLX5_CURR_TIME_SEC (rte_rdtsc() / rte_get_tsc_hz())
477 /* Aging information for per port. */
478 struct mlx5_age_info {
479 uint8_t flags; /* Indicate if is new event or need to be triggered. */
480 struct mlx5_counters aged_counters; /* Aged flow counter list. */
481 rte_spinlock_t aged_sl; /* Aged flow counter list lock. */
484 /* Per port data of shared IB device. */
485 struct mlx5_dev_shared_port {
487 uint32_t devx_ih_port_id;
489 * Interrupt handler port_id. Used by shared interrupt
490 * handler to find the corresponding rte_eth device
491 * by IB port index. If value is equal or greater
492 * RTE_MAX_ETHPORTS it means there is no subhandler
493 * installed for specified IB port index.
495 struct mlx5_age_info age_info;
496 /* Aging information for per port. */
499 /* Table key of the hash organization. */
500 union mlx5_flow_tbl_key {
502 /* Table ID should be at the lowest address. */
503 uint32_t table_id; /**< ID of the table. */
504 uint16_t reserved; /**< must be zero for comparison. */
505 uint8_t domain; /**< 1 - FDB, 0 - NIC TX/RX. */
506 uint8_t direction; /**< 1 - egress, 0 - ingress. */
508 uint64_t v64; /**< full 64bits value of key */
511 /* Table structure. */
512 struct mlx5_flow_tbl_resource {
513 void *obj; /**< Pointer to DR table object. */
514 rte_atomic32_t refcnt; /**< Reference counter. */
517 #define MLX5_MAX_TABLES UINT16_MAX
518 #define MLX5_HAIRPIN_TX_TABLE (UINT16_MAX - 1)
519 /* Reserve the last two tables for metadata register copy. */
520 #define MLX5_FLOW_MREG_ACT_TABLE_GROUP (MLX5_MAX_TABLES - 1)
521 #define MLX5_FLOW_MREG_CP_TABLE_GROUP (MLX5_MAX_TABLES - 2)
522 /* Tables for metering splits should be added here. */
523 #define MLX5_MAX_TABLES_EXTERNAL (MLX5_MAX_TABLES - 3)
524 #define MLX5_FLOW_TABLE_LEVEL_METER (MLX5_MAX_TABLES - 4)
525 #define MLX5_FLOW_TABLE_LEVEL_SUFFIX (MLX5_MAX_TABLES - 3)
526 #define MLX5_MAX_TABLES_FDB UINT16_MAX
527 #define MLX5_FLOW_TABLE_FACTOR 10
529 /* ID generation structure. */
530 struct mlx5_flow_id_pool {
531 uint32_t *free_arr; /**< Pointer to the a array of free values. */
533 /**< The next index that can be used without any free elements. */
534 uint32_t *curr; /**< Pointer to the index to pop. */
535 uint32_t *last; /**< Pointer to the last element in the empty arrray. */
536 uint32_t max_id; /**< Maximum id can be allocated from the pool. */
539 /* Tx pacing queue structure - for Clock and Rearm queues. */
540 struct mlx5_txpp_wq {
541 /* Completion Queue related data.*/
542 struct mlx5_devx_obj *cq;
545 volatile void *cq_buf;
546 volatile struct mlx5_cqe *cqes;
548 volatile uint32_t *cq_dbrec;
551 /* Send Queue related data.*/
552 struct mlx5_devx_obj *sq;
555 volatile void *sq_buf;
556 volatile struct mlx5_wqe *wqes;
558 uint16_t sq_size; /* Number of WQEs in the queue. */
559 uint16_t sq_ci; /* Next WQE to execute. */
560 volatile uint32_t *sq_dbrec;
563 /* Tx packet pacing internal timestamp. */
564 struct mlx5_txpp_ts {
565 rte_atomic64_t ci_ts;
569 /* Tx packet pacing structure. */
570 struct mlx5_dev_txpp {
571 pthread_mutex_t mutex; /* Pacing create/destroy mutex. */
572 uint32_t refcnt; /* Pacing reference counter. */
573 uint32_t freq; /* Timestamp frequency, Hz. */
574 uint32_t tick; /* Completion tick duration in nanoseconds. */
575 uint32_t test; /* Packet pacing test mode. */
576 int32_t skew; /* Scheduling skew. */
577 struct rte_intr_handle intr_handle; /* Periodic interrupt. */
578 void *echan; /* Event Channel. */
579 struct mlx5_txpp_wq clock_queue; /* Clock Queue. */
580 struct mlx5_txpp_wq rearm_queue; /* Clock Queue. */
581 void *pp; /* Packet pacing context. */
582 uint16_t pp_id; /* Packet pacing context index. */
583 uint16_t ts_n; /* Number of captured timestamps. */
584 uint16_t ts_p; /* Pointer to statisticks timestamp. */
585 struct mlx5_txpp_ts *tsa; /* Timestamps sliding window stats. */
586 struct mlx5_txpp_ts ts; /* Cached completion id/timestamp. */
587 uint32_t sync_lost:1; /* ci/timestamp synchronization lost. */
588 /* Statistics counters. */
589 rte_atomic32_t err_miss_int; /* Missed service interrupt. */
590 rte_atomic32_t err_rearm_queue; /* Rearm Queue errors. */
591 rte_atomic32_t err_clock_queue; /* Clock Queue errors. */
592 rte_atomic32_t err_ts_past; /* Timestamp in the past. */
593 rte_atomic32_t err_ts_future; /* Timestamp in the distant future. */
596 /* Supported flex parser profile ID. */
597 enum mlx5_flex_parser_profile_id {
598 MLX5_FLEX_PARSER_ECPRI_0 = 0,
599 MLX5_FLEX_PARSER_MAX = 8,
602 /* Sample ID information of flex parser structure. */
603 struct mlx5_flex_parser_profiles {
604 uint32_t num; /* Actual number of samples. */
605 uint32_t ids[8]; /* Sample IDs for this profile. */
606 uint8_t offset[8]; /* Bytes offset of each parser. */
607 void *obj; /* Flex parser node object. */
611 * Shared Infiniband device context for Master/Representors
612 * which belong to same IB device with multiple IB ports.
614 struct mlx5_dev_ctx_shared {
615 LIST_ENTRY(mlx5_dev_ctx_shared) next;
617 uint32_t devx:1; /* Opened with DV. */
618 uint32_t eqn; /* Event Queue number. */
619 uint32_t max_port; /* Maximal IB device port index. */
620 void *ctx; /* Verbs/DV/DevX context. */
621 void *pd; /* Protection Domain. */
622 uint32_t pdn; /* Protection Domain number. */
623 uint32_t tdn; /* Transport Domain number. */
624 char ibdev_name[DEV_SYSFS_NAME_MAX]; /* SYSFS dev name. */
625 char ibdev_path[DEV_SYSFS_PATH_MAX]; /* SYSFS dev path for secondary */
626 struct mlx5_dev_attr device_attr; /* Device properties. */
627 int numa_node; /* Numa node of backing physical device. */
628 LIST_ENTRY(mlx5_dev_ctx_shared) mem_event_cb;
629 /**< Called by memory event callback. */
630 struct mlx5_mr_share_cache share_cache;
631 /* Packet pacing related structure. */
632 struct mlx5_dev_txpp txpp;
633 /* Shared DV/DR flow data section. */
634 pthread_mutex_t dv_mutex; /* DV context mutex. */
635 uint32_t dv_meta_mask; /* flow META metadata supported mask. */
636 uint32_t dv_mark_mask; /* flow MARK metadata supported mask. */
637 uint32_t dv_regc0_mask; /* available bits of metatada reg_c[0]. */
638 uint32_t dv_refcnt; /* DV/DR data reference counter. */
639 void *fdb_domain; /* FDB Direct Rules name space handle. */
640 void *rx_domain; /* RX Direct Rules name space handle. */
641 void *tx_domain; /* TX Direct Rules name space handle. */
643 rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */
644 rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX];
645 /* UAR same-page access control required in 32bit implementations. */
647 struct mlx5_hlist *flow_tbls;
648 /* Direct Rules tables for FDB, NIC TX+RX */
649 void *esw_drop_action; /* Pointer to DR E-Switch drop action. */
650 void *pop_vlan_action; /* Pointer to DR pop VLAN action. */
651 struct mlx5_hlist *encaps_decaps; /* Encap/decap action hash list. */
652 struct mlx5_hlist *modify_cmds;
653 struct mlx5_hlist *tag_table;
654 uint32_t port_id_action_list; /* List of port ID actions. */
655 uint32_t push_vlan_action_list; /* List of push VLAN actions. */
656 uint32_t sample_action_list; /* List of sample actions. */
657 uint32_t dest_array_list; /* List of destination array actions. */
658 struct mlx5_flow_counter_mng cmng; /* Counters management structure. */
659 struct mlx5_flow_default_miss_resource default_miss;
660 /* Default miss action resource structure. */
661 struct mlx5_indexed_pool *ipool[MLX5_IPOOL_MAX];
662 /* Memory Pool for mlx5 flow resources. */
663 struct mlx5_l3t_tbl *cnt_id_tbl; /* Shared counter lookup table. */
664 /* Shared interrupt handler section. */
665 struct rte_intr_handle intr_handle; /* Interrupt handler for device. */
666 struct rte_intr_handle intr_handle_devx; /* DEVX interrupt handler. */
667 void *devx_comp; /* DEVX async comp obj. */
668 struct mlx5_devx_obj *tis; /* TIS object. */
669 struct mlx5_devx_obj *td; /* Transport domain. */
670 struct mlx5_flow_id_pool *flow_id_pool; /* Flow ID pool. */
671 void *tx_uar; /* Tx/packet pacing shared UAR. */
672 struct mlx5_flex_parser_profiles fp[MLX5_FLEX_PARSER_MAX];
673 /* Flex parser profiles information. */
674 void *devx_rx_uar; /* DevX UAR for Rx. */
675 struct mlx5_dev_shared_port port[]; /* per device port data array. */
678 /* Per-process private structure. */
679 struct mlx5_proc_priv {
681 /* Size of UAR register table. */
683 /* Table of UAR registers for each process. */
686 /* MTR profile list. */
687 TAILQ_HEAD(mlx5_mtr_profiles, mlx5_flow_meter_profile);
689 TAILQ_HEAD(mlx5_flow_meters, mlx5_flow_meter);
691 #define MLX5_PROC_PRIV(port_id) \
692 ((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private)
694 /* Verbs/DevX Rx queue elements. */
695 struct mlx5_rxq_obj {
696 LIST_ENTRY(mlx5_rxq_obj) next; /* Pointer to the next element. */
697 struct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */
698 int fd; /* File descriptor for event channel */
702 void *wq; /* Work Queue. */
703 void *ibv_cq; /* Completion Queue. */
707 struct mlx5_devx_obj *rq; /* DevX Rx Queue object. */
708 struct mlx5_devx_obj *devx_cq; /* DevX CQ object. */
714 /* Indirection table. */
715 struct mlx5_ind_table_obj {
716 LIST_ENTRY(mlx5_ind_table_obj) next; /* Pointer to the next element. */
717 rte_atomic32_t refcnt; /* Reference counter. */
720 void *ind_table; /**< Indirection table. */
721 struct mlx5_devx_obj *rqt; /* DevX RQT object. */
723 uint32_t queues_n; /**< Number of queues in the list. */
724 uint16_t queues[]; /**< Queue list. */
729 ILIST_ENTRY(uint32_t)next; /* Index to the next element. */
730 rte_atomic32_t refcnt; /* Reference counter. */
731 struct mlx5_ind_table_obj *ind_table; /* Indirection table. */
734 void *qp; /* Verbs queue pair. */
735 struct mlx5_devx_obj *tir; /* DevX TIR object. */
737 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
738 void *action; /* DV QP action pointer. */
740 uint64_t hash_fields; /* Verbs Hash fields. */
741 uint32_t rss_key_len; /* Hash key length in bytes. */
742 uint8_t rss_key[]; /* Hash key. */
745 /* Verbs/DevX Tx queue elements. */
746 struct mlx5_txq_obj {
747 LIST_ENTRY(mlx5_txq_obj) next; /* Pointer to the next element. */
748 struct mlx5_txq_ctrl *txq_ctrl; /* Pointer to the control queue. */
752 void *cq; /* Completion Queue. */
753 void *qp; /* Queue Pair. */
756 struct mlx5_devx_obj *sq;
757 /* DevX object for Sx queue. */
758 struct mlx5_devx_obj *tis; /* The TIS object. */
761 struct rte_eth_dev *dev;
762 struct mlx5_devx_obj *cq_devx;
765 int64_t cq_dbrec_offset;
766 struct mlx5_devx_dbr_page *cq_dbrec_page;
767 struct mlx5_devx_obj *sq_devx;
770 int64_t sq_dbrec_offset;
771 struct mlx5_devx_dbr_page *sq_dbrec_page;
776 enum mlx5_rxq_modify_type {
777 MLX5_RXQ_MOD_ERR2RST, /* modify state from error to reset. */
778 MLX5_RXQ_MOD_RST2RDY, /* modify state from reset to ready. */
779 MLX5_RXQ_MOD_RDY2ERR, /* modify state from ready to error. */
780 MLX5_RXQ_MOD_RDY2RST, /* modify state from ready to reset. */
783 enum mlx5_txq_modify_type {
784 MLX5_TXQ_MOD_RDY2RDY, /* modify state from ready to ready. */
785 MLX5_TXQ_MOD_RST2RDY, /* modify state from reset to ready. */
786 MLX5_TXQ_MOD_RDY2RST, /* modify state from ready to reset. */
787 MLX5_TXQ_MOD_ERR2RDY, /* modify state from error to ready. */
790 /* HW objects operations structure. */
791 struct mlx5_obj_ops {
792 int (*rxq_obj_modify_vlan_strip)(struct mlx5_rxq_obj *rxq_obj, int on);
793 int (*rxq_obj_new)(struct rte_eth_dev *dev, uint16_t idx);
794 int (*rxq_event_get)(struct mlx5_rxq_obj *rxq_obj);
795 int (*rxq_obj_modify)(struct mlx5_rxq_obj *rxq_obj, uint8_t type);
796 void (*rxq_obj_release)(struct mlx5_rxq_obj *rxq_obj);
797 int (*ind_table_new)(struct rte_eth_dev *dev, const unsigned int log_n,
798 struct mlx5_ind_table_obj *ind_tbl);
799 void (*ind_table_destroy)(struct mlx5_ind_table_obj *ind_tbl);
800 int (*hrxq_new)(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq,
801 int tunnel __rte_unused);
802 void (*hrxq_destroy)(struct mlx5_hrxq *hrxq);
803 int (*drop_action_create)(struct rte_eth_dev *dev);
804 void (*drop_action_destroy)(struct rte_eth_dev *dev);
805 int (*txq_obj_new)(struct rte_eth_dev *dev, uint16_t idx);
806 int (*txq_obj_modify)(struct mlx5_txq_obj *obj,
807 enum mlx5_txq_modify_type type, uint8_t dev_port);
808 void (*txq_obj_release)(struct mlx5_txq_obj *txq_obj);
812 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */
813 struct mlx5_dev_ctx_shared *sh; /* Shared device context. */
814 uint32_t dev_port; /* Device port number. */
815 struct rte_pci_device *pci_dev; /* Backend PCI device. */
816 struct rte_ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */
817 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES);
818 /* Bit-field of MAC addresses owned by the PMD. */
819 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */
820 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */
821 /* Device properties. */
822 uint16_t mtu; /* Configured MTU. */
823 unsigned int isolated:1; /* Whether isolated mode is enabled. */
824 unsigned int representor:1; /* Device is a port representor. */
825 unsigned int master:1; /* Device is a E-Switch master. */
826 unsigned int dr_shared:1; /* DV/DR data is shared. */
827 unsigned int txpp_en:1; /* Tx packet pacing enabled. */
828 unsigned int mtr_en:1; /* Whether support meter. */
829 unsigned int mtr_reg_share:1; /* Whether support meter REG_C share. */
830 unsigned int sampler_en:1; /* Whether support sampler. */
831 uint16_t domain_id; /* Switch domain identifier. */
832 uint16_t vport_id; /* Associated VF vport index (if any). */
833 uint32_t vport_meta_tag; /* Used for vport index match ove VF LAG. */
834 uint32_t vport_meta_mask; /* Used for vport index field match mask. */
835 int32_t representor_id; /* Port representor identifier. */
836 int32_t pf_bond; /* >=0 means PF index in bonding configuration. */
837 unsigned int if_index; /* Associated kernel network device index. */
838 uint32_t bond_ifindex; /**< Bond interface index. */
839 char bond_name[IF_NAMESIZE]; /**< Bond interface name. */
841 unsigned int rxqs_n; /* RX queues array size. */
842 unsigned int txqs_n; /* TX queues array size. */
843 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */
844 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */
845 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
846 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */
847 unsigned int (*reta_idx)[]; /* RETA index table. */
848 unsigned int reta_idx_n; /* RETA index size. */
849 struct mlx5_drop drop_queue; /* Flow drop queues. */
850 uint32_t flows; /* RTE Flow rules. */
851 uint32_t ctrl_flows; /* Control flow rules. */
852 void *inter_flows; /* Intermediate resources for flow creation. */
853 void *rss_desc; /* Intermediate rss description resources. */
854 int flow_idx; /* Intermediate device flow index. */
855 int flow_nested_idx; /* Intermediate device flow index, nested. */
856 struct mlx5_obj_ops obj_ops; /* HW objects operations. */
857 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */
858 LIST_HEAD(rxqobj, mlx5_rxq_obj) rxqsobj; /* Verbs/DevX Rx queues. */
859 uint32_t hrxqs; /* Verbs Hash Rx queues. */
860 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */
861 LIST_HEAD(txqobj, mlx5_txq_obj) txqsobj; /* Verbs/DevX Tx queues. */
862 /* Indirection tables. */
863 LIST_HEAD(ind_tables, mlx5_ind_table_obj) ind_tbls;
864 /* Pointer to next element. */
865 rte_atomic32_t refcnt; /**< Reference counter. */
866 /**< Verbs modify header action object. */
867 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
868 uint8_t max_lro_msg_size;
869 /* Tags resources cache. */
870 uint32_t link_speed_capa; /* Link speed capabilities. */
871 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */
872 struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */
873 struct mlx5_dev_config config; /* Device configuration. */
874 struct mlx5_verbs_alloc_ctx verbs_alloc_ctx;
875 /* Context for Verbs allocator. */
876 int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */
877 int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */
878 struct mlx5_dbr_page_list dbrpgs; /* Door-bell pages. */
879 struct mlx5_nl_vlan_vmwa_context *vmwa_context; /* VLAN WA context. */
880 struct mlx5_flow_id_pool *qrss_id_pool;
881 struct mlx5_hlist *mreg_cp_tbl;
882 /* Hash table of Rx metadata register copy table. */
883 uint8_t mtr_sfx_reg; /* Meter prefix-suffix flow match REG_C. */
884 uint8_t mtr_color_reg; /* Meter color match REG_C. */
885 struct mlx5_mtr_profiles flow_meter_profiles; /* MTR profile list. */
886 struct mlx5_flow_meters flow_meters; /* MTR list. */
887 uint8_t skip_default_rss_reta; /* Skip configuration of default reta. */
888 uint8_t fdb_def_rule; /* Whether fdb jump to table 1 is configured. */
889 struct mlx5_mp_id mp_id; /* ID of a multi-process process */
890 LIST_HEAD(fdir, mlx5_fdir_flow) fdir_flows; /* fdir flows. */
893 #define PORT_ID(priv) ((priv)->dev_data->port_id)
894 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)])
898 int mlx5_getenv_int(const char *);
899 int mlx5_proc_priv_init(struct rte_eth_dev *dev);
900 int mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev,
901 struct rte_eth_udp_tunnel *udp_tunnel);
902 uint16_t mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev);
903 int mlx5_dev_close(struct rte_eth_dev *dev);
905 /* Macro to iterate over all valid ports for mlx5 driver. */
906 #define MLX5_ETH_FOREACH_DEV(port_id, pci_dev) \
907 for (port_id = mlx5_eth_find_next(0, pci_dev); \
908 port_id < RTE_MAX_ETHPORTS; \
909 port_id = mlx5_eth_find_next(port_id + 1, pci_dev))
910 int mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs);
911 struct mlx5_dev_ctx_shared *
912 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
913 const struct mlx5_dev_config *config);
914 void mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh);
915 void mlx5_free_table_hash_list(struct mlx5_priv *priv);
916 int mlx5_alloc_table_hash_list(struct mlx5_priv *priv);
917 void mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
918 struct mlx5_dev_config *config);
919 void mlx5_set_metadata_mask(struct rte_eth_dev *dev);
920 int mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
921 struct mlx5_dev_config *config);
922 int mlx5_dev_configure(struct rte_eth_dev *dev);
923 int mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info);
924 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size);
925 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
926 int mlx5_hairpin_cap_get(struct rte_eth_dev *dev,
927 struct rte_eth_hairpin_cap *cap);
928 bool mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev);
929 int mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev);
933 int mlx5_dev_configure(struct rte_eth_dev *dev);
934 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver,
936 int mlx5_dev_infos_get(struct rte_eth_dev *dev,
937 struct rte_eth_dev_info *info);
938 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev);
939 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
940 int mlx5_hairpin_cap_get(struct rte_eth_dev *dev,
941 struct rte_eth_hairpin_cap *cap);
942 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev);
943 struct mlx5_priv *mlx5_port_to_eswitch_info(uint16_t port, bool valid);
944 struct mlx5_priv *mlx5_dev_to_eswitch_info(struct rte_eth_dev *dev);
945 int mlx5_dev_configure_rss_reta(struct rte_eth_dev *dev);
947 /* mlx5_ethdev_os.c */
949 unsigned int mlx5_ifindex(const struct rte_eth_dev *dev);
950 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]);
951 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu);
952 int mlx5_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
953 int mlx5_read_clock(struct rte_eth_dev *dev, uint64_t *clock);
954 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete);
955 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev,
956 struct rte_eth_fc_conf *fc_conf);
957 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev,
958 struct rte_eth_fc_conf *fc_conf);
959 void mlx5_dev_interrupt_handler(void *arg);
960 void mlx5_dev_interrupt_handler_devx(void *arg);
961 int mlx5_set_link_down(struct rte_eth_dev *dev);
962 int mlx5_set_link_up(struct rte_eth_dev *dev);
963 int mlx5_is_removed(struct rte_eth_dev *dev);
964 int mlx5_sysfs_switch_info(unsigned int ifindex,
965 struct mlx5_switch_info *info);
966 void mlx5_translate_port_name(const char *port_name_in,
967 struct mlx5_switch_info *port_info_out);
968 void mlx5_intr_callback_unregister(const struct rte_intr_handle *handle,
969 rte_intr_callback_fn cb_fn, void *cb_arg);
970 int mlx5_sysfs_bond_info(unsigned int pf_ifindex, unsigned int *ifindex,
972 int mlx5_get_module_info(struct rte_eth_dev *dev,
973 struct rte_eth_dev_module_info *modinfo);
974 int mlx5_get_module_eeprom(struct rte_eth_dev *dev,
975 struct rte_dev_eeprom_info *info);
976 int mlx5_os_read_dev_stat(struct mlx5_priv *priv,
977 const char *ctr_name, uint64_t *stat);
978 int mlx5_os_read_dev_counters(struct rte_eth_dev *dev, uint64_t *stats);
979 int mlx5_os_get_stats_n(struct rte_eth_dev *dev);
980 void mlx5_os_stats_init(struct rte_eth_dev *dev);
984 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
985 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
986 uint32_t index, uint32_t vmdq);
987 int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr);
988 int mlx5_set_mc_addr_list(struct rte_eth_dev *dev,
989 struct rte_ether_addr *mc_addr_set,
990 uint32_t nb_mc_addr);
994 int mlx5_rss_hash_update(struct rte_eth_dev *dev,
995 struct rte_eth_rss_conf *rss_conf);
996 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev,
997 struct rte_eth_rss_conf *rss_conf);
998 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size);
999 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev,
1000 struct rte_eth_rss_reta_entry64 *reta_conf,
1001 uint16_t reta_size);
1002 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev,
1003 struct rte_eth_rss_reta_entry64 *reta_conf,
1004 uint16_t reta_size);
1008 int mlx5_promiscuous_enable(struct rte_eth_dev *dev);
1009 int mlx5_promiscuous_disable(struct rte_eth_dev *dev);
1010 int mlx5_allmulticast_enable(struct rte_eth_dev *dev);
1011 int mlx5_allmulticast_disable(struct rte_eth_dev *dev);
1015 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
1016 int mlx5_stats_reset(struct rte_eth_dev *dev);
1017 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats,
1019 int mlx5_xstats_reset(struct rte_eth_dev *dev);
1020 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
1021 struct rte_eth_xstat_name *xstats_names,
1026 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
1027 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on);
1028 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask);
1030 /* mlx5_vlan_os.c */
1032 void mlx5_vlan_vmwa_exit(void *ctx);
1033 void mlx5_vlan_vmwa_release(struct rte_eth_dev *dev,
1034 struct mlx5_vf_vlan *vf_vlan);
1035 void mlx5_vlan_vmwa_acquire(struct rte_eth_dev *dev,
1036 struct mlx5_vf_vlan *vf_vlan);
1037 void *mlx5_vlan_vmwa_init(struct rte_eth_dev *dev, uint32_t ifindex);
1039 /* mlx5_trigger.c */
1041 int mlx5_dev_start(struct rte_eth_dev *dev);
1042 int mlx5_dev_stop(struct rte_eth_dev *dev);
1043 int mlx5_traffic_enable(struct rte_eth_dev *dev);
1044 void mlx5_traffic_disable(struct rte_eth_dev *dev);
1045 int mlx5_traffic_restart(struct rte_eth_dev *dev);
1049 int mlx5_flow_discover_mreg_c(struct rte_eth_dev *eth_dev);
1050 bool mlx5_flow_ext_mreg_supported(struct rte_eth_dev *dev);
1051 void mlx5_flow_print(struct rte_flow *flow);
1052 int mlx5_flow_validate(struct rte_eth_dev *dev,
1053 const struct rte_flow_attr *attr,
1054 const struct rte_flow_item items[],
1055 const struct rte_flow_action actions[],
1056 struct rte_flow_error *error);
1057 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev,
1058 const struct rte_flow_attr *attr,
1059 const struct rte_flow_item items[],
1060 const struct rte_flow_action actions[],
1061 struct rte_flow_error *error);
1062 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow,
1063 struct rte_flow_error *error);
1064 void mlx5_flow_list_flush(struct rte_eth_dev *dev, uint32_t *list, bool active);
1065 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error);
1066 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow,
1067 const struct rte_flow_action *action, void *data,
1068 struct rte_flow_error *error);
1069 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable,
1070 struct rte_flow_error *error);
1071 int mlx5_dev_filter_ctrl(struct rte_eth_dev *dev,
1072 enum rte_filter_type filter_type,
1073 enum rte_filter_op filter_op,
1075 int mlx5_flow_start(struct rte_eth_dev *dev, uint32_t *list);
1076 void mlx5_flow_stop(struct rte_eth_dev *dev, uint32_t *list);
1077 int mlx5_flow_start_default(struct rte_eth_dev *dev);
1078 void mlx5_flow_stop_default(struct rte_eth_dev *dev);
1079 void mlx5_flow_alloc_intermediate(struct rte_eth_dev *dev);
1080 void mlx5_flow_free_intermediate(struct rte_eth_dev *dev);
1081 int mlx5_flow_verify(struct rte_eth_dev *dev);
1082 int mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, uint32_t queue);
1083 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev,
1084 struct rte_flow_item_eth *eth_spec,
1085 struct rte_flow_item_eth *eth_mask,
1086 struct rte_flow_item_vlan *vlan_spec,
1087 struct rte_flow_item_vlan *vlan_mask);
1088 int mlx5_ctrl_flow(struct rte_eth_dev *dev,
1089 struct rte_flow_item_eth *eth_spec,
1090 struct rte_flow_item_eth *eth_mask);
1091 int mlx5_flow_lacp_miss(struct rte_eth_dev *dev);
1092 struct rte_flow *mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev);
1093 int mlx5_flow_create_drop_queue(struct rte_eth_dev *dev);
1094 void mlx5_flow_delete_drop_queue(struct rte_eth_dev *dev);
1095 void mlx5_flow_async_pool_query_handle(struct mlx5_dev_ctx_shared *sh,
1096 uint64_t async_id, int status);
1097 void mlx5_set_query_alarm(struct mlx5_dev_ctx_shared *sh);
1098 void mlx5_flow_query_alarm(void *arg);
1099 uint32_t mlx5_counter_alloc(struct rte_eth_dev *dev);
1100 void mlx5_counter_free(struct rte_eth_dev *dev, uint32_t cnt);
1101 int mlx5_counter_query(struct rte_eth_dev *dev, uint32_t cnt,
1102 bool clear, uint64_t *pkts, uint64_t *bytes);
1103 int mlx5_flow_dev_dump(struct rte_eth_dev *dev, FILE *file,
1104 struct rte_flow_error *error);
1105 void mlx5_flow_rxq_dynf_metadata_set(struct rte_eth_dev *dev);
1106 int mlx5_flow_get_aged_flows(struct rte_eth_dev *dev, void **contexts,
1107 uint32_t nb_contexts, struct rte_flow_error *error);
1111 int mlx5_mp_os_primary_handle(const struct rte_mp_msg *mp_msg,
1113 int mlx5_mp_os_secondary_handle(const struct rte_mp_msg *mp_msg,
1115 void mlx5_mp_os_req_start_rxtx(struct rte_eth_dev *dev);
1116 void mlx5_mp_os_req_stop_rxtx(struct rte_eth_dev *dev);
1117 int mlx5_mp_os_req_queue_control(struct rte_eth_dev *dev, uint16_t queue_id,
1118 enum mlx5_mp_req_type req_type);
1122 int mlx5_pmd_socket_init(void);
1124 /* mlx5_flow_meter.c */
1126 int mlx5_flow_meter_ops_get(struct rte_eth_dev *dev, void *arg);
1127 struct mlx5_flow_meter *mlx5_flow_meter_find(struct mlx5_priv *priv,
1129 struct mlx5_flow_meter *mlx5_flow_meter_attach
1130 (struct mlx5_priv *priv,
1132 const struct rte_flow_attr *attr,
1133 struct rte_flow_error *error);
1134 void mlx5_flow_meter_detach(struct mlx5_flow_meter *fm);
1137 struct rte_pci_driver;
1138 int mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *dev_attr);
1139 void mlx5_os_free_shared_dr(struct mlx5_priv *priv);
1140 int mlx5_os_open_device(const struct mlx5_dev_spawn_data *spawn,
1141 const struct mlx5_dev_config *config,
1142 struct mlx5_dev_ctx_shared *sh);
1143 int mlx5_os_get_pdn(void *pd, uint32_t *pdn);
1144 int mlx5_os_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1145 struct rte_pci_device *pci_dev);
1146 void mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh);
1147 void mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh);
1148 void mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb,
1149 mlx5_dereg_mr_t *dereg_mr_cb);
1150 void mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
1151 int mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
1153 int mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv, unsigned int iface_idx,
1154 struct rte_ether_addr *mac_addr,
1156 int mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable);
1157 int mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable);
1158 int mlx5_os_set_nonblock_channel_fd(int fd);
1159 void mlx5_os_mac_addr_flush(struct rte_eth_dev *dev);
1163 int mlx5_txpp_start(struct rte_eth_dev *dev);
1164 void mlx5_txpp_stop(struct rte_eth_dev *dev);
1165 int mlx5_txpp_read_clock(struct rte_eth_dev *dev, uint64_t *timestamp);
1166 int mlx5_txpp_xstats_get(struct rte_eth_dev *dev,
1167 struct rte_eth_xstat *stats,
1168 unsigned int n, unsigned int n_used);
1169 int mlx5_txpp_xstats_reset(struct rte_eth_dev *dev);
1170 int mlx5_txpp_xstats_get_names(struct rte_eth_dev *dev,
1171 struct rte_eth_xstat_name *xstats_names,
1172 unsigned int n, unsigned int n_used);
1173 void mlx5_txpp_interrupt_handler(void *cb_arg);
1177 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev);
1179 #endif /* RTE_PMD_MLX5_H_ */