1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_H_
7 #define RTE_PMD_MLX5_H_
13 #include <netinet/in.h>
14 #include <sys/queue.h>
17 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
19 #pragma GCC diagnostic ignored "-Wpedantic"
21 #include <infiniband/verbs.h>
23 #pragma GCC diagnostic error "-Wpedantic"
27 #include <rte_ether.h>
28 #include <rte_ethdev_driver.h>
29 #include <rte_rwlock.h>
30 #include <rte_interrupts.h>
31 #include <rte_errno.h>
34 #include "mlx5_utils.h"
36 #include "mlx5_autoconf.h"
37 #include "mlx5_defs.h"
40 PCI_VENDOR_ID_MELLANOX = 0x15b3,
44 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013,
45 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014,
46 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015,
47 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016,
48 PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017,
49 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018,
50 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019,
51 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a,
52 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF = 0xa2d2,
53 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF = 0xa2d3,
54 PCI_DEVICE_ID_MELLANOX_CONNECTX6 = 0x101b,
55 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF = 0x101c,
58 /* Request types for IPC. */
59 enum mlx5_mp_req_type {
60 MLX5_MP_REQ_VERBS_CMD_FD = 1,
61 MLX5_MP_REQ_CREATE_MR,
62 MLX5_MP_REQ_START_RXTX,
63 MLX5_MP_REQ_STOP_RXTX,
66 /* Pameters for IPC. */
67 struct mlx5_mp_param {
68 enum mlx5_mp_req_type type;
73 uintptr_t addr; /* MLX5_MP_REQ_CREATE_MR */
77 /** Request timeout for IPC. */
78 #define MLX5_MP_REQ_TIMEOUT_SEC 5
80 /** Key string for IPC. */
81 #define MLX5_MP_NAME "net_mlx5_mp"
83 /* Recognized Infiniband device physical port name types. */
84 enum mlx5_phys_port_name_type {
85 MLX5_PHYS_PORT_NAME_TYPE_NOTSET = 0, /* Not set. */
86 MLX5_PHYS_PORT_NAME_TYPE_LEGACY, /* before kernel ver < 5.0 */
87 MLX5_PHYS_PORT_NAME_TYPE_UPLINK, /* p0, kernel ver >= 5.0 */
88 MLX5_PHYS_PORT_NAME_TYPE_PFVF, /* pf0vf0, kernel ver >= 5.0 */
89 MLX5_PHYS_PORT_NAME_TYPE_UNKNOWN, /* Unrecognized. */
92 /** Switch information returned by mlx5_nl_switch_info(). */
93 struct mlx5_switch_info {
94 uint32_t master:1; /**< Master device. */
95 uint32_t representor:1; /**< Representor device. */
96 enum mlx5_phys_port_name_type name_type; /** < Port name type. */
97 int32_t pf_num; /**< PF number (valid for pfxvfx format only). */
98 int32_t port_name; /**< Representor port name. */
99 uint64_t switch_id; /**< Switch identifier. */
102 LIST_HEAD(mlx5_dev_list, mlx5_priv);
104 /* Shared data between primary and secondary processes. */
105 struct mlx5_shared_data {
107 /* Global spinlock for primary and secondary processes. */
108 int init_done; /* Whether primary has done initialization. */
109 unsigned int secondary_cnt; /* Number of secondary processes init'd. */
110 struct mlx5_dev_list mem_event_cb_list;
111 rte_rwlock_t mem_event_rwlock;
114 /* Per-process data structure, not visible to other processes. */
115 struct mlx5_local_data {
116 int init_done; /* Whether a secondary has done initialization. */
119 extern struct mlx5_shared_data *mlx5_shared_data;
121 struct mlx5_counter_ctrl {
122 /* Name of the counter. */
123 char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE];
124 /* Name of the counter on the device table. */
125 char ctr_name[RTE_ETH_XSTATS_NAME_SIZE];
126 uint32_t ib:1; /**< Nonzero for IB counters. */
129 struct mlx5_xstats_ctrl {
130 /* Number of device stats. */
132 /* Number of device stats identified by PMD. */
133 uint16_t mlx5_stats_n;
134 /* Index in the device counters table. */
135 uint16_t dev_table_idx[MLX5_MAX_XSTATS];
136 uint64_t base[MLX5_MAX_XSTATS];
137 struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS];
140 struct mlx5_stats_ctrl {
141 /* Base for imissed counter. */
142 uint64_t imissed_base;
145 /* devx counter object */
146 struct mlx5_devx_counter_set {
147 struct mlx5dv_devx_obj *obj;
148 int id; /* Flow counter ID */
152 TAILQ_HEAD(mlx5_flows, rte_flow);
154 /* Default PMD specific parameter value. */
155 #define MLX5_ARG_UNSET (-1)
158 * Device configuration structure.
160 * Merged configuration from:
162 * - Device capabilities,
163 * - User device parameters disabled features.
165 struct mlx5_dev_config {
166 unsigned int hw_csum:1; /* Checksum offload is supported. */
167 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */
168 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */
169 unsigned int hw_padding:1; /* End alignment padding is supported. */
170 unsigned int vf:1; /* This is a VF. */
171 unsigned int tunnel_en:1;
172 /* Whether tunnel stateless offloads are supported. */
173 unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */
174 unsigned int cqe_comp:1; /* CQE compression is enabled. */
175 unsigned int cqe_pad:1; /* CQE padding is enabled. */
176 unsigned int tso:1; /* Whether TSO is supported. */
177 unsigned int tx_vec_en:1; /* Tx vector is enabled. */
178 unsigned int rx_vec_en:1; /* Rx vector is enabled. */
179 unsigned int mpw_hdr_dseg:1; /* Enable DSEGs in the title WQEBB. */
180 unsigned int mr_ext_memseg_en:1;
181 /* Whether memseg should be extended for MR creation. */
182 unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */
183 unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */
184 unsigned int dv_flow_en:1; /* Enable DV flow. */
185 unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */
186 unsigned int devx:1; /* Whether devx interface is available or not. */
188 unsigned int enabled:1; /* Whether MPRQ is enabled. */
189 unsigned int stride_num_n; /* Number of strides. */
190 unsigned int min_stride_size_n; /* Min size of a stride. */
191 unsigned int max_stride_size_n; /* Max size of a stride. */
192 unsigned int max_memcpy_len;
193 /* Maximum packet size to memcpy Rx packets. */
194 unsigned int min_rxqs_num;
195 /* Rx queue count threshold to enable MPRQ. */
196 } mprq; /* Configurations for Multi-Packet RQ. */
197 int mps; /* Multi-packet send supported mode. */
198 unsigned int flow_prio; /* Number of flow priorities. */
199 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */
200 unsigned int ind_table_max_size; /* Maximum indirection table size. */
201 int txq_inline; /* Maximum packet size for inlining. */
202 int txqs_inline; /* Queue number threshold for inlining. */
203 int txqs_vec; /* Queue number threshold for vectorized Tx. */
204 int inline_max_packet_sz; /* Max packet size for inlining. */
208 * Type of objet being allocated.
210 enum mlx5_verbs_alloc_type {
211 MLX5_VERBS_ALLOC_TYPE_NONE,
212 MLX5_VERBS_ALLOC_TYPE_TX_QUEUE,
213 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE,
217 * Verbs allocator needs a context to know in the callback which kind of
218 * resources it is allocating.
220 struct mlx5_verbs_alloc_ctx {
221 enum mlx5_verbs_alloc_type type; /* Kind of object being allocated. */
222 const void *obj; /* Pointer to the DPDK object. */
225 LIST_HEAD(mlx5_mr_list, mlx5_mr);
227 /* Flow drop context necessary due to Verbs API. */
229 struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */
230 struct mlx5_rxq_ibv *rxq; /* Verbs Rx queue. */
233 struct mlx5_flow_tcf_context;
235 /* Per port data of shared IB device. */
236 struct mlx5_ibv_shared_port {
239 * Interrupt handler port_id. Used by shared interrupt
240 * handler to find the corresponding rte_eth device
241 * by IB port index. If value is equal or greater
242 * RTE_MAX_ETHPORTS it means there is no subhandler
243 * installed for specified IB port index.
247 /* Table structure. */
248 struct mlx5_flow_tbl_resource {
249 void *obj; /**< Pointer to DR table object. */
250 rte_atomic32_t refcnt; /**< Reference counter. */
253 #define MLX5_MAX_TABLES 1024
254 #define MLX5_GROUP_FACTOR 1
257 * Shared Infiniband device context for Master/Representors
258 * which belong to same IB device with multiple IB ports.
260 struct mlx5_ibv_shared {
261 LIST_ENTRY(mlx5_ibv_shared) next;
263 uint32_t devx:1; /* Opened with DV. */
264 uint32_t max_port; /* Maximal IB device port index. */
265 struct ibv_context *ctx; /* Verbs/DV context. */
266 struct ibv_pd *pd; /* Protection Domain. */
267 char ibdev_name[IBV_SYSFS_NAME_MAX]; /* IB device name. */
268 char ibdev_path[IBV_SYSFS_PATH_MAX]; /* IB device path for secondary */
269 struct ibv_device_attr_ex device_attr; /* Device properties. */
270 /* Shared DV/DR flow data section. */
271 pthread_mutex_t dv_mutex; /* DV context mutex. */
272 uint32_t dv_refcnt; /* DV/DR data reference counter. */
273 void *rx_ns; /* RX Direct Rules name space handle. */
274 struct mlx5_flow_tbl_resource rx_tbl[MLX5_MAX_TABLES];
275 /* RX Direct Rules tables. */
276 void *tx_ns; /* TX Direct Rules name space handle. */
277 struct mlx5_flow_tbl_resource tx_tbl[MLX5_MAX_TABLES];
278 /* TX Direct Rules tables/ */
279 LIST_HEAD(matchers, mlx5_flow_dv_matcher) matchers;
280 LIST_HEAD(encap_decap, mlx5_flow_dv_encap_decap_resource) encaps_decaps;
281 LIST_HEAD(modify_cmd, mlx5_flow_dv_modify_hdr_resource) modify_cmds;
282 LIST_HEAD(tag, mlx5_flow_dv_tag_resource) tags;
283 LIST_HEAD(jump, mlx5_flow_dv_jump_tbl_resource) jump_tbl;
284 /* Shared interrupt handler section. */
285 pthread_mutex_t intr_mutex; /* Interrupt config mutex. */
286 uint32_t intr_cnt; /* Interrupt handler reference counter. */
287 struct rte_intr_handle intr_handle; /* Interrupt handler for device. */
288 struct mlx5_ibv_shared_port port[]; /* per device port data array. */
291 /* Per-process private structure. */
292 struct mlx5_proc_priv {
294 /* Size of UAR register table. */
296 /* Table of UAR registers for each process. */
299 #define MLX5_PROC_PRIV(port_id) \
300 ((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private)
303 LIST_ENTRY(mlx5_priv) mem_event_cb;
304 /**< Called by memory event callback. */
305 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */
306 struct mlx5_ibv_shared *sh; /* Shared IB device context. */
307 uint32_t ibv_port; /* IB device port number. */
308 struct ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */
309 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES);
310 /* Bit-field of MAC addresses owned by the PMD. */
311 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */
312 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */
313 /* Device properties. */
314 uint16_t mtu; /* Configured MTU. */
315 unsigned int isolated:1; /* Whether isolated mode is enabled. */
316 unsigned int representor:1; /* Device is a port representor. */
317 unsigned int master:1; /* Device is a E-Switch master. */
318 unsigned int dr_shared:1; /* DV/DR data is shared. */
319 uint16_t domain_id; /* Switch domain identifier. */
320 uint16_t vport_id; /* Associated VF vport index (if any). */
321 int32_t representor_id; /* Port representor identifier. */
323 unsigned int rxqs_n; /* RX queues array size. */
324 unsigned int txqs_n; /* TX queues array size. */
325 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */
326 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */
327 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
328 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */
329 unsigned int (*reta_idx)[]; /* RETA index table. */
330 unsigned int reta_idx_n; /* RETA index size. */
331 struct mlx5_drop drop_queue; /* Flow drop queues. */
332 struct mlx5_flows flows; /* RTE Flow rules. */
333 struct mlx5_flows ctrl_flows; /* Control flow rules. */
334 LIST_HEAD(counters, mlx5_flow_counter) flow_counters;
337 uint32_t dev_gen; /* Generation number to flush local caches. */
338 rte_rwlock_t rwlock; /* MR Lock. */
339 struct mlx5_mr_btree cache; /* Global MR cache table. */
340 struct mlx5_mr_list mr_list; /* Registered MR list. */
341 struct mlx5_mr_list mr_free_list; /* Freed MR list. */
343 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */
344 LIST_HEAD(rxqibv, mlx5_rxq_ibv) rxqsibv; /* Verbs Rx queues. */
345 LIST_HEAD(hrxq, mlx5_hrxq) hrxqs; /* Verbs Hash Rx queues. */
346 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */
347 LIST_HEAD(txqibv, mlx5_txq_ibv) txqsibv; /* Verbs Tx queues. */
348 /* Verbs Indirection tables. */
349 LIST_HEAD(ind_tables, mlx5_ind_table_ibv) ind_tbls;
350 /* Pointer to next element. */
351 rte_atomic32_t refcnt; /**< Reference counter. */
352 struct ibv_flow_action *verbs_action;
353 /**< Verbs modify header action object. */
354 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
355 /* Tags resources cache. */
356 uint32_t link_speed_capa; /* Link speed capabilities. */
357 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */
358 struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */
359 struct mlx5_dev_config config; /* Device configuration. */
360 struct mlx5_verbs_alloc_ctx verbs_alloc_ctx;
361 /* Context for Verbs allocator. */
362 int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */
363 int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */
364 uint32_t nl_sn; /* Netlink message sequence number. */
366 rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */
367 rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX];
368 /* UAR same-page access control required in 32bit implementations. */
370 struct mlx5_flow_tcf_context *tcf_context; /* TC flower context. */
373 #define PORT_ID(priv) ((priv)->dev_data->port_id)
374 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)])
378 int mlx5_getenv_int(const char *);
379 int mlx5_proc_priv_init(struct rte_eth_dev *dev);
383 int mlx5_get_ifname(const struct rte_eth_dev *dev, char (*ifname)[IF_NAMESIZE]);
384 int mlx5_get_master_ifname(const char *ibdev_path, char (*ifname)[IF_NAMESIZE]);
385 unsigned int mlx5_ifindex(const struct rte_eth_dev *dev);
386 int mlx5_ifreq(const struct rte_eth_dev *dev, int req, struct ifreq *ifr);
387 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu);
388 int mlx5_set_flags(struct rte_eth_dev *dev, unsigned int keep,
390 int mlx5_dev_configure(struct rte_eth_dev *dev);
391 void mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info);
392 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size);
393 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev);
394 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete);
395 int mlx5_force_link_status_change(struct rte_eth_dev *dev, int status);
396 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
397 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev,
398 struct rte_eth_fc_conf *fc_conf);
399 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev,
400 struct rte_eth_fc_conf *fc_conf);
401 int mlx5_ibv_device_to_pci_addr(const struct ibv_device *device,
402 struct rte_pci_addr *pci_addr);
403 void mlx5_dev_link_status_handler(void *arg);
404 void mlx5_dev_interrupt_handler(void *arg);
405 void mlx5_dev_interrupt_handler_uninstall(struct rte_eth_dev *dev);
406 void mlx5_dev_interrupt_handler_install(struct rte_eth_dev *dev);
407 int mlx5_set_link_down(struct rte_eth_dev *dev);
408 int mlx5_set_link_up(struct rte_eth_dev *dev);
409 int mlx5_is_removed(struct rte_eth_dev *dev);
410 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev);
411 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev);
412 unsigned int mlx5_dev_to_port_id(const struct rte_device *dev,
414 unsigned int port_list_n);
415 int mlx5_sysfs_switch_info(unsigned int ifindex,
416 struct mlx5_switch_info *info);
417 void mlx5_sysfs_check_switch_info(bool device_dir,
418 struct mlx5_switch_info *switch_info);
419 void mlx5_nl_check_switch_info(bool nun_vf_set,
420 struct mlx5_switch_info *switch_info);
421 void mlx5_translate_port_name(const char *port_name_in,
422 struct mlx5_switch_info *port_info_out);
426 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[ETHER_ADDR_LEN]);
427 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
428 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac,
429 uint32_t index, uint32_t vmdq);
430 int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr);
431 int mlx5_set_mc_addr_list(struct rte_eth_dev *dev,
432 struct ether_addr *mc_addr_set, uint32_t nb_mc_addr);
436 int mlx5_rss_hash_update(struct rte_eth_dev *dev,
437 struct rte_eth_rss_conf *rss_conf);
438 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev,
439 struct rte_eth_rss_conf *rss_conf);
440 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size);
441 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev,
442 struct rte_eth_rss_reta_entry64 *reta_conf,
444 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev,
445 struct rte_eth_rss_reta_entry64 *reta_conf,
450 void mlx5_promiscuous_enable(struct rte_eth_dev *dev);
451 void mlx5_promiscuous_disable(struct rte_eth_dev *dev);
452 void mlx5_allmulticast_enable(struct rte_eth_dev *dev);
453 void mlx5_allmulticast_disable(struct rte_eth_dev *dev);
457 void mlx5_stats_init(struct rte_eth_dev *dev);
458 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
459 void mlx5_stats_reset(struct rte_eth_dev *dev);
460 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats,
462 void mlx5_xstats_reset(struct rte_eth_dev *dev);
463 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
464 struct rte_eth_xstat_name *xstats_names,
469 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
470 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on);
471 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask);
475 int mlx5_dev_start(struct rte_eth_dev *dev);
476 void mlx5_dev_stop(struct rte_eth_dev *dev);
477 int mlx5_traffic_enable(struct rte_eth_dev *dev);
478 void mlx5_traffic_disable(struct rte_eth_dev *dev);
479 int mlx5_traffic_restart(struct rte_eth_dev *dev);
483 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
484 void mlx5_flow_print(struct rte_flow *flow);
485 int mlx5_flow_validate(struct rte_eth_dev *dev,
486 const struct rte_flow_attr *attr,
487 const struct rte_flow_item items[],
488 const struct rte_flow_action actions[],
489 struct rte_flow_error *error);
490 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev,
491 const struct rte_flow_attr *attr,
492 const struct rte_flow_item items[],
493 const struct rte_flow_action actions[],
494 struct rte_flow_error *error);
495 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow,
496 struct rte_flow_error *error);
497 void mlx5_flow_list_flush(struct rte_eth_dev *dev, struct mlx5_flows *list);
498 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error);
499 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow,
500 const struct rte_flow_action *action, void *data,
501 struct rte_flow_error *error);
502 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable,
503 struct rte_flow_error *error);
504 int mlx5_dev_filter_ctrl(struct rte_eth_dev *dev,
505 enum rte_filter_type filter_type,
506 enum rte_filter_op filter_op,
508 int mlx5_flow_start(struct rte_eth_dev *dev, struct mlx5_flows *list);
509 void mlx5_flow_stop(struct rte_eth_dev *dev, struct mlx5_flows *list);
510 int mlx5_flow_verify(struct rte_eth_dev *dev);
511 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev,
512 struct rte_flow_item_eth *eth_spec,
513 struct rte_flow_item_eth *eth_mask,
514 struct rte_flow_item_vlan *vlan_spec,
515 struct rte_flow_item_vlan *vlan_mask);
516 int mlx5_ctrl_flow(struct rte_eth_dev *dev,
517 struct rte_flow_item_eth *eth_spec,
518 struct rte_flow_item_eth *eth_mask);
519 int mlx5_flow_create_drop_queue(struct rte_eth_dev *dev);
520 void mlx5_flow_delete_drop_queue(struct rte_eth_dev *dev);
523 void mlx5_mp_req_start_rxtx(struct rte_eth_dev *dev);
524 void mlx5_mp_req_stop_rxtx(struct rte_eth_dev *dev);
525 int mlx5_mp_req_mr_create(struct rte_eth_dev *dev, uintptr_t addr);
526 int mlx5_mp_req_verbs_cmd_fd(struct rte_eth_dev *dev);
527 void mlx5_mp_init_primary(void);
528 void mlx5_mp_uninit_primary(void);
529 void mlx5_mp_init_secondary(void);
530 void mlx5_mp_uninit_secondary(void);
534 int mlx5_nl_init(int protocol);
535 int mlx5_nl_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac,
537 int mlx5_nl_mac_addr_remove(struct rte_eth_dev *dev, struct ether_addr *mac,
539 void mlx5_nl_mac_addr_sync(struct rte_eth_dev *dev);
540 void mlx5_nl_mac_addr_flush(struct rte_eth_dev *dev);
541 int mlx5_nl_promisc(struct rte_eth_dev *dev, int enable);
542 int mlx5_nl_allmulti(struct rte_eth_dev *dev, int enable);
543 unsigned int mlx5_nl_portnum(int nl, const char *name);
544 unsigned int mlx5_nl_ifindex(int nl, const char *name, uint32_t pindex);
545 int mlx5_nl_switch_info(int nl, unsigned int ifindex,
546 struct mlx5_switch_info *info);
548 /* mlx5_devx_cmds.c */
550 int mlx5_devx_cmd_flow_counter_alloc(struct ibv_context *ctx,
551 struct mlx5_devx_counter_set *dcx);
552 int mlx5_devx_cmd_flow_counter_free(struct mlx5dv_devx_obj *obj);
553 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_counter_set *dcx,
555 uint64_t *pkts, uint64_t *bytes);
556 #endif /* RTE_PMD_MLX5_H_ */