1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_H_
7 #define RTE_PMD_MLX5_H_
13 #include <netinet/in.h>
14 #include <sys/queue.h>
17 #include <rte_ether.h>
18 #include <rte_ethdev_driver.h>
19 #include <rte_rwlock.h>
20 #include <rte_interrupts.h>
21 #include <rte_errno.h>
24 #include <mlx5_glue.h>
25 #include <mlx5_devx_cmds.h>
27 #include <mlx5_common_mp.h>
28 #include <mlx5_common_mr.h>
30 #include "mlx5_defs.h"
31 #include "mlx5_utils.h"
33 #include "mlx5_autoconf.h"
36 #define MLX5_SH(dev) (((struct mlx5_priv *)(dev)->data->dev_private)->sh)
38 enum mlx5_ipool_index {
39 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
40 MLX5_IPOOL_DECAP_ENCAP = 0, /* Pool for encap/decap resource. */
41 MLX5_IPOOL_PUSH_VLAN, /* Pool for push vlan resource. */
42 MLX5_IPOOL_TAG, /* Pool for tag resource. */
43 MLX5_IPOOL_PORT_ID, /* Pool for port id resource. */
44 MLX5_IPOOL_JUMP, /* Pool for jump resource. */
45 MLX5_IPOOL_SAMPLE, /* Pool for sample resource. */
46 MLX5_IPOOL_DEST_ARRAY, /* Pool for destination array resource. */
47 MLX5_IPOOL_TUNNEL_ID, /* Pool for tunnel offload context */
48 MLX5_IPOOL_TNL_TBL_ID, /* Pool for tunnel table ID. */
50 MLX5_IPOOL_MTR, /* Pool for meter resource. */
51 MLX5_IPOOL_MCP, /* Pool for metadata resource. */
52 MLX5_IPOOL_HRXQ, /* Pool for hrxq resource. */
53 MLX5_IPOOL_MLX5_FLOW, /* Pool for mlx5 flow handle. */
54 MLX5_IPOOL_RTE_FLOW, /* Pool for rte_flow. */
55 MLX5_IPOOL_RSS_EXPANTION_FLOW_ID, /* Pool for Queue/RSS flow ID. */
56 MLX5_IPOOL_RSS_SHARED_ACTIONS, /* Pool for RSS shared actions. */
61 * There are three reclaim memory mode supported.
62 * 0(none) means no memory reclaim.
63 * 1(light) means only PMD level reclaim.
64 * 2(aggressive) means both PMD and rdma-core level reclaim.
66 enum mlx5_reclaim_mem_mode {
67 MLX5_RCM_NONE, /* Don't reclaim memory. */
68 MLX5_RCM_LIGHT, /* Reclaim PMD level. */
69 MLX5_RCM_AGGR, /* Reclaim PMD and rdma-core level. */
72 /* Hash and cache list callback context. */
73 struct mlx5_flow_cb_ctx {
74 struct rte_eth_dev *dev;
75 struct rte_flow_error *error;
79 /* Device attributes used in mlx5 PMD */
80 struct mlx5_dev_attr {
81 uint64_t device_cap_flags_ex;
91 uint32_t raw_packet_caps;
92 uint32_t max_rwq_indirection_table_size;
94 uint32_t tso_supported_qpts;
97 uint32_t sw_parsing_offloads;
98 uint32_t min_single_stride_log_num_of_bytes;
99 uint32_t max_single_stride_log_num_of_bytes;
100 uint32_t min_single_wqe_log_num_of_strides;
101 uint32_t max_single_wqe_log_num_of_strides;
102 uint32_t stride_supported_qpts;
103 uint32_t tunnel_offloads_caps;
107 /** Data associated with devices to spawn. */
108 struct mlx5_dev_spawn_data {
109 uint32_t ifindex; /**< Network interface index. */
110 uint32_t max_port; /**< Device maximal port index. */
111 uint32_t phys_port; /**< Device physical port index. */
112 int pf_bond; /**< bonding device PF index. < 0 - no bonding */
113 struct mlx5_switch_info info; /**< Switch information. */
114 void *phys_dev; /**< Associated physical device. */
115 struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */
116 struct rte_pci_device *pci_dev; /**< Backend PCI device. */
119 /** Key string for IPC. */
120 #define MLX5_MP_NAME "net_mlx5_mp"
123 LIST_HEAD(mlx5_dev_list, mlx5_dev_ctx_shared);
125 /* Shared data between primary and secondary processes. */
126 struct mlx5_shared_data {
128 /* Global spinlock for primary and secondary processes. */
129 int init_done; /* Whether primary has done initialization. */
130 unsigned int secondary_cnt; /* Number of secondary processes init'd. */
131 struct mlx5_dev_list mem_event_cb_list;
132 rte_rwlock_t mem_event_rwlock;
135 /* Per-process data structure, not visible to other processes. */
136 struct mlx5_local_data {
137 int init_done; /* Whether a secondary has done initialization. */
140 extern struct mlx5_shared_data *mlx5_shared_data;
142 /* Dev ops structs */
143 extern const struct eth_dev_ops mlx5_dev_ops;
144 extern const struct eth_dev_ops mlx5_dev_sec_ops;
145 extern const struct eth_dev_ops mlx5_dev_ops_isolate;
147 struct mlx5_counter_ctrl {
148 /* Name of the counter. */
149 char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE];
150 /* Name of the counter on the device table. */
151 char ctr_name[RTE_ETH_XSTATS_NAME_SIZE];
152 uint32_t dev:1; /**< Nonzero for dev counters. */
155 struct mlx5_xstats_ctrl {
156 /* Number of device stats. */
158 /* Number of device stats identified by PMD. */
159 uint16_t mlx5_stats_n;
160 /* Index in the device counters table. */
161 uint16_t dev_table_idx[MLX5_MAX_XSTATS];
162 uint64_t base[MLX5_MAX_XSTATS];
163 uint64_t xstats[MLX5_MAX_XSTATS];
164 uint64_t hw_stats[MLX5_MAX_XSTATS];
165 struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS];
168 struct mlx5_stats_ctrl {
169 /* Base for imissed counter. */
170 uint64_t imissed_base;
174 /* Default PMD specific parameter value. */
175 #define MLX5_ARG_UNSET (-1)
177 #define MLX5_LRO_SUPPORTED(dev) \
178 (((struct mlx5_priv *)((dev)->data->dev_private))->config.lro.supported)
180 /* Maximal size of coalesced segment for LRO is set in chunks of 256 Bytes. */
181 #define MLX5_LRO_SEG_CHUNK_SIZE 256u
183 /* Maximal size of aggregated LRO packet. */
184 #define MLX5_MAX_LRO_SIZE (UINT8_MAX * MLX5_LRO_SEG_CHUNK_SIZE)
186 /* Maximal number of segments to split. */
187 #define MLX5_MAX_RXQ_NSEG (1u << MLX5_MAX_LOG_RQ_SEGS)
189 /* LRO configurations structure. */
190 struct mlx5_lro_config {
191 uint32_t supported:1; /* Whether LRO is supported. */
192 uint32_t timeout; /* User configuration. */
196 * Device configuration structure.
198 * Merged configuration from:
200 * - Device capabilities,
201 * - User device parameters disabled features.
203 struct mlx5_dev_config {
204 unsigned int hw_csum:1; /* Checksum offload is supported. */
205 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */
206 unsigned int hw_vlan_insert:1; /* VLAN insertion in WQE is supported. */
207 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */
208 unsigned int hw_padding:1; /* End alignment padding is supported. */
209 unsigned int vf:1; /* This is a VF. */
210 unsigned int tunnel_en:1;
211 /* Whether tunnel stateless offloads are supported. */
212 unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */
213 unsigned int cqe_comp:1; /* CQE compression is enabled. */
214 unsigned int cqe_comp_fmt:3; /* CQE compression format. */
215 unsigned int tso:1; /* Whether TSO is supported. */
216 unsigned int rx_vec_en:1; /* Rx vector is enabled. */
217 unsigned int mr_ext_memseg_en:1;
218 /* Whether memseg should be extended for MR creation. */
219 unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */
220 unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */
221 unsigned int dv_esw_en:1; /* Enable E-Switch DV flow. */
222 unsigned int dv_flow_en:1; /* Enable DV flow. */
223 unsigned int dv_xmeta_en:2; /* Enable extensive flow metadata. */
224 unsigned int lacp_by_user:1;
225 /* Enable user to manage LACP traffic. */
226 unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */
227 unsigned int devx:1; /* Whether devx interface is available or not. */
228 unsigned int dest_tir:1; /* Whether advanced DR API is available. */
229 unsigned int reclaim_mode:2; /* Memory reclaim mode. */
230 unsigned int rt_timestamp:1; /* realtime timestamp format. */
231 unsigned int sys_mem_en:1; /* The default memory allocator. */
232 unsigned int decap_en:1; /* Whether decap will be used or not. */
233 unsigned int dv_miss_info:1; /* restore packet after partial hw miss */
235 unsigned int enabled:1; /* Whether MPRQ is enabled. */
236 unsigned int stride_num_n; /* Number of strides. */
237 unsigned int stride_size_n; /* Size of a stride. */
238 unsigned int min_stride_size_n; /* Min size of a stride. */
239 unsigned int max_stride_size_n; /* Max size of a stride. */
240 unsigned int max_memcpy_len;
241 /* Maximum packet size to memcpy Rx packets. */
242 unsigned int min_rxqs_num;
243 /* Rx queue count threshold to enable MPRQ. */
244 } mprq; /* Configurations for Multi-Packet RQ. */
245 int mps; /* Multi-packet send supported mode. */
246 int dbnc; /* Skip doorbell register write barrier. */
247 unsigned int flow_prio; /* Number of flow priorities. */
248 enum modify_reg flow_mreg_c[MLX5_MREG_C_NUM];
249 /* Availibility of mreg_c's. */
250 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */
251 unsigned int ind_table_max_size; /* Maximum indirection table size. */
252 unsigned int max_dump_files_num; /* Maximum dump files per queue. */
253 unsigned int log_hp_size; /* Single hairpin queue data size in total. */
254 int txqs_inline; /* Queue number threshold for inlining. */
255 int txq_inline_min; /* Minimal amount of data bytes to inline. */
256 int txq_inline_max; /* Max packet size for inlining with SEND. */
257 int txq_inline_mpw; /* Max packet size for inlining with eMPW. */
258 int tx_pp; /* Timestamp scheduling granularity in nanoseconds. */
259 int tx_skew; /* Tx scheduling skew between WQE and data on wire. */
260 struct mlx5_hca_attr hca_attr; /* HCA attributes. */
261 struct mlx5_lro_config lro; /* LRO configuration. */
265 /* Structure for VF VLAN workaround. */
266 struct mlx5_vf_vlan {
271 /* Flow drop context necessary due to Verbs API. */
273 struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */
274 struct mlx5_rxq_obj *rxq; /* Rx queue object. */
277 #define MLX5_COUNTERS_PER_POOL 512
278 #define MLX5_MAX_PENDING_QUERIES 4
279 #define MLX5_CNT_CONTAINER_RESIZE 64
280 #define MLX5_CNT_SHARED_OFFSET 0x80000000
281 #define IS_SHARED_CNT(cnt) (!!((cnt) & MLX5_CNT_SHARED_OFFSET))
282 #define IS_BATCH_CNT(cnt) (((cnt) & (MLX5_CNT_SHARED_OFFSET - 1)) >= \
283 MLX5_CNT_BATCH_OFFSET)
284 #define MLX5_CNT_SIZE (sizeof(struct mlx5_flow_counter))
285 #define MLX5_AGE_SIZE (sizeof(struct mlx5_age_param))
287 #define MLX5_CNT_LEN(pool) \
289 ((pool)->is_aged ? MLX5_AGE_SIZE : 0))
290 #define MLX5_POOL_GET_CNT(pool, index) \
291 ((struct mlx5_flow_counter *) \
292 ((uint8_t *)((pool) + 1) + (index) * (MLX5_CNT_LEN(pool))))
293 #define MLX5_CNT_ARRAY_IDX(pool, cnt) \
294 ((int)(((uint8_t *)(cnt) - (uint8_t *)((pool) + 1)) / \
297 * The pool index and offset of counter in the pool array makes up the
298 * counter index. In case the counter is from pool 0 and offset 0, it
299 * should plus 1 to avoid index 0, since 0 means invalid counter index
302 #define MLX5_MAKE_CNT_IDX(pi, offset) \
303 ((pi) * MLX5_COUNTERS_PER_POOL + (offset) + 1)
304 #define MLX5_CNT_TO_AGE(cnt) \
305 ((struct mlx5_age_param *)((cnt) + 1))
307 * The maximum single counter is 0x800000 as MLX5_CNT_BATCH_OFFSET
308 * defines. The pool size is 512, pool index should never reach
311 #define POOL_IDX_INVALID UINT16_MAX
315 AGE_FREE, /* Initialized state. */
316 AGE_CANDIDATE, /* Counter assigned to flows. */
317 AGE_TMOUT, /* Timeout, wait for rte_flow_get_aged_flows and destroy. */
320 enum mlx5_counter_type {
321 MLX5_COUNTER_TYPE_ORIGIN,
322 MLX5_COUNTER_TYPE_AGE,
323 MLX5_COUNTER_TYPE_MAX,
326 /* Counter age parameter. */
327 struct mlx5_age_param {
328 uint16_t state; /**< Age state (atomically accessed). */
329 uint16_t port_id; /**< Port id of the counter. */
330 uint32_t timeout:24; /**< Aging timeout in seconds. */
331 uint32_t sec_since_last_hit;
332 /**< Time in seconds since last hit (atomically accessed). */
333 void *context; /**< Flow counter age context. */
336 struct flow_counter_stats {
341 /* Shared counters information for counters. */
342 struct mlx5_flow_counter_shared {
343 uint32_t id; /**< User counter ID. */
346 /* Shared counter configuration. */
347 struct mlx5_shared_counter_conf {
348 struct rte_eth_dev *dev; /* The device shared counter belongs to. */
349 uint32_t id; /* The shared counter ID. */
352 struct mlx5_flow_counter_pool;
353 /* Generic counters information. */
354 struct mlx5_flow_counter {
357 * User-defined counter shared info is only used during
358 * counter active time. And aging counter sharing is not
359 * supported, so active shared counter will not be chained
360 * to the aging list. For shared counter, only when it is
361 * released, the TAILQ entry memory will be used, at that
362 * time, shared memory is not used anymore.
364 * Similarly to none-batch counter dcs, since it doesn't
365 * support aging, while counter is allocated, the entry
366 * memory is not used anymore. In this case, as bytes
367 * memory is used only when counter is allocated, and
368 * entry memory is used only when counter is free. The
369 * dcs pointer can be saved to these two different place
370 * at different stage. It will eliminate the individual
371 * counter extend struct.
373 TAILQ_ENTRY(mlx5_flow_counter) next;
374 /**< Pointer to the next flow counter structure. */
376 struct mlx5_flow_counter_shared shared_info;
377 /**< Shared counter information. */
378 void *dcs_when_active;
380 * For non-batch mode, the dcs will be saved
381 * here when the counter is free.
386 uint64_t hits; /**< Reset value of hits packets. */
387 struct mlx5_flow_counter_pool *pool; /**< Counter pool. */
390 uint64_t bytes; /**< Reset value of bytes. */
393 * For non-batch mode, the dcs will be saved here
394 * when the counter is free.
397 void *action; /**< Pointer to the dv action. */
400 TAILQ_HEAD(mlx5_counters, mlx5_flow_counter);
402 /* Generic counter pool structure - query is in pool resolution. */
403 struct mlx5_flow_counter_pool {
404 TAILQ_ENTRY(mlx5_flow_counter_pool) next;
405 struct mlx5_counters counters[2]; /* Free counter list. */
406 struct mlx5_devx_obj *min_dcs;
407 /* The devx object of the minimum counter ID. */
408 uint64_t time_of_last_age_check;
409 /* System time (from rte_rdtsc()) read in the last aging check. */
410 uint32_t index:30; /* Pool index in container. */
411 uint32_t is_aged:1; /* Pool with aging counter. */
412 volatile uint32_t query_gen:1; /* Query round. */
413 rte_spinlock_t sl; /* The pool lock. */
414 rte_spinlock_t csl; /* The pool counter free list lock. */
415 struct mlx5_counter_stats_raw *raw;
416 struct mlx5_counter_stats_raw *raw_hw;
417 /* The raw on HW working. */
420 /* Memory management structure for group of counter statistics raws. */
421 struct mlx5_counter_stats_mem_mng {
422 LIST_ENTRY(mlx5_counter_stats_mem_mng) next;
423 struct mlx5_counter_stats_raw *raws;
424 struct mlx5_devx_obj *dm;
428 /* Raw memory structure for the counter statistics values of a pool. */
429 struct mlx5_counter_stats_raw {
430 LIST_ENTRY(mlx5_counter_stats_raw) next;
431 struct mlx5_counter_stats_mem_mng *mem_mng;
432 volatile struct flow_counter_stats *data;
435 TAILQ_HEAD(mlx5_counter_pools, mlx5_flow_counter_pool);
437 /* Counter global management structure. */
438 struct mlx5_flow_counter_mng {
439 volatile uint16_t n_valid; /* Number of valid pools. */
440 uint16_t n; /* Number of pools. */
441 uint16_t last_pool_idx; /* Last used pool index */
442 int min_id; /* The minimum counter ID in the pools. */
443 int max_id; /* The maximum counter ID in the pools. */
444 rte_spinlock_t pool_update_sl; /* The pool update lock. */
445 rte_spinlock_t csl[MLX5_COUNTER_TYPE_MAX];
446 /* The counter free list lock. */
447 struct mlx5_counters counters[MLX5_COUNTER_TYPE_MAX];
448 /* Free counter list. */
449 struct mlx5_flow_counter_pool **pools; /* Counter pool array. */
450 struct mlx5_counter_stats_mem_mng *mem_mng;
451 /* Hold the memory management for the next allocated pools raws. */
452 struct mlx5_counters flow_counters; /* Legacy flow counter list. */
453 uint8_t pending_queries;
455 uint8_t query_thread_on;
456 bool relaxed_ordering_read;
457 bool relaxed_ordering_write;
458 bool counter_fallback; /* Use counter fallback management. */
459 LIST_HEAD(mem_mngs, mlx5_counter_stats_mem_mng) mem_mngs;
460 LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws;
463 /* ASO structures. */
464 #define MLX5_ASO_QUEUE_LOG_DESC 10
469 struct mlx5_devx_obj *cq;
470 struct mlx5dv_devx_umem *umem_obj;
472 volatile void *umem_buf;
473 volatile struct mlx5_cqe *cqes;
475 volatile uint32_t *db_rec;
479 struct mlx5_aso_devx_mr {
482 struct mlx5dv_devx_umem *umem;
483 struct mlx5_devx_obj *mkey;
487 struct mlx5_aso_sq_elem {
488 struct mlx5_aso_age_pool *pool;
494 struct mlx5_aso_cq cq;
495 struct mlx5_devx_obj *sq;
496 struct mlx5dv_devx_umem *wqe_umem; /* SQ buffer umem. */
498 volatile void *umem_buf;
499 volatile struct mlx5_aso_wqe *wqes;
501 volatile uint32_t *db_rec;
502 volatile uint64_t *uar_addr;
503 struct mlx5_aso_devx_mr mr;
508 struct mlx5_aso_sq_elem elts[1 << MLX5_ASO_QUEUE_LOG_DESC];
509 uint16_t next; /* Pool index of the next pool to query. */
512 struct mlx5_aso_age_action {
513 LIST_ENTRY(mlx5_aso_age_action) next;
516 /* Following fields relevant only when action is active. */
517 uint16_t offset; /* Offset of ASO Flow Hit flag in DevX object. */
518 struct mlx5_age_param age_params;
521 #define MLX5_ASO_AGE_ACTIONS_PER_POOL 512
523 struct mlx5_aso_age_pool {
524 struct mlx5_devx_obj *flow_hit_aso_obj;
525 uint16_t index; /* Pool index in pools array. */
526 uint64_t time_of_last_age_check; /* In seconds. */
527 struct mlx5_aso_age_action actions[MLX5_ASO_AGE_ACTIONS_PER_POOL];
530 LIST_HEAD(aso_age_list, mlx5_aso_age_action);
532 struct mlx5_aso_age_mng {
533 struct mlx5_aso_age_pool **pools;
534 uint16_t n; /* Total number of pools. */
535 uint16_t next; /* Number of pools in use, index of next free pool. */
536 rte_spinlock_t resize_sl; /* Lock for resize objects. */
537 rte_spinlock_t free_sl; /* Lock for free list access. */
538 struct aso_age_list free; /* Free age actions list - ready to use. */
539 struct mlx5_aso_sq aso_sq; /* ASO queue objects. */
542 #define MLX5_AGE_EVENT_NEW 1
543 #define MLX5_AGE_TRIGGER 2
544 #define MLX5_AGE_SET(age_info, BIT) \
545 ((age_info)->flags |= (1 << (BIT)))
546 #define MLX5_AGE_GET(age_info, BIT) \
547 ((age_info)->flags & (1 << (BIT)))
548 #define GET_PORT_AGE_INFO(priv) \
549 (&((priv)->sh->port[(priv)->dev_port - 1].age_info))
550 /* Current time in seconds. */
551 #define MLX5_CURR_TIME_SEC (rte_rdtsc() / rte_get_tsc_hz())
553 /* Aging information for per port. */
554 struct mlx5_age_info {
555 uint8_t flags; /* Indicate if is new event or need to be triggered. */
556 struct mlx5_counters aged_counters; /* Aged counter list. */
557 struct aso_age_list aged_aso; /* Aged ASO actions list. */
558 rte_spinlock_t aged_sl; /* Aged flow list lock. */
561 /* Per port data of shared IB device. */
562 struct mlx5_dev_shared_port {
564 uint32_t devx_ih_port_id;
566 * Interrupt handler port_id. Used by shared interrupt
567 * handler to find the corresponding rte_eth device
568 * by IB port index. If value is equal or greater
569 * RTE_MAX_ETHPORTS it means there is no subhandler
570 * installed for specified IB port index.
572 struct mlx5_age_info age_info;
573 /* Aging information for per port. */
576 /* Table key of the hash organization. */
577 union mlx5_flow_tbl_key {
579 /* Table ID should be at the lowest address. */
580 uint32_t table_id; /**< ID of the table. */
581 uint16_t dummy; /**< Dummy table for DV API. */
582 uint8_t domain; /**< 1 - FDB, 0 - NIC TX/RX. */
583 uint8_t direction; /**< 1 - egress, 0 - ingress. */
585 uint64_t v64; /**< full 64bits value of key */
588 /* Table structure. */
589 struct mlx5_flow_tbl_resource {
590 void *obj; /**< Pointer to DR table object. */
591 uint32_t refcnt; /**< Reference counter. */
594 #define MLX5_MAX_TABLES UINT16_MAX
595 #define MLX5_HAIRPIN_TX_TABLE (UINT16_MAX - 1)
596 /* Reserve the last two tables for metadata register copy. */
597 #define MLX5_FLOW_MREG_ACT_TABLE_GROUP (MLX5_MAX_TABLES - 1)
598 #define MLX5_FLOW_MREG_CP_TABLE_GROUP (MLX5_MAX_TABLES - 2)
599 /* Tables for metering splits should be added here. */
600 #define MLX5_FLOW_TABLE_LEVEL_SUFFIX (MLX5_MAX_TABLES - 3)
601 #define MLX5_FLOW_TABLE_LEVEL_METER (MLX5_MAX_TABLES - 4)
602 #define MLX5_MAX_TABLES_EXTERNAL MLX5_FLOW_TABLE_LEVEL_METER
603 #define MLX5_MAX_TABLES_FDB UINT16_MAX
604 #define MLX5_FLOW_TABLE_FACTOR 10
606 /* ID generation structure. */
607 struct mlx5_flow_id_pool {
608 uint32_t *free_arr; /**< Pointer to the a array of free values. */
610 /**< The next index that can be used without any free elements. */
611 uint32_t *curr; /**< Pointer to the index to pop. */
612 uint32_t *last; /**< Pointer to the last element in the empty arrray. */
613 uint32_t max_id; /**< Maximum id can be allocated from the pool. */
616 /* Tx pacing queue structure - for Clock and Rearm queues. */
617 struct mlx5_txpp_wq {
618 /* Completion Queue related data.*/
619 struct mlx5_devx_obj *cq;
622 volatile void *cq_buf;
623 volatile struct mlx5_cqe *cqes;
625 volatile uint32_t *cq_dbrec;
628 /* Send Queue related data.*/
629 struct mlx5_devx_obj *sq;
632 volatile void *sq_buf;
633 volatile struct mlx5_wqe *wqes;
635 uint16_t sq_size; /* Number of WQEs in the queue. */
636 uint16_t sq_ci; /* Next WQE to execute. */
637 volatile uint32_t *sq_dbrec;
640 /* Tx packet pacing internal timestamp. */
641 struct mlx5_txpp_ts {
646 /* Tx packet pacing structure. */
647 struct mlx5_dev_txpp {
648 pthread_mutex_t mutex; /* Pacing create/destroy mutex. */
649 uint32_t refcnt; /* Pacing reference counter. */
650 uint32_t freq; /* Timestamp frequency, Hz. */
651 uint32_t tick; /* Completion tick duration in nanoseconds. */
652 uint32_t test; /* Packet pacing test mode. */
653 int32_t skew; /* Scheduling skew. */
654 struct rte_intr_handle intr_handle; /* Periodic interrupt. */
655 void *echan; /* Event Channel. */
656 struct mlx5_txpp_wq clock_queue; /* Clock Queue. */
657 struct mlx5_txpp_wq rearm_queue; /* Clock Queue. */
658 void *pp; /* Packet pacing context. */
659 uint16_t pp_id; /* Packet pacing context index. */
660 uint16_t ts_n; /* Number of captured timestamps. */
661 uint16_t ts_p; /* Pointer to statisticks timestamp. */
662 struct mlx5_txpp_ts *tsa; /* Timestamps sliding window stats. */
663 struct mlx5_txpp_ts ts; /* Cached completion id/timestamp. */
664 uint32_t sync_lost:1; /* ci/timestamp synchronization lost. */
665 /* Statistics counters. */
666 uint64_t err_miss_int; /* Missed service interrupt. */
667 uint64_t err_rearm_queue; /* Rearm Queue errors. */
668 uint64_t err_clock_queue; /* Clock Queue errors. */
669 uint64_t err_ts_past; /* Timestamp in the past. */
670 uint64_t err_ts_future; /* Timestamp in the distant future. */
673 /* Supported flex parser profile ID. */
674 enum mlx5_flex_parser_profile_id {
675 MLX5_FLEX_PARSER_ECPRI_0 = 0,
676 MLX5_FLEX_PARSER_MAX = 8,
679 /* Sample ID information of flex parser structure. */
680 struct mlx5_flex_parser_profiles {
681 uint32_t num; /* Actual number of samples. */
682 uint32_t ids[8]; /* Sample IDs for this profile. */
683 uint8_t offset[8]; /* Bytes offset of each parser. */
684 void *obj; /* Flex parser node object. */
688 * Shared Infiniband device context for Master/Representors
689 * which belong to same IB device with multiple IB ports.
691 struct mlx5_dev_ctx_shared {
692 LIST_ENTRY(mlx5_dev_ctx_shared) next;
694 uint16_t bond_dev; /* Bond primary device id. */
695 uint32_t devx:1; /* Opened with DV. */
696 uint32_t flow_hit_aso_en:1; /* Flow Hit ASO is supported. */
697 uint32_t eqn; /* Event Queue number. */
698 uint32_t max_port; /* Maximal IB device port index. */
699 void *ctx; /* Verbs/DV/DevX context. */
700 void *pd; /* Protection Domain. */
701 uint32_t pdn; /* Protection Domain number. */
702 uint32_t tdn; /* Transport Domain number. */
703 char ibdev_name[MLX5_FS_NAME_MAX]; /* SYSFS dev name. */
704 char ibdev_path[MLX5_FS_PATH_MAX]; /* SYSFS dev path for secondary */
705 struct mlx5_dev_attr device_attr; /* Device properties. */
706 int numa_node; /* Numa node of backing physical device. */
707 LIST_ENTRY(mlx5_dev_ctx_shared) mem_event_cb;
708 /**< Called by memory event callback. */
709 struct mlx5_mr_share_cache share_cache;
710 /* Packet pacing related structure. */
711 struct mlx5_dev_txpp txpp;
712 /* Shared DV/DR flow data section. */
713 uint32_t dv_meta_mask; /* flow META metadata supported mask. */
714 uint32_t dv_mark_mask; /* flow MARK metadata supported mask. */
715 uint32_t dv_regc0_mask; /* available bits of metatada reg_c[0]. */
716 void *fdb_domain; /* FDB Direct Rules name space handle. */
717 void *rx_domain; /* RX Direct Rules name space handle. */
718 void *tx_domain; /* TX Direct Rules name space handle. */
720 rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */
721 rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX];
722 /* UAR same-page access control required in 32bit implementations. */
724 struct mlx5_hlist *flow_tbls;
725 struct mlx5_flow_tunnel_hub *tunnel_hub;
726 /* Direct Rules tables for FDB, NIC TX+RX */
727 void *esw_drop_action; /* Pointer to DR E-Switch drop action. */
728 void *pop_vlan_action; /* Pointer to DR pop VLAN action. */
729 struct mlx5_hlist *encaps_decaps; /* Encap/decap action hash list. */
730 struct mlx5_hlist *modify_cmds;
731 struct mlx5_hlist *tag_table;
732 struct mlx5_cache_list port_id_action_list; /* Port ID action cache. */
733 struct mlx5_cache_list push_vlan_action_list; /* Push VLAN actions. */
734 struct mlx5_cache_list sample_action_list; /* List of sample actions. */
735 struct mlx5_cache_list dest_array_list;
736 /* List of destination array actions. */
737 struct mlx5_flow_counter_mng cmng; /* Counters management structure. */
738 void *default_miss_action; /* Default miss action. */
739 struct mlx5_indexed_pool *ipool[MLX5_IPOOL_MAX];
740 /* Memory Pool for mlx5 flow resources. */
741 struct mlx5_l3t_tbl *cnt_id_tbl; /* Shared counter lookup table. */
742 /* Shared interrupt handler section. */
743 struct rte_intr_handle intr_handle; /* Interrupt handler for device. */
744 struct rte_intr_handle intr_handle_devx; /* DEVX interrupt handler. */
745 void *devx_comp; /* DEVX async comp obj. */
746 struct mlx5_devx_obj *tis; /* TIS object. */
747 struct mlx5_devx_obj *td; /* Transport domain. */
748 void *tx_uar; /* Tx/packet pacing shared UAR. */
749 struct mlx5_flex_parser_profiles fp[MLX5_FLEX_PARSER_MAX];
750 /* Flex parser profiles information. */
751 void *devx_rx_uar; /* DevX UAR for Rx. */
752 struct mlx5_aso_age_mng *aso_age_mng;
753 /* Management data for aging mechanism using ASO Flow Hit. */
754 struct mlx5_dev_shared_port port[]; /* per device port data array. */
757 /* Per-process private structure. */
758 struct mlx5_proc_priv {
760 /* Size of UAR register table. */
762 /* Table of UAR registers for each process. */
765 /* MTR profile list. */
766 TAILQ_HEAD(mlx5_mtr_profiles, mlx5_flow_meter_profile);
768 TAILQ_HEAD(mlx5_flow_meters, mlx5_flow_meter);
770 /* RSS description. */
771 struct mlx5_flow_rss_desc {
773 uint32_t queue_num; /**< Number of entries in @p queue. */
774 uint64_t types; /**< Specific RSS hash types (see ETH_RSS_*). */
775 uint64_t hash_fields; /* Verbs Hash fields. */
776 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
777 uint32_t key_len; /**< RSS hash key len. */
778 uint32_t tunnel; /**< Queue in tunnel. */
779 uint32_t shared_rss; /**< Shared RSS index. */
780 struct mlx5_ind_table_obj *ind_tbl;
781 /**< Indirection table for shared RSS hash RX queues. */
783 uint16_t *queue; /**< Destination queues. */
784 const uint16_t *const_q; /**< Const pointer convert. */
788 #define MLX5_PROC_PRIV(port_id) \
789 ((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private)
791 /* Verbs/DevX Rx queue elements. */
792 struct mlx5_rxq_obj {
793 LIST_ENTRY(mlx5_rxq_obj) next; /* Pointer to the next element. */
794 struct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */
795 int fd; /* File descriptor for event channel */
799 void *wq; /* Work Queue. */
800 void *ibv_cq; /* Completion Queue. */
804 struct mlx5_devx_obj *rq; /* DevX Rx Queue object. */
805 struct mlx5_devx_obj *devx_cq; /* DevX CQ object. */
811 /* Indirection table. */
812 struct mlx5_ind_table_obj {
813 LIST_ENTRY(mlx5_ind_table_obj) next; /* Pointer to the next element. */
814 uint32_t refcnt; /* Reference counter. */
817 void *ind_table; /**< Indirection table. */
818 struct mlx5_devx_obj *rqt; /* DevX RQT object. */
820 uint32_t queues_n; /**< Number of queues in the list. */
821 uint16_t *queues; /**< Queue list. */
827 struct mlx5_cache_entry entry; /* Cache entry. */
828 uint32_t standalone:1; /* This object used in shared action. */
829 struct mlx5_ind_table_obj *ind_table; /* Indirection table. */
832 void *qp; /* Verbs queue pair. */
833 struct mlx5_devx_obj *tir; /* DevX TIR object. */
835 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
836 void *action; /* DV QP action pointer. */
838 uint64_t hash_fields; /* Verbs Hash fields. */
839 uint32_t rss_key_len; /* Hash key length in bytes. */
840 uint32_t idx; /* Hash Rx queue index. */
841 uint8_t rss_key[]; /* Hash key. */
844 /* Verbs/DevX Tx queue elements. */
845 struct mlx5_txq_obj {
846 LIST_ENTRY(mlx5_txq_obj) next; /* Pointer to the next element. */
847 struct mlx5_txq_ctrl *txq_ctrl; /* Pointer to the control queue. */
851 void *cq; /* Completion Queue. */
852 void *qp; /* Queue Pair. */
855 struct mlx5_devx_obj *sq;
856 /* DevX object for Sx queue. */
857 struct mlx5_devx_obj *tis; /* The TIS object. */
860 struct rte_eth_dev *dev;
861 struct mlx5_devx_obj *cq_devx;
864 int64_t cq_dbrec_offset;
865 struct mlx5_devx_dbr_page *cq_dbrec_page;
866 struct mlx5_devx_obj *sq_devx;
869 int64_t sq_dbrec_offset;
870 struct mlx5_devx_dbr_page *sq_dbrec_page;
875 enum mlx5_rxq_modify_type {
876 MLX5_RXQ_MOD_ERR2RST, /* modify state from error to reset. */
877 MLX5_RXQ_MOD_RST2RDY, /* modify state from reset to ready. */
878 MLX5_RXQ_MOD_RDY2ERR, /* modify state from ready to error. */
879 MLX5_RXQ_MOD_RDY2RST, /* modify state from ready to reset. */
882 enum mlx5_txq_modify_type {
883 MLX5_TXQ_MOD_RST2RDY, /* modify state from reset to ready. */
884 MLX5_TXQ_MOD_RDY2RST, /* modify state from ready to reset. */
885 MLX5_TXQ_MOD_ERR2RDY, /* modify state from error to ready. */
888 /* HW objects operations structure. */
889 struct mlx5_obj_ops {
890 int (*rxq_obj_modify_vlan_strip)(struct mlx5_rxq_obj *rxq_obj, int on);
891 int (*rxq_obj_new)(struct rte_eth_dev *dev, uint16_t idx);
892 int (*rxq_event_get)(struct mlx5_rxq_obj *rxq_obj);
893 int (*rxq_obj_modify)(struct mlx5_rxq_obj *rxq_obj, uint8_t type);
894 void (*rxq_obj_release)(struct mlx5_rxq_obj *rxq_obj);
895 int (*ind_table_new)(struct rte_eth_dev *dev, const unsigned int log_n,
896 struct mlx5_ind_table_obj *ind_tbl);
897 int (*ind_table_modify)(struct rte_eth_dev *dev,
898 const unsigned int log_n,
899 const uint16_t *queues, const uint32_t queues_n,
900 struct mlx5_ind_table_obj *ind_tbl);
901 void (*ind_table_destroy)(struct mlx5_ind_table_obj *ind_tbl);
902 int (*hrxq_new)(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq,
903 int tunnel __rte_unused);
904 int (*hrxq_modify)(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq,
905 const uint8_t *rss_key,
906 uint64_t hash_fields,
907 const struct mlx5_ind_table_obj *ind_tbl);
908 void (*hrxq_destroy)(struct mlx5_hrxq *hrxq);
909 int (*drop_action_create)(struct rte_eth_dev *dev);
910 void (*drop_action_destroy)(struct rte_eth_dev *dev);
911 int (*txq_obj_new)(struct rte_eth_dev *dev, uint16_t idx);
912 int (*txq_obj_modify)(struct mlx5_txq_obj *obj,
913 enum mlx5_txq_modify_type type, uint8_t dev_port);
914 void (*txq_obj_release)(struct mlx5_txq_obj *txq_obj);
917 #define MLX5_RSS_HASH_FIELDS_LEN RTE_DIM(mlx5_rss_hash_fields)
919 /* MR operations structure. */
921 mlx5_reg_mr_t reg_mr;
922 mlx5_dereg_mr_t dereg_mr;
926 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */
927 struct mlx5_dev_ctx_shared *sh; /* Shared device context. */
928 uint32_t dev_port; /* Device port number. */
929 struct rte_pci_device *pci_dev; /* Backend PCI device. */
930 struct rte_ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */
931 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES);
932 /* Bit-field of MAC addresses owned by the PMD. */
933 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */
934 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */
935 /* Device properties. */
936 uint16_t mtu; /* Configured MTU. */
937 unsigned int isolated:1; /* Whether isolated mode is enabled. */
938 unsigned int representor:1; /* Device is a port representor. */
939 unsigned int master:1; /* Device is a E-Switch master. */
940 unsigned int txpp_en:1; /* Tx packet pacing enabled. */
941 unsigned int mtr_en:1; /* Whether support meter. */
942 unsigned int mtr_reg_share:1; /* Whether support meter REG_C share. */
943 unsigned int sampler_en:1; /* Whether support sampler. */
944 uint16_t domain_id; /* Switch domain identifier. */
945 uint16_t vport_id; /* Associated VF vport index (if any). */
946 uint32_t vport_meta_tag; /* Used for vport index match ove VF LAG. */
947 uint32_t vport_meta_mask; /* Used for vport index field match mask. */
948 int32_t representor_id; /* Port representor identifier. */
949 int32_t pf_bond; /* >=0 means PF index in bonding configuration. */
950 unsigned int if_index; /* Associated kernel network device index. */
951 uint32_t bond_ifindex; /**< Bond interface index. */
952 char bond_name[MLX5_NAMESIZE]; /**< Bond interface name. */
954 unsigned int rxqs_n; /* RX queues array size. */
955 unsigned int txqs_n; /* TX queues array size. */
956 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */
957 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */
958 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
959 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */
960 unsigned int (*reta_idx)[]; /* RETA index table. */
961 unsigned int reta_idx_n; /* RETA index size. */
962 struct mlx5_drop drop_queue; /* Flow drop queues. */
963 uint32_t flows; /* RTE Flow rules. */
964 uint32_t ctrl_flows; /* Control flow rules. */
965 rte_spinlock_t flow_list_lock;
966 struct mlx5_obj_ops obj_ops; /* HW objects operations. */
967 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */
968 LIST_HEAD(rxqobj, mlx5_rxq_obj) rxqsobj; /* Verbs/DevX Rx queues. */
969 struct mlx5_cache_list hrxqs; /* Hash Rx queues. */
970 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */
971 LIST_HEAD(txqobj, mlx5_txq_obj) txqsobj; /* Verbs/DevX Tx queues. */
972 /* Indirection tables. */
973 LIST_HEAD(ind_tables, mlx5_ind_table_obj) ind_tbls;
974 /* Pointer to next element. */
975 uint32_t refcnt; /**< Reference counter. */
976 /**< Verbs modify header action object. */
977 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
978 uint8_t max_lro_msg_size;
979 /* Tags resources cache. */
980 uint32_t link_speed_capa; /* Link speed capabilities. */
981 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */
982 struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */
983 struct mlx5_dev_config config; /* Device configuration. */
984 /* Context for Verbs allocator. */
985 int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */
986 int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */
987 struct mlx5_dbr_page_list dbrpgs; /* Door-bell pages. */
988 struct mlx5_nl_vlan_vmwa_context *vmwa_context; /* VLAN WA context. */
989 struct mlx5_hlist *mreg_cp_tbl;
990 /* Hash table of Rx metadata register copy table. */
991 uint8_t mtr_sfx_reg; /* Meter prefix-suffix flow match REG_C. */
992 uint8_t mtr_color_reg; /* Meter color match REG_C. */
993 struct mlx5_mtr_profiles flow_meter_profiles; /* MTR profile list. */
994 struct mlx5_flow_meters flow_meters; /* MTR list. */
995 uint8_t skip_default_rss_reta; /* Skip configuration of default reta. */
996 uint8_t fdb_def_rule; /* Whether fdb jump to table 1 is configured. */
997 struct mlx5_mp_id mp_id; /* ID of a multi-process process */
998 LIST_HEAD(fdir, mlx5_fdir_flow) fdir_flows; /* fdir flows. */
999 rte_spinlock_t shared_act_sl; /* Shared actions spinlock. */
1000 uint32_t rss_shared_actions; /* RSS shared actions. */
1003 #define PORT_ID(priv) ((priv)->dev_data->port_id)
1004 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)])
1006 struct rte_hairpin_peer_info {
1010 uint16_t tx_explicit;
1011 uint16_t manual_bind;
1016 int mlx5_getenv_int(const char *);
1017 int mlx5_proc_priv_init(struct rte_eth_dev *dev);
1018 int mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev,
1019 struct rte_eth_udp_tunnel *udp_tunnel);
1020 uint16_t mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev);
1021 int mlx5_dev_close(struct rte_eth_dev *dev);
1022 void mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh);
1024 /* Macro to iterate over all valid ports for mlx5 driver. */
1025 #define MLX5_ETH_FOREACH_DEV(port_id, pci_dev) \
1026 for (port_id = mlx5_eth_find_next(0, pci_dev); \
1027 port_id < RTE_MAX_ETHPORTS; \
1028 port_id = mlx5_eth_find_next(port_id + 1, pci_dev))
1029 int mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs);
1030 struct mlx5_dev_ctx_shared *
1031 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
1032 const struct mlx5_dev_config *config);
1033 void mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh);
1034 void mlx5_free_table_hash_list(struct mlx5_priv *priv);
1035 int mlx5_alloc_table_hash_list(struct mlx5_priv *priv);
1036 void mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1037 struct mlx5_dev_config *config);
1038 void mlx5_set_metadata_mask(struct rte_eth_dev *dev);
1039 int mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
1040 struct mlx5_dev_config *config);
1041 int mlx5_dev_configure(struct rte_eth_dev *dev);
1042 int mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info);
1043 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size);
1044 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
1045 int mlx5_hairpin_cap_get(struct rte_eth_dev *dev,
1046 struct rte_eth_hairpin_cap *cap);
1047 bool mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev);
1048 int mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev);
1049 int mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh);
1053 int mlx5_dev_configure(struct rte_eth_dev *dev);
1054 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver,
1056 int mlx5_dev_infos_get(struct rte_eth_dev *dev,
1057 struct rte_eth_dev_info *info);
1058 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev);
1059 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
1060 int mlx5_hairpin_cap_get(struct rte_eth_dev *dev,
1061 struct rte_eth_hairpin_cap *cap);
1062 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev);
1063 struct mlx5_priv *mlx5_port_to_eswitch_info(uint16_t port, bool valid);
1064 struct mlx5_priv *mlx5_dev_to_eswitch_info(struct rte_eth_dev *dev);
1065 int mlx5_dev_configure_rss_reta(struct rte_eth_dev *dev);
1067 /* mlx5_ethdev_os.c */
1069 int mlx5_get_ifname(const struct rte_eth_dev *dev,
1070 char (*ifname)[MLX5_NAMESIZE]);
1071 unsigned int mlx5_ifindex(const struct rte_eth_dev *dev);
1072 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]);
1073 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu);
1074 int mlx5_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
1075 int mlx5_read_clock(struct rte_eth_dev *dev, uint64_t *clock);
1076 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete);
1077 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev,
1078 struct rte_eth_fc_conf *fc_conf);
1079 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev,
1080 struct rte_eth_fc_conf *fc_conf);
1081 void mlx5_dev_interrupt_handler(void *arg);
1082 void mlx5_dev_interrupt_handler_devx(void *arg);
1083 int mlx5_set_link_down(struct rte_eth_dev *dev);
1084 int mlx5_set_link_up(struct rte_eth_dev *dev);
1085 int mlx5_is_removed(struct rte_eth_dev *dev);
1086 int mlx5_sysfs_switch_info(unsigned int ifindex,
1087 struct mlx5_switch_info *info);
1088 void mlx5_translate_port_name(const char *port_name_in,
1089 struct mlx5_switch_info *port_info_out);
1090 void mlx5_intr_callback_unregister(const struct rte_intr_handle *handle,
1091 rte_intr_callback_fn cb_fn, void *cb_arg);
1092 int mlx5_sysfs_bond_info(unsigned int pf_ifindex, unsigned int *ifindex,
1094 int mlx5_get_module_info(struct rte_eth_dev *dev,
1095 struct rte_eth_dev_module_info *modinfo);
1096 int mlx5_get_module_eeprom(struct rte_eth_dev *dev,
1097 struct rte_dev_eeprom_info *info);
1098 int mlx5_os_read_dev_stat(struct mlx5_priv *priv,
1099 const char *ctr_name, uint64_t *stat);
1100 int mlx5_os_read_dev_counters(struct rte_eth_dev *dev, uint64_t *stats);
1101 int mlx5_os_get_stats_n(struct rte_eth_dev *dev);
1102 void mlx5_os_stats_init(struct rte_eth_dev *dev);
1106 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
1107 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
1108 uint32_t index, uint32_t vmdq);
1109 int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr);
1110 int mlx5_set_mc_addr_list(struct rte_eth_dev *dev,
1111 struct rte_ether_addr *mc_addr_set,
1112 uint32_t nb_mc_addr);
1116 int mlx5_rss_hash_update(struct rte_eth_dev *dev,
1117 struct rte_eth_rss_conf *rss_conf);
1118 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev,
1119 struct rte_eth_rss_conf *rss_conf);
1120 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size);
1121 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev,
1122 struct rte_eth_rss_reta_entry64 *reta_conf,
1123 uint16_t reta_size);
1124 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev,
1125 struct rte_eth_rss_reta_entry64 *reta_conf,
1126 uint16_t reta_size);
1130 int mlx5_promiscuous_enable(struct rte_eth_dev *dev);
1131 int mlx5_promiscuous_disable(struct rte_eth_dev *dev);
1132 int mlx5_allmulticast_enable(struct rte_eth_dev *dev);
1133 int mlx5_allmulticast_disable(struct rte_eth_dev *dev);
1137 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
1138 int mlx5_stats_reset(struct rte_eth_dev *dev);
1139 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats,
1141 int mlx5_xstats_reset(struct rte_eth_dev *dev);
1142 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
1143 struct rte_eth_xstat_name *xstats_names,
1148 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
1149 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on);
1150 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask);
1152 /* mlx5_vlan_os.c */
1154 void mlx5_vlan_vmwa_exit(void *ctx);
1155 void mlx5_vlan_vmwa_release(struct rte_eth_dev *dev,
1156 struct mlx5_vf_vlan *vf_vlan);
1157 void mlx5_vlan_vmwa_acquire(struct rte_eth_dev *dev,
1158 struct mlx5_vf_vlan *vf_vlan);
1159 void *mlx5_vlan_vmwa_init(struct rte_eth_dev *dev, uint32_t ifindex);
1161 /* mlx5_trigger.c */
1163 int mlx5_dev_start(struct rte_eth_dev *dev);
1164 int mlx5_dev_stop(struct rte_eth_dev *dev);
1165 int mlx5_traffic_enable(struct rte_eth_dev *dev);
1166 void mlx5_traffic_disable(struct rte_eth_dev *dev);
1167 int mlx5_traffic_restart(struct rte_eth_dev *dev);
1168 int mlx5_hairpin_queue_peer_update(struct rte_eth_dev *dev, uint16_t peer_queue,
1169 struct rte_hairpin_peer_info *current_info,
1170 struct rte_hairpin_peer_info *peer_info,
1171 uint32_t direction);
1172 int mlx5_hairpin_queue_peer_bind(struct rte_eth_dev *dev, uint16_t cur_queue,
1173 struct rte_hairpin_peer_info *peer_info,
1174 uint32_t direction);
1175 int mlx5_hairpin_queue_peer_unbind(struct rte_eth_dev *dev, uint16_t cur_queue,
1176 uint32_t direction);
1177 int mlx5_hairpin_bind(struct rte_eth_dev *dev, uint16_t rx_port);
1178 int mlx5_hairpin_unbind(struct rte_eth_dev *dev, uint16_t rx_port);
1179 int mlx5_hairpin_get_peer_ports(struct rte_eth_dev *dev, uint16_t *peer_ports,
1180 size_t len, uint32_t direction);
1184 int mlx5_flow_discover_mreg_c(struct rte_eth_dev *eth_dev);
1185 bool mlx5_flow_ext_mreg_supported(struct rte_eth_dev *dev);
1186 void mlx5_flow_print(struct rte_flow *flow);
1187 int mlx5_flow_validate(struct rte_eth_dev *dev,
1188 const struct rte_flow_attr *attr,
1189 const struct rte_flow_item items[],
1190 const struct rte_flow_action actions[],
1191 struct rte_flow_error *error);
1192 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev,
1193 const struct rte_flow_attr *attr,
1194 const struct rte_flow_item items[],
1195 const struct rte_flow_action actions[],
1196 struct rte_flow_error *error);
1197 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow,
1198 struct rte_flow_error *error);
1199 void mlx5_flow_list_flush(struct rte_eth_dev *dev, uint32_t *list, bool active);
1200 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error);
1201 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow,
1202 const struct rte_flow_action *action, void *data,
1203 struct rte_flow_error *error);
1204 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable,
1205 struct rte_flow_error *error);
1206 int mlx5_dev_filter_ctrl(struct rte_eth_dev *dev,
1207 enum rte_filter_type filter_type,
1208 enum rte_filter_op filter_op,
1210 int mlx5_flow_start_default(struct rte_eth_dev *dev);
1211 void mlx5_flow_stop_default(struct rte_eth_dev *dev);
1212 int mlx5_flow_verify(struct rte_eth_dev *dev);
1213 int mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, uint32_t queue);
1214 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev,
1215 struct rte_flow_item_eth *eth_spec,
1216 struct rte_flow_item_eth *eth_mask,
1217 struct rte_flow_item_vlan *vlan_spec,
1218 struct rte_flow_item_vlan *vlan_mask);
1219 int mlx5_ctrl_flow(struct rte_eth_dev *dev,
1220 struct rte_flow_item_eth *eth_spec,
1221 struct rte_flow_item_eth *eth_mask);
1222 int mlx5_flow_lacp_miss(struct rte_eth_dev *dev);
1223 struct rte_flow *mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev);
1224 int mlx5_flow_create_drop_queue(struct rte_eth_dev *dev);
1225 void mlx5_flow_delete_drop_queue(struct rte_eth_dev *dev);
1226 void mlx5_flow_async_pool_query_handle(struct mlx5_dev_ctx_shared *sh,
1227 uint64_t async_id, int status);
1228 void mlx5_set_query_alarm(struct mlx5_dev_ctx_shared *sh);
1229 void mlx5_flow_query_alarm(void *arg);
1230 uint32_t mlx5_counter_alloc(struct rte_eth_dev *dev);
1231 void mlx5_counter_free(struct rte_eth_dev *dev, uint32_t cnt);
1232 int mlx5_counter_query(struct rte_eth_dev *dev, uint32_t cnt,
1233 bool clear, uint64_t *pkts, uint64_t *bytes);
1234 int mlx5_flow_dev_dump(struct rte_eth_dev *dev, FILE *file,
1235 struct rte_flow_error *error);
1236 void mlx5_flow_rxq_dynf_metadata_set(struct rte_eth_dev *dev);
1237 int mlx5_flow_get_aged_flows(struct rte_eth_dev *dev, void **contexts,
1238 uint32_t nb_contexts, struct rte_flow_error *error);
1242 int mlx5_mp_os_primary_handle(const struct rte_mp_msg *mp_msg,
1244 int mlx5_mp_os_secondary_handle(const struct rte_mp_msg *mp_msg,
1246 void mlx5_mp_os_req_start_rxtx(struct rte_eth_dev *dev);
1247 void mlx5_mp_os_req_stop_rxtx(struct rte_eth_dev *dev);
1248 int mlx5_mp_os_req_queue_control(struct rte_eth_dev *dev, uint16_t queue_id,
1249 enum mlx5_mp_req_type req_type);
1253 int mlx5_pmd_socket_init(void);
1255 /* mlx5_flow_meter.c */
1257 int mlx5_flow_meter_ops_get(struct rte_eth_dev *dev, void *arg);
1258 struct mlx5_flow_meter *mlx5_flow_meter_find(struct mlx5_priv *priv,
1260 struct mlx5_flow_meter *mlx5_flow_meter_attach
1261 (struct mlx5_priv *priv,
1263 const struct rte_flow_attr *attr,
1264 struct rte_flow_error *error);
1265 void mlx5_flow_meter_detach(struct mlx5_flow_meter *fm);
1268 struct rte_pci_driver;
1269 int mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *dev_attr);
1270 void mlx5_os_free_shared_dr(struct mlx5_priv *priv);
1271 int mlx5_os_open_device(const struct mlx5_dev_spawn_data *spawn,
1272 const struct mlx5_dev_config *config,
1273 struct mlx5_dev_ctx_shared *sh);
1274 int mlx5_os_get_pdn(void *pd, uint32_t *pdn);
1275 int mlx5_os_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1276 struct rte_pci_device *pci_dev);
1277 void mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh);
1278 void mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh);
1279 void mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb,
1280 mlx5_dereg_mr_t *dereg_mr_cb);
1281 void mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
1282 int mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
1284 int mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv, unsigned int iface_idx,
1285 struct rte_ether_addr *mac_addr,
1287 int mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable);
1288 int mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable);
1289 int mlx5_os_set_nonblock_channel_fd(int fd);
1290 void mlx5_os_mac_addr_flush(struct rte_eth_dev *dev);
1294 int mlx5_txpp_start(struct rte_eth_dev *dev);
1295 void mlx5_txpp_stop(struct rte_eth_dev *dev);
1296 int mlx5_txpp_read_clock(struct rte_eth_dev *dev, uint64_t *timestamp);
1297 int mlx5_txpp_xstats_get(struct rte_eth_dev *dev,
1298 struct rte_eth_xstat *stats,
1299 unsigned int n, unsigned int n_used);
1300 int mlx5_txpp_xstats_reset(struct rte_eth_dev *dev);
1301 int mlx5_txpp_xstats_get_names(struct rte_eth_dev *dev,
1302 struct rte_eth_xstat_name *xstats_names,
1303 unsigned int n, unsigned int n_used);
1304 void mlx5_txpp_interrupt_handler(void *cb_arg);
1308 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev);
1310 /* mlx5_flow_age.c */
1312 int mlx5_aso_queue_init(struct mlx5_dev_ctx_shared *sh);
1313 int mlx5_aso_queue_start(struct mlx5_dev_ctx_shared *sh);
1314 int mlx5_aso_queue_stop(struct mlx5_dev_ctx_shared *sh);
1315 void mlx5_aso_queue_uninit(struct mlx5_dev_ctx_shared *sh);
1317 #endif /* RTE_PMD_MLX5_H_ */