1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_H_
7 #define RTE_PMD_MLX5_H_
14 #include <netinet/in.h>
15 #include <sys/queue.h>
18 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
20 #pragma GCC diagnostic ignored "-Wpedantic"
22 #include <infiniband/verbs.h>
24 #pragma GCC diagnostic error "-Wpedantic"
28 #include <rte_ether.h>
29 #include <rte_ethdev_driver.h>
30 #include <rte_rwlock.h>
31 #include <rte_interrupts.h>
32 #include <rte_errno.h>
35 #include "mlx5_utils.h"
37 #include "mlx5_autoconf.h"
38 #include "mlx5_defs.h"
39 #include "mlx5_glue.h"
43 PCI_VENDOR_ID_MELLANOX = 0x15b3,
47 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013,
48 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014,
49 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015,
50 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016,
51 PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017,
52 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018,
53 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019,
54 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a,
55 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF = 0xa2d2,
56 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF = 0xa2d3,
57 PCI_DEVICE_ID_MELLANOX_CONNECTX6 = 0x101b,
58 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF = 0x101c,
59 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX = 0x101d,
60 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF = 0x101e,
63 /* Request types for IPC. */
64 enum mlx5_mp_req_type {
65 MLX5_MP_REQ_VERBS_CMD_FD = 1,
66 MLX5_MP_REQ_CREATE_MR,
67 MLX5_MP_REQ_START_RXTX,
68 MLX5_MP_REQ_STOP_RXTX,
69 MLX5_MP_REQ_QUEUE_STATE_MODIFY,
72 struct mlx5_mp_arg_queue_state_modify {
73 uint8_t is_wq; /* Set if WQ. */
74 uint16_t queue_id; /* DPDK queue ID. */
75 enum ibv_wq_state state; /* WQ requested state. */
78 /* Pameters for IPC. */
79 struct mlx5_mp_param {
80 enum mlx5_mp_req_type type;
85 uintptr_t addr; /* MLX5_MP_REQ_CREATE_MR */
86 struct mlx5_mp_arg_queue_state_modify state_modify;
87 /* MLX5_MP_REQ_QUEUE_STATE_MODIFY */
91 /** Request timeout for IPC. */
92 #define MLX5_MP_REQ_TIMEOUT_SEC 5
94 /** Key string for IPC. */
95 #define MLX5_MP_NAME "net_mlx5_mp"
97 /* Recognized Infiniband device physical port name types. */
98 enum mlx5_phys_port_name_type {
99 MLX5_PHYS_PORT_NAME_TYPE_NOTSET = 0, /* Not set. */
100 MLX5_PHYS_PORT_NAME_TYPE_LEGACY, /* before kernel ver < 5.0 */
101 MLX5_PHYS_PORT_NAME_TYPE_UPLINK, /* p0, kernel ver >= 5.0 */
102 MLX5_PHYS_PORT_NAME_TYPE_PFVF, /* pf0vf0, kernel ver >= 5.0 */
103 MLX5_PHYS_PORT_NAME_TYPE_UNKNOWN, /* Unrecognized. */
106 /** Switch information returned by mlx5_nl_switch_info(). */
107 struct mlx5_switch_info {
108 uint32_t master:1; /**< Master device. */
109 uint32_t representor:1; /**< Representor device. */
110 enum mlx5_phys_port_name_type name_type; /** < Port name type. */
111 int32_t pf_num; /**< PF number (valid for pfxvfx format only). */
112 int32_t port_name; /**< Representor port name. */
113 uint64_t switch_id; /**< Switch identifier. */
116 LIST_HEAD(mlx5_dev_list, mlx5_ibv_shared);
118 /* Shared data between primary and secondary processes. */
119 struct mlx5_shared_data {
121 /* Global spinlock for primary and secondary processes. */
122 int init_done; /* Whether primary has done initialization. */
123 unsigned int secondary_cnt; /* Number of secondary processes init'd. */
124 struct mlx5_dev_list mem_event_cb_list;
125 rte_rwlock_t mem_event_rwlock;
128 /* Per-process data structure, not visible to other processes. */
129 struct mlx5_local_data {
130 int init_done; /* Whether a secondary has done initialization. */
133 extern struct mlx5_shared_data *mlx5_shared_data;
135 struct mlx5_counter_ctrl {
136 /* Name of the counter. */
137 char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE];
138 /* Name of the counter on the device table. */
139 char ctr_name[RTE_ETH_XSTATS_NAME_SIZE];
140 uint32_t ib:1; /**< Nonzero for IB counters. */
143 struct mlx5_xstats_ctrl {
144 /* Number of device stats. */
146 /* Number of device stats identified by PMD. */
147 uint16_t mlx5_stats_n;
148 /* Index in the device counters table. */
149 uint16_t dev_table_idx[MLX5_MAX_XSTATS];
150 uint64_t base[MLX5_MAX_XSTATS];
151 struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS];
154 struct mlx5_stats_ctrl {
155 /* Base for imissed counter. */
156 uint64_t imissed_base;
159 /* devX creation object */
160 struct mlx5_devx_obj {
161 struct mlx5dv_devx_obj *obj; /* The DV object. */
162 int id; /* The object ID. */
165 struct mlx5_devx_mkey_attr {
172 /* HCA supports this number of time periods for LRO. */
173 #define MLX5_LRO_NUM_SUPP_PERIODS 4
175 /* HCA attributes. */
176 struct mlx5_hca_attr {
177 uint32_t eswitch_manager:1;
178 uint32_t flow_counters_dump:1;
179 uint8_t flow_counter_bulk_alloc_bitmap;
180 uint32_t eth_net_offloads:1;
182 uint32_t wqe_vlan_insert:1;
183 uint32_t wqe_inline_mode:2;
184 uint32_t vport_inline_mode:3;
185 uint32_t tunnel_stateless_geneve_rx:1;
186 uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */
188 uint32_t tunnel_lro_gre:1;
189 uint32_t tunnel_lro_vxlan:1;
190 uint32_t lro_max_msg_sz_mode:2;
191 uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS];
192 uint32_t flex_parser_protocols;
194 uint32_t log_max_hairpin_queues:5;
195 uint32_t log_max_hairpin_wq_data_sz:5;
196 uint32_t log_max_hairpin_num_packets:5;
201 TAILQ_HEAD(mlx5_flows, rte_flow);
203 /* Default PMD specific parameter value. */
204 #define MLX5_ARG_UNSET (-1)
206 #define MLX5_LRO_SUPPORTED(dev) \
207 (((struct mlx5_priv *)((dev)->data->dev_private))->config.lro.supported)
209 /* LRO configurations structure. */
210 struct mlx5_lro_config {
211 uint32_t supported:1; /* Whether LRO is supported. */
212 uint32_t timeout; /* User configuration. */
216 * Device configuration structure.
218 * Merged configuration from:
220 * - Device capabilities,
221 * - User device parameters disabled features.
223 struct mlx5_dev_config {
224 unsigned int hw_csum:1; /* Checksum offload is supported. */
225 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */
226 unsigned int hw_vlan_insert:1; /* VLAN insertion in WQE is supported. */
227 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */
228 unsigned int hw_padding:1; /* End alignment padding is supported. */
229 unsigned int vf:1; /* This is a VF. */
230 unsigned int tunnel_en:1;
231 /* Whether tunnel stateless offloads are supported. */
232 unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */
233 unsigned int cqe_comp:1; /* CQE compression is enabled. */
234 unsigned int cqe_pad:1; /* CQE padding is enabled. */
235 unsigned int tso:1; /* Whether TSO is supported. */
236 unsigned int rx_vec_en:1; /* Rx vector is enabled. */
237 unsigned int mr_ext_memseg_en:1;
238 /* Whether memseg should be extended for MR creation. */
239 unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */
240 unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */
241 unsigned int dv_esw_en:1; /* Enable E-Switch DV flow. */
242 unsigned int dv_flow_en:1; /* Enable DV flow. */
243 unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */
244 unsigned int devx:1; /* Whether devx interface is available or not. */
245 unsigned int dest_tir:1; /* Whether advanced DR API is available. */
247 unsigned int enabled:1; /* Whether MPRQ is enabled. */
248 unsigned int stride_num_n; /* Number of strides. */
249 unsigned int min_stride_size_n; /* Min size of a stride. */
250 unsigned int max_stride_size_n; /* Max size of a stride. */
251 unsigned int max_memcpy_len;
252 /* Maximum packet size to memcpy Rx packets. */
253 unsigned int min_rxqs_num;
254 /* Rx queue count threshold to enable MPRQ. */
255 } mprq; /* Configurations for Multi-Packet RQ. */
256 int mps; /* Multi-packet send supported mode. */
257 unsigned int flow_prio; /* Number of flow priorities. */
258 enum modify_reg flow_mreg_c[MLX5_MREG_C_NUM];
259 /* Availibility of mreg_c's. */
260 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */
261 unsigned int ind_table_max_size; /* Maximum indirection table size. */
262 unsigned int max_dump_files_num; /* Maximum dump files per queue. */
263 int txqs_inline; /* Queue number threshold for inlining. */
264 int txq_inline_min; /* Minimal amount of data bytes to inline. */
265 int txq_inline_max; /* Max packet size for inlining with SEND. */
266 int txq_inline_mpw; /* Max packet size for inlining with eMPW. */
267 struct mlx5_hca_attr hca_attr; /* HCA attributes. */
268 struct mlx5_lro_config lro; /* LRO configuration. */
271 struct mlx5_devx_wq_attr {
273 uint32_t wq_signature:1;
274 uint32_t end_padding_mode:2;
276 uint32_t hds_skip_first_sge:1;
277 uint32_t log2_hds_buf_size:3;
278 uint32_t page_offset:5;
281 uint32_t uar_page:24;
285 uint32_t log_wq_stride:4;
286 uint32_t log_wq_pg_sz:5;
287 uint32_t log_wq_sz:5;
288 uint32_t dbr_umem_valid:1;
289 uint32_t wq_umem_valid:1;
290 uint32_t log_hairpin_num_packets:5;
291 uint32_t log_hairpin_data_sz:5;
292 uint32_t single_wqe_log_num_of_strides:4;
293 uint32_t two_byte_shift_en:1;
294 uint32_t single_stride_log_num_of_bytes:3;
295 uint32_t dbr_umem_id;
297 uint64_t wq_umem_offset;
300 /* Create RQ attributes structure, used by create RQ operation. */
301 struct mlx5_devx_create_rq_attr {
303 uint32_t delay_drop_en:1;
304 uint32_t scatter_fcs:1;
306 uint32_t mem_rq_type:4;
308 uint32_t flush_in_error_en:1;
310 uint32_t user_index:24;
312 uint32_t counter_set_id:8;
314 struct mlx5_devx_wq_attr wq_attr;
317 /* Modify RQ attributes structure, used by modify RQ operation. */
318 struct mlx5_devx_modify_rq_attr {
320 uint32_t rq_state:4; /* Current RQ state. */
321 uint32_t state:4; /* Required RQ state. */
322 uint32_t scatter_fcs:1;
324 uint32_t counter_set_id:8;
325 uint32_t hairpin_peer_sq:24;
326 uint32_t hairpin_peer_vhca:16;
327 uint64_t modify_bitmask;
328 uint32_t lwm:16; /* Contained WQ lwm. */
331 struct mlx5_rx_hash_field_select {
332 uint32_t l3_prot_type:1;
333 uint32_t l4_prot_type:1;
334 uint32_t selected_fields:30;
337 /* TIR attributes structure, used by TIR operations. */
338 struct mlx5_devx_tir_attr {
339 uint32_t disp_type:4;
340 uint32_t lro_timeout_period_usecs:16;
341 uint32_t lro_enable_mask:4;
342 uint32_t lro_max_msg_sz:8;
343 uint32_t inline_rqn:24;
344 uint32_t rx_hash_symmetric:1;
345 uint32_t tunneled_offload_en:1;
346 uint32_t indirect_table:24;
347 uint32_t rx_hash_fn:4;
348 uint32_t self_lb_block:2;
349 uint32_t transport_domain:24;
350 uint32_t rx_hash_toeplitz_key[10];
351 struct mlx5_rx_hash_field_select rx_hash_field_selector_outer;
352 struct mlx5_rx_hash_field_select rx_hash_field_selector_inner;
355 /* RQT attributes structure, used by RQT operations. */
356 struct mlx5_devx_rqt_attr {
357 uint32_t rqt_max_size:16;
358 uint32_t rqt_actual_size:16;
362 /* TIS attributes structure. */
363 struct mlx5_devx_tis_attr {
364 uint32_t strict_lag_tx_port_affinity:1;
366 uint32_t lag_tx_port_affinity:4;
368 uint32_t transport_domain:24;
371 /* SQ attributes structure, used by SQ create operation. */
372 struct mlx5_devx_create_sq_attr {
374 uint32_t cd_master:1;
376 uint32_t flush_in_error_en:1;
377 uint32_t allow_multi_pkt_send_wqe:1;
378 uint32_t min_wqe_inline_mode:3;
381 uint32_t allow_swp:1;
383 uint32_t user_index:24;
385 uint32_t packet_pacing_rate_limit_index:16;
386 uint32_t tis_lst_sz:16;
388 struct mlx5_devx_wq_attr wq_attr;
391 /* SQ attributes structure, used by SQ modify operation. */
392 struct mlx5_devx_modify_sq_attr {
395 uint32_t hairpin_peer_rq:24;
396 uint32_t hairpin_peer_vhca:16;
400 * Type of object being allocated.
402 enum mlx5_verbs_alloc_type {
403 MLX5_VERBS_ALLOC_TYPE_NONE,
404 MLX5_VERBS_ALLOC_TYPE_TX_QUEUE,
405 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE,
408 /* VLAN netdev for VLAN workaround. */
409 struct mlx5_vlan_dev {
411 uint32_t ifindex; /**< Own interface index. */
414 /* Structure for VF VLAN workaround. */
415 struct mlx5_vf_vlan {
421 * Array of VLAN devices created on the base of VF
422 * used for workaround in virtual environments.
424 struct mlx5_vlan_vmwa_context {
428 struct rte_eth_dev *dev;
429 struct mlx5_vlan_dev vlan_dev[4096];
433 * Verbs allocator needs a context to know in the callback which kind of
434 * resources it is allocating.
436 struct mlx5_verbs_alloc_ctx {
437 enum mlx5_verbs_alloc_type type; /* Kind of object being allocated. */
438 const void *obj; /* Pointer to the DPDK object. */
441 LIST_HEAD(mlx5_mr_list, mlx5_mr);
443 /* Flow drop context necessary due to Verbs API. */
445 struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */
446 struct mlx5_rxq_obj *rxq; /* Rx queue object. */
449 #define MLX5_COUNTERS_PER_POOL 512
450 #define MLX5_MAX_PENDING_QUERIES 4
452 struct mlx5_flow_counter_pool;
454 struct flow_counter_stats {
459 /* Counters information. */
460 struct mlx5_flow_counter {
461 TAILQ_ENTRY(mlx5_flow_counter) next;
462 /**< Pointer to the next flow counter structure. */
463 uint32_t shared:1; /**< Share counter ID with other flow rules. */
465 /**< Whether the counter was allocated by batch command. */
466 uint32_t ref_cnt:30; /**< Reference counter. */
467 uint32_t id; /**< Counter ID. */
468 union { /**< Holds the counters for the rule. */
469 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42)
470 struct ibv_counter_set *cs;
471 #elif defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
472 struct ibv_counters *cs;
474 struct mlx5_devx_obj *dcs; /**< Counter Devx object. */
475 struct mlx5_flow_counter_pool *pool; /**< The counter pool. */
478 uint64_t hits; /**< Reset value of hits packets. */
479 int64_t query_gen; /**< Generation of the last release. */
481 uint64_t bytes; /**< Reset value of bytes. */
482 void *action; /**< Pointer to the dv action. */
485 TAILQ_HEAD(mlx5_counters, mlx5_flow_counter);
487 /* Counter pool structure - query is in pool resolution. */
488 struct mlx5_flow_counter_pool {
489 TAILQ_ENTRY(mlx5_flow_counter_pool) next;
490 struct mlx5_counters counters; /* Free counter list. */
492 struct mlx5_devx_obj *min_dcs;
493 rte_atomic64_t a64_dcs;
495 /* The devx object of the minimum counter ID. */
496 rte_atomic64_t query_gen;
497 uint32_t n_counters: 16; /* Number of devx allocated counters. */
498 rte_spinlock_t sl; /* The pool lock. */
499 struct mlx5_counter_stats_raw *raw;
500 struct mlx5_counter_stats_raw *raw_hw; /* The raw on HW working. */
501 struct mlx5_flow_counter counters_raw[]; /* The pool counters memory. */
504 struct mlx5_counter_stats_raw;
506 /* Memory management structure for group of counter statistics raws. */
507 struct mlx5_counter_stats_mem_mng {
508 LIST_ENTRY(mlx5_counter_stats_mem_mng) next;
509 struct mlx5_counter_stats_raw *raws;
510 struct mlx5_devx_obj *dm;
511 struct mlx5dv_devx_umem *umem;
514 /* Raw memory structure for the counter statistics values of a pool. */
515 struct mlx5_counter_stats_raw {
516 LIST_ENTRY(mlx5_counter_stats_raw) next;
518 struct mlx5_counter_stats_mem_mng *mem_mng;
519 volatile struct flow_counter_stats *data;
522 TAILQ_HEAD(mlx5_counter_pools, mlx5_flow_counter_pool);
524 /* Container structure for counter pools. */
525 struct mlx5_pools_container {
526 rte_atomic16_t n_valid; /* Number of valid pools. */
527 uint16_t n; /* Number of pools. */
528 struct mlx5_counter_pools pool_list; /* Counter pool list. */
529 struct mlx5_flow_counter_pool **pools; /* Counter pool array. */
530 struct mlx5_counter_stats_mem_mng *init_mem_mng;
531 /* Hold the memory management for the next allocated pools raws. */
534 /* Counter global management structure. */
535 struct mlx5_flow_counter_mng {
536 uint8_t mhi[2]; /* master \ host container index. */
537 struct mlx5_pools_container ccont[2 * 2];
538 /* 2 containers for single and for batch for double-buffer. */
539 struct mlx5_counters flow_counters; /* Legacy flow counter list. */
540 uint8_t pending_queries;
543 uint8_t query_thread_on;
544 LIST_HEAD(mem_mngs, mlx5_counter_stats_mem_mng) mem_mngs;
545 LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws;
548 /* Per port data of shared IB device. */
549 struct mlx5_ibv_shared_port {
551 uint32_t devx_ih_port_id;
553 * Interrupt handler port_id. Used by shared interrupt
554 * handler to find the corresponding rte_eth device
555 * by IB port index. If value is equal or greater
556 * RTE_MAX_ETHPORTS it means there is no subhandler
557 * installed for specified IB port index.
561 /* Table structure. */
562 struct mlx5_flow_tbl_resource {
563 void *obj; /**< Pointer to DR table object. */
564 rte_atomic32_t refcnt; /**< Reference counter. */
567 #define MLX5_MAX_TABLES UINT16_MAX
568 #define MLX5_HAIRPIN_TX_TABLE (UINT16_MAX - 1)
569 /* Reserve the last two tables for metadata register copy. */
570 #define MLX5_FLOW_MREG_ACT_TABLE_GROUP (MLX5_MAX_TABLES - 1)
571 #define MLX5_FLOW_MREG_CP_TABLE_GROUP \
572 (MLX5_FLOW_MREG_ACT_TABLE_GROUP - 1)
573 #define MLX5_MAX_TABLES_FDB UINT16_MAX
575 #define MLX5_DBR_PAGE_SIZE 4096 /* Must be >= 512. */
576 #define MLX5_DBR_SIZE 8
577 #define MLX5_DBR_PER_PAGE (MLX5_DBR_PAGE_SIZE / MLX5_DBR_SIZE)
578 #define MLX5_DBR_BITMAP_SIZE (MLX5_DBR_PER_PAGE / 64)
580 struct mlx5_devx_dbr_page {
581 /* Door-bell records, must be first member in structure. */
582 uint8_t dbrs[MLX5_DBR_PAGE_SIZE];
583 LIST_ENTRY(mlx5_devx_dbr_page) next; /* Pointer to the next element. */
584 struct mlx5dv_devx_umem *umem;
585 uint32_t dbr_count; /* Number of door-bell records in use. */
586 /* 1 bit marks matching door-bell is in use. */
587 uint64_t dbr_bitmap[MLX5_DBR_BITMAP_SIZE];
590 /* ID generation structure. */
591 struct mlx5_flow_id_pool {
592 uint32_t *free_arr; /**< Pointer to the a array of free values. */
594 /**< The next index that can be used without any free elements. */
595 uint32_t *curr; /**< Pointer to the index to pop. */
596 uint32_t *last; /**< Pointer to the last element in the empty arrray. */
600 * Shared Infiniband device context for Master/Representors
601 * which belong to same IB device with multiple IB ports.
603 struct mlx5_ibv_shared {
604 LIST_ENTRY(mlx5_ibv_shared) next;
606 uint32_t devx:1; /* Opened with DV. */
607 uint32_t max_port; /* Maximal IB device port index. */
608 struct ibv_context *ctx; /* Verbs/DV context. */
609 struct ibv_pd *pd; /* Protection Domain. */
610 uint32_t pdn; /* Protection Domain number. */
611 uint32_t tdn; /* Transport Domain number. */
612 char ibdev_name[IBV_SYSFS_NAME_MAX]; /* IB device name. */
613 char ibdev_path[IBV_SYSFS_PATH_MAX]; /* IB device path for secondary */
614 struct ibv_device_attr_ex device_attr; /* Device properties. */
615 LIST_ENTRY(mlx5_ibv_shared) mem_event_cb;
616 /**< Called by memory event callback. */
618 uint32_t dev_gen; /* Generation number to flush local caches. */
619 rte_rwlock_t rwlock; /* MR Lock. */
620 struct mlx5_mr_btree cache; /* Global MR cache table. */
621 struct mlx5_mr_list mr_list; /* Registered MR list. */
622 struct mlx5_mr_list mr_free_list; /* Freed MR list. */
624 /* Shared DV/DR flow data section. */
625 pthread_mutex_t dv_mutex; /* DV context mutex. */
626 uint32_t dv_refcnt; /* DV/DR data reference counter. */
627 void *fdb_domain; /* FDB Direct Rules name space handle. */
628 struct mlx5_flow_tbl_resource fdb_tbl[MLX5_MAX_TABLES_FDB];
629 /* FDB Direct Rules tables. */
630 void *rx_domain; /* RX Direct Rules name space handle. */
631 struct mlx5_flow_tbl_resource rx_tbl[MLX5_MAX_TABLES];
632 /* RX Direct Rules tables. */
633 void *tx_domain; /* TX Direct Rules name space handle. */
634 struct mlx5_flow_tbl_resource tx_tbl[MLX5_MAX_TABLES];
635 /* TX Direct Rules tables. */
636 void *esw_drop_action; /* Pointer to DR E-Switch drop action. */
637 void *pop_vlan_action; /* Pointer to DR pop VLAN action. */
638 /* TX Direct Rules tables/ */
639 LIST_HEAD(matchers, mlx5_flow_dv_matcher) matchers;
640 LIST_HEAD(encap_decap, mlx5_flow_dv_encap_decap_resource) encaps_decaps;
641 LIST_HEAD(modify_cmd, mlx5_flow_dv_modify_hdr_resource) modify_cmds;
642 LIST_HEAD(tag, mlx5_flow_dv_tag_resource) tags;
643 LIST_HEAD(jump, mlx5_flow_dv_jump_tbl_resource) jump_tbl;
644 LIST_HEAD(port_id_action_list, mlx5_flow_dv_port_id_action_resource)
645 port_id_action_list; /* List of port ID actions. */
646 LIST_HEAD(push_vlan_action_list, mlx5_flow_dv_push_vlan_action_resource)
647 push_vlan_action_list; /* List of push VLAN actions. */
648 struct mlx5_flow_counter_mng cmng; /* Counters management structure. */
649 /* Shared interrupt handler section. */
650 pthread_mutex_t intr_mutex; /* Interrupt config mutex. */
651 uint32_t intr_cnt; /* Interrupt handler reference counter. */
652 struct rte_intr_handle intr_handle; /* Interrupt handler for device. */
653 uint32_t devx_intr_cnt; /* Devx interrupt handler reference counter. */
654 struct rte_intr_handle intr_handle_devx; /* DEVX interrupt handler. */
655 struct mlx5dv_devx_cmd_comp *devx_comp; /* DEVX async comp obj. */
656 struct mlx5_devx_obj *tis; /* TIS object. */
657 struct mlx5_devx_obj *td; /* Transport domain. */
658 struct mlx5_flow_id_pool *flow_id_pool; /* Flow ID pool. */
659 struct mlx5_ibv_shared_port port[]; /* per device port data array. */
662 /* Per-process private structure. */
663 struct mlx5_proc_priv {
665 /* Size of UAR register table. */
667 /* Table of UAR registers for each process. */
670 #define MLX5_PROC_PRIV(port_id) \
671 ((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private)
674 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */
675 struct mlx5_ibv_shared *sh; /* Shared IB device context. */
676 uint32_t ibv_port; /* IB device port number. */
677 struct rte_pci_device *pci_dev; /* Backend PCI device. */
678 struct rte_ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */
679 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES);
680 /* Bit-field of MAC addresses owned by the PMD. */
681 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */
682 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */
683 /* Device properties. */
684 uint16_t mtu; /* Configured MTU. */
685 unsigned int isolated:1; /* Whether isolated mode is enabled. */
686 unsigned int representor:1; /* Device is a port representor. */
687 unsigned int master:1; /* Device is a E-Switch master. */
688 unsigned int dr_shared:1; /* DV/DR data is shared. */
689 unsigned int counter_fallback:1; /* Use counter fallback management. */
690 uint16_t domain_id; /* Switch domain identifier. */
691 uint16_t vport_id; /* Associated VF vport index (if any). */
692 uint32_t vport_meta_tag; /* Used for vport index match ove VF LAG. */
693 uint32_t vport_meta_mask; /* Used for vport index field match mask. */
694 int32_t representor_id; /* Port representor identifier. */
695 int32_t pf_bond; /* >=0 means PF index in bonding configuration. */
696 unsigned int if_index; /* Associated kernel network device index. */
698 unsigned int rxqs_n; /* RX queues array size. */
699 unsigned int txqs_n; /* TX queues array size. */
700 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */
701 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */
702 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
703 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */
704 unsigned int (*reta_idx)[]; /* RETA index table. */
705 unsigned int reta_idx_n; /* RETA index size. */
706 struct mlx5_drop drop_queue; /* Flow drop queues. */
707 struct mlx5_flows flows; /* RTE Flow rules. */
708 struct mlx5_flows ctrl_flows; /* Control flow rules. */
709 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */
710 LIST_HEAD(rxqobj, mlx5_rxq_obj) rxqsobj; /* Verbs/DevX Rx queues. */
711 LIST_HEAD(hrxq, mlx5_hrxq) hrxqs; /* Verbs Hash Rx queues. */
712 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */
713 LIST_HEAD(txqobj, mlx5_txq_obj) txqsobj; /* Verbs/DevX Tx queues. */
714 /* Indirection tables. */
715 LIST_HEAD(ind_tables, mlx5_ind_table_obj) ind_tbls;
716 /* Pointer to next element. */
717 rte_atomic32_t refcnt; /**< Reference counter. */
718 struct ibv_flow_action *verbs_action;
719 /**< Verbs modify header action object. */
720 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
721 uint8_t max_lro_msg_size;
722 /* Tags resources cache. */
723 uint32_t link_speed_capa; /* Link speed capabilities. */
724 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */
725 struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */
726 struct mlx5_dev_config config; /* Device configuration. */
727 struct mlx5_verbs_alloc_ctx verbs_alloc_ctx;
728 /* Context for Verbs allocator. */
729 int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */
730 int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */
731 uint32_t nl_sn; /* Netlink message sequence number. */
732 LIST_HEAD(dbrpage, mlx5_devx_dbr_page) dbrpgs; /* Door-bell pages. */
733 struct mlx5_vlan_vmwa_context *vmwa_context; /* VLAN WA context. */
735 rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */
736 rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX];
737 /* UAR same-page access control required in 32bit implementations. */
739 uint8_t skip_default_rss_reta; /* Skip configuration of default reta. */
742 #define PORT_ID(priv) ((priv)->dev_data->port_id)
743 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)])
747 int mlx5_getenv_int(const char *);
748 int mlx5_proc_priv_init(struct rte_eth_dev *dev);
749 int64_t mlx5_get_dbr(struct rte_eth_dev *dev,
750 struct mlx5_devx_dbr_page **dbr_page);
751 int32_t mlx5_release_dbr(struct rte_eth_dev *dev, uint32_t umem_id,
753 int mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev,
754 struct rte_eth_udp_tunnel *udp_tunnel);
755 uint16_t mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev);
757 /* Macro to iterate over all valid ports for mlx5 driver. */
758 #define MLX5_ETH_FOREACH_DEV(port_id, pci_dev) \
759 for (port_id = mlx5_eth_find_next(0, pci_dev); \
760 port_id < RTE_MAX_ETHPORTS; \
761 port_id = mlx5_eth_find_next(port_id + 1, pci_dev))
765 int mlx5_get_ifname(const struct rte_eth_dev *dev, char (*ifname)[IF_NAMESIZE]);
766 int mlx5_get_master_ifname(const char *ibdev_path, char (*ifname)[IF_NAMESIZE]);
767 unsigned int mlx5_ifindex(const struct rte_eth_dev *dev);
768 int mlx5_ifreq(const struct rte_eth_dev *dev, int req, struct ifreq *ifr);
769 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu);
770 int mlx5_set_flags(struct rte_eth_dev *dev, unsigned int keep,
772 int mlx5_dev_configure(struct rte_eth_dev *dev);
773 int mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info);
774 int mlx5_read_clock(struct rte_eth_dev *dev, uint64_t *clock);
775 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size);
776 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev);
777 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete);
778 int mlx5_force_link_status_change(struct rte_eth_dev *dev, int status);
779 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
780 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev,
781 struct rte_eth_fc_conf *fc_conf);
782 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev,
783 struct rte_eth_fc_conf *fc_conf);
784 int mlx5_dev_to_pci_addr(const char *dev_path,
785 struct rte_pci_addr *pci_addr);
786 void mlx5_dev_link_status_handler(void *arg);
787 void mlx5_dev_interrupt_handler(void *arg);
788 void mlx5_dev_interrupt_handler_devx(void *arg);
789 void mlx5_dev_interrupt_handler_uninstall(struct rte_eth_dev *dev);
790 void mlx5_dev_interrupt_handler_install(struct rte_eth_dev *dev);
791 void mlx5_dev_interrupt_handler_devx_uninstall(struct rte_eth_dev *dev);
792 void mlx5_dev_interrupt_handler_devx_install(struct rte_eth_dev *dev);
793 int mlx5_set_link_down(struct rte_eth_dev *dev);
794 int mlx5_set_link_up(struct rte_eth_dev *dev);
795 int mlx5_is_removed(struct rte_eth_dev *dev);
796 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev);
797 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev);
798 struct mlx5_priv *mlx5_port_to_eswitch_info(uint16_t port, bool valid);
799 struct mlx5_priv *mlx5_dev_to_eswitch_info(struct rte_eth_dev *dev);
800 int mlx5_sysfs_switch_info(unsigned int ifindex,
801 struct mlx5_switch_info *info);
802 void mlx5_sysfs_check_switch_info(bool device_dir,
803 struct mlx5_switch_info *switch_info);
804 void mlx5_nl_check_switch_info(bool nun_vf_set,
805 struct mlx5_switch_info *switch_info);
806 void mlx5_translate_port_name(const char *port_name_in,
807 struct mlx5_switch_info *port_info_out);
808 void mlx5_intr_callback_unregister(const struct rte_intr_handle *handle,
809 rte_intr_callback_fn cb_fn, void *cb_arg);
810 int mlx5_get_module_info(struct rte_eth_dev *dev,
811 struct rte_eth_dev_module_info *modinfo);
812 int mlx5_get_module_eeprom(struct rte_eth_dev *dev,
813 struct rte_dev_eeprom_info *info);
814 int mlx5_hairpin_cap_get(struct rte_eth_dev *dev,
815 struct rte_eth_hairpin_cap *cap);
816 int mlx5_dev_configure_rss_reta(struct rte_eth_dev *dev);
820 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]);
821 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
822 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
823 uint32_t index, uint32_t vmdq);
824 int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr);
825 int mlx5_set_mc_addr_list(struct rte_eth_dev *dev,
826 struct rte_ether_addr *mc_addr_set,
827 uint32_t nb_mc_addr);
831 int mlx5_rss_hash_update(struct rte_eth_dev *dev,
832 struct rte_eth_rss_conf *rss_conf);
833 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev,
834 struct rte_eth_rss_conf *rss_conf);
835 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size);
836 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev,
837 struct rte_eth_rss_reta_entry64 *reta_conf,
839 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev,
840 struct rte_eth_rss_reta_entry64 *reta_conf,
845 int mlx5_promiscuous_enable(struct rte_eth_dev *dev);
846 int mlx5_promiscuous_disable(struct rte_eth_dev *dev);
847 int mlx5_allmulticast_enable(struct rte_eth_dev *dev);
848 int mlx5_allmulticast_disable(struct rte_eth_dev *dev);
852 void mlx5_stats_init(struct rte_eth_dev *dev);
853 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
854 int mlx5_stats_reset(struct rte_eth_dev *dev);
855 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats,
857 int mlx5_xstats_reset(struct rte_eth_dev *dev);
858 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
859 struct rte_eth_xstat_name *xstats_names,
864 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
865 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on);
866 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask);
870 int mlx5_dev_start(struct rte_eth_dev *dev);
871 void mlx5_dev_stop(struct rte_eth_dev *dev);
872 int mlx5_traffic_enable(struct rte_eth_dev *dev);
873 void mlx5_traffic_disable(struct rte_eth_dev *dev);
874 int mlx5_traffic_restart(struct rte_eth_dev *dev);
878 int mlx5_flow_discover_mreg_c(struct rte_eth_dev *eth_dev);
879 bool mlx5_flow_ext_mreg_supported(struct rte_eth_dev *dev);
880 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
881 void mlx5_flow_print(struct rte_flow *flow);
882 int mlx5_flow_validate(struct rte_eth_dev *dev,
883 const struct rte_flow_attr *attr,
884 const struct rte_flow_item items[],
885 const struct rte_flow_action actions[],
886 struct rte_flow_error *error);
887 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev,
888 const struct rte_flow_attr *attr,
889 const struct rte_flow_item items[],
890 const struct rte_flow_action actions[],
891 struct rte_flow_error *error);
892 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow,
893 struct rte_flow_error *error);
894 void mlx5_flow_list_flush(struct rte_eth_dev *dev, struct mlx5_flows *list);
895 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error);
896 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow,
897 const struct rte_flow_action *action, void *data,
898 struct rte_flow_error *error);
899 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable,
900 struct rte_flow_error *error);
901 int mlx5_dev_filter_ctrl(struct rte_eth_dev *dev,
902 enum rte_filter_type filter_type,
903 enum rte_filter_op filter_op,
905 int mlx5_flow_start(struct rte_eth_dev *dev, struct mlx5_flows *list);
906 void mlx5_flow_stop(struct rte_eth_dev *dev, struct mlx5_flows *list);
907 int mlx5_flow_verify(struct rte_eth_dev *dev);
908 int mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, uint32_t queue);
909 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev,
910 struct rte_flow_item_eth *eth_spec,
911 struct rte_flow_item_eth *eth_mask,
912 struct rte_flow_item_vlan *vlan_spec,
913 struct rte_flow_item_vlan *vlan_mask);
914 int mlx5_ctrl_flow(struct rte_eth_dev *dev,
915 struct rte_flow_item_eth *eth_spec,
916 struct rte_flow_item_eth *eth_mask);
917 struct rte_flow *mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev);
918 int mlx5_flow_create_drop_queue(struct rte_eth_dev *dev);
919 void mlx5_flow_delete_drop_queue(struct rte_eth_dev *dev);
920 void mlx5_flow_async_pool_query_handle(struct mlx5_ibv_shared *sh,
921 uint64_t async_id, int status);
922 void mlx5_set_query_alarm(struct mlx5_ibv_shared *sh);
923 void mlx5_flow_query_alarm(void *arg);
926 void mlx5_mp_req_start_rxtx(struct rte_eth_dev *dev);
927 void mlx5_mp_req_stop_rxtx(struct rte_eth_dev *dev);
928 int mlx5_mp_req_mr_create(struct rte_eth_dev *dev, uintptr_t addr);
929 int mlx5_mp_req_verbs_cmd_fd(struct rte_eth_dev *dev);
930 int mlx5_mp_req_queue_state_modify(struct rte_eth_dev *dev,
931 struct mlx5_mp_arg_queue_state_modify *sm);
932 int mlx5_mp_init_primary(void);
933 void mlx5_mp_uninit_primary(void);
934 int mlx5_mp_init_secondary(void);
935 void mlx5_mp_uninit_secondary(void);
939 int mlx5_nl_init(int protocol);
940 int mlx5_nl_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
942 int mlx5_nl_mac_addr_remove(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
944 void mlx5_nl_mac_addr_sync(struct rte_eth_dev *dev);
945 void mlx5_nl_mac_addr_flush(struct rte_eth_dev *dev);
946 int mlx5_nl_promisc(struct rte_eth_dev *dev, int enable);
947 int mlx5_nl_allmulti(struct rte_eth_dev *dev, int enable);
948 unsigned int mlx5_nl_portnum(int nl, const char *name);
949 unsigned int mlx5_nl_ifindex(int nl, const char *name, uint32_t pindex);
950 int mlx5_nl_switch_info(int nl, unsigned int ifindex,
951 struct mlx5_switch_info *info);
953 struct mlx5_vlan_vmwa_context *mlx5_vlan_vmwa_init(struct rte_eth_dev *dev,
955 void mlx5_vlan_vmwa_exit(struct mlx5_vlan_vmwa_context *ctx);
956 void mlx5_vlan_vmwa_release(struct rte_eth_dev *dev,
957 struct mlx5_vf_vlan *vf_vlan);
958 void mlx5_vlan_vmwa_acquire(struct rte_eth_dev *dev,
959 struct mlx5_vf_vlan *vf_vlan);
961 /* mlx5_devx_cmds.c */
963 struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(struct ibv_context *ctx,
965 int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj);
966 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
967 int clear, uint32_t n_counters,
968 uint64_t *pkts, uint64_t *bytes,
969 uint32_t mkey, void *addr,
970 struct mlx5dv_devx_cmd_comp *cmd_comp,
972 int mlx5_devx_cmd_query_hca_attr(struct ibv_context *ctx,
973 struct mlx5_hca_attr *attr);
974 struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(struct ibv_context *ctx,
975 struct mlx5_devx_mkey_attr *attr);
976 int mlx5_devx_get_out_command_status(void *out);
977 int mlx5_devx_cmd_qp_query_tis_td(struct ibv_qp *qp, uint32_t tis_num,
979 struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(struct ibv_context *ctx,
980 struct mlx5_devx_create_rq_attr *rq_attr,
982 int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
983 struct mlx5_devx_modify_rq_attr *rq_attr);
984 struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(struct ibv_context *ctx,
985 struct mlx5_devx_tir_attr *tir_attr);
986 struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(struct ibv_context *ctx,
987 struct mlx5_devx_rqt_attr *rqt_attr);
988 struct mlx5_devx_obj *mlx5_devx_cmd_create_sq
989 (struct ibv_context *ctx, struct mlx5_devx_create_sq_attr *sq_attr);
990 int mlx5_devx_cmd_modify_sq
991 (struct mlx5_devx_obj *sq, struct mlx5_devx_modify_sq_attr *sq_attr);
992 struct mlx5_devx_obj *mlx5_devx_cmd_create_tis
993 (struct ibv_context *ctx, struct mlx5_devx_tis_attr *tis_attr);
994 struct mlx5_devx_obj *mlx5_devx_cmd_create_td(struct ibv_context *ctx);
996 #endif /* RTE_PMD_MLX5_H_ */