1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_H_
7 #define RTE_PMD_MLX5_H_
14 #include <netinet/in.h>
15 #include <sys/queue.h>
18 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
20 #pragma GCC diagnostic ignored "-Wpedantic"
22 #include <infiniband/verbs.h>
24 #pragma GCC diagnostic error "-Wpedantic"
28 #include <rte_ether.h>
29 #include <rte_ethdev_driver.h>
30 #include <rte_rwlock.h>
31 #include <rte_interrupts.h>
32 #include <rte_errno.h>
35 #include "mlx5_utils.h"
37 #include "mlx5_autoconf.h"
38 #include "mlx5_defs.h"
39 #include "mlx5_glue.h"
42 PCI_VENDOR_ID_MELLANOX = 0x15b3,
46 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013,
47 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014,
48 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015,
49 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016,
50 PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017,
51 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018,
52 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019,
53 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a,
54 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF = 0xa2d2,
55 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF = 0xa2d3,
56 PCI_DEVICE_ID_MELLANOX_CONNECTX6 = 0x101b,
57 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF = 0x101c,
58 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX = 0x101d,
59 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF = 0x101e,
62 /* Request types for IPC. */
63 enum mlx5_mp_req_type {
64 MLX5_MP_REQ_VERBS_CMD_FD = 1,
65 MLX5_MP_REQ_CREATE_MR,
66 MLX5_MP_REQ_START_RXTX,
67 MLX5_MP_REQ_STOP_RXTX,
68 MLX5_MP_REQ_QUEUE_STATE_MODIFY,
71 struct mlx5_mp_arg_queue_state_modify {
72 uint8_t is_wq; /* Set if WQ. */
73 uint16_t queue_id; /* DPDK queue ID. */
74 enum ibv_wq_state state; /* WQ requested state. */
77 /* Pameters for IPC. */
78 struct mlx5_mp_param {
79 enum mlx5_mp_req_type type;
84 uintptr_t addr; /* MLX5_MP_REQ_CREATE_MR */
85 struct mlx5_mp_arg_queue_state_modify state_modify;
86 /* MLX5_MP_REQ_QUEUE_STATE_MODIFY */
90 /** Request timeout for IPC. */
91 #define MLX5_MP_REQ_TIMEOUT_SEC 5
93 /** Key string for IPC. */
94 #define MLX5_MP_NAME "net_mlx5_mp"
96 /* Recognized Infiniband device physical port name types. */
97 enum mlx5_phys_port_name_type {
98 MLX5_PHYS_PORT_NAME_TYPE_NOTSET = 0, /* Not set. */
99 MLX5_PHYS_PORT_NAME_TYPE_LEGACY, /* before kernel ver < 5.0 */
100 MLX5_PHYS_PORT_NAME_TYPE_UPLINK, /* p0, kernel ver >= 5.0 */
101 MLX5_PHYS_PORT_NAME_TYPE_PFVF, /* pf0vf0, kernel ver >= 5.0 */
102 MLX5_PHYS_PORT_NAME_TYPE_UNKNOWN, /* Unrecognized. */
105 /** Switch information returned by mlx5_nl_switch_info(). */
106 struct mlx5_switch_info {
107 uint32_t master:1; /**< Master device. */
108 uint32_t representor:1; /**< Representor device. */
109 enum mlx5_phys_port_name_type name_type; /** < Port name type. */
110 int32_t pf_num; /**< PF number (valid for pfxvfx format only). */
111 int32_t port_name; /**< Representor port name. */
112 uint64_t switch_id; /**< Switch identifier. */
115 LIST_HEAD(mlx5_dev_list, mlx5_ibv_shared);
117 /* Shared data between primary and secondary processes. */
118 struct mlx5_shared_data {
120 /* Global spinlock for primary and secondary processes. */
121 int init_done; /* Whether primary has done initialization. */
122 unsigned int secondary_cnt; /* Number of secondary processes init'd. */
123 struct mlx5_dev_list mem_event_cb_list;
124 rte_rwlock_t mem_event_rwlock;
127 /* Per-process data structure, not visible to other processes. */
128 struct mlx5_local_data {
129 int init_done; /* Whether a secondary has done initialization. */
132 extern struct mlx5_shared_data *mlx5_shared_data;
134 struct mlx5_counter_ctrl {
135 /* Name of the counter. */
136 char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE];
137 /* Name of the counter on the device table. */
138 char ctr_name[RTE_ETH_XSTATS_NAME_SIZE];
139 uint32_t ib:1; /**< Nonzero for IB counters. */
142 struct mlx5_xstats_ctrl {
143 /* Number of device stats. */
145 /* Number of device stats identified by PMD. */
146 uint16_t mlx5_stats_n;
147 /* Index in the device counters table. */
148 uint16_t dev_table_idx[MLX5_MAX_XSTATS];
149 uint64_t base[MLX5_MAX_XSTATS];
150 struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS];
153 struct mlx5_stats_ctrl {
154 /* Base for imissed counter. */
155 uint64_t imissed_base;
158 /* devX creation object */
159 struct mlx5_devx_obj {
160 struct mlx5dv_devx_obj *obj; /* The DV object. */
161 int id; /* The object ID. */
164 struct mlx5_devx_mkey_attr {
171 /* HCA supports this number of time periods for LRO. */
172 #define MLX5_LRO_NUM_SUPP_PERIODS 4
174 /* HCA attributes. */
175 struct mlx5_hca_attr {
176 uint32_t eswitch_manager:1;
177 uint32_t flow_counters_dump:1;
178 uint8_t flow_counter_bulk_alloc_bitmap;
179 uint32_t eth_net_offloads:1;
181 uint32_t wqe_vlan_insert:1;
182 uint32_t wqe_inline_mode:2;
183 uint32_t vport_inline_mode:3;
184 uint32_t tunnel_stateless_geneve_rx:1;
185 uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */
187 uint32_t tunnel_lro_gre:1;
188 uint32_t tunnel_lro_vxlan:1;
189 uint32_t lro_max_msg_sz_mode:2;
190 uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS];
191 uint32_t flex_parser_protocols;
193 uint32_t log_max_hairpin_queues:5;
194 uint32_t log_max_hairpin_wq_data_sz:5;
195 uint32_t log_max_hairpin_num_packets:5;
200 TAILQ_HEAD(mlx5_flows, rte_flow);
202 /* Default PMD specific parameter value. */
203 #define MLX5_ARG_UNSET (-1)
205 #define MLX5_LRO_SUPPORTED(dev) \
206 (((struct mlx5_priv *)((dev)->data->dev_private))->config.lro.supported)
208 /* LRO configurations structure. */
209 struct mlx5_lro_config {
210 uint32_t supported:1; /* Whether LRO is supported. */
211 uint32_t timeout; /* User configuration. */
215 * Device configuration structure.
217 * Merged configuration from:
219 * - Device capabilities,
220 * - User device parameters disabled features.
222 struct mlx5_dev_config {
223 unsigned int hw_csum:1; /* Checksum offload is supported. */
224 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */
225 unsigned int hw_vlan_insert:1; /* VLAN insertion in WQE is supported. */
226 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */
227 unsigned int hw_padding:1; /* End alignment padding is supported. */
228 unsigned int vf:1; /* This is a VF. */
229 unsigned int tunnel_en:1;
230 /* Whether tunnel stateless offloads are supported. */
231 unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */
232 unsigned int cqe_comp:1; /* CQE compression is enabled. */
233 unsigned int cqe_pad:1; /* CQE padding is enabled. */
234 unsigned int tso:1; /* Whether TSO is supported. */
235 unsigned int rx_vec_en:1; /* Rx vector is enabled. */
236 unsigned int mr_ext_memseg_en:1;
237 /* Whether memseg should be extended for MR creation. */
238 unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */
239 unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */
240 unsigned int dv_esw_en:1; /* Enable E-Switch DV flow. */
241 unsigned int dv_flow_en:1; /* Enable DV flow. */
242 unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */
243 unsigned int devx:1; /* Whether devx interface is available or not. */
244 unsigned int dest_tir:1; /* Whether advanced DR API is available. */
246 unsigned int enabled:1; /* Whether MPRQ is enabled. */
247 unsigned int stride_num_n; /* Number of strides. */
248 unsigned int min_stride_size_n; /* Min size of a stride. */
249 unsigned int max_stride_size_n; /* Max size of a stride. */
250 unsigned int max_memcpy_len;
251 /* Maximum packet size to memcpy Rx packets. */
252 unsigned int min_rxqs_num;
253 /* Rx queue count threshold to enable MPRQ. */
254 } mprq; /* Configurations for Multi-Packet RQ. */
255 int mps; /* Multi-packet send supported mode. */
256 unsigned int flow_prio; /* Number of flow priorities. */
257 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */
258 unsigned int ind_table_max_size; /* Maximum indirection table size. */
259 unsigned int max_dump_files_num; /* Maximum dump files per queue. */
260 int txqs_inline; /* Queue number threshold for inlining. */
261 int txq_inline_min; /* Minimal amount of data bytes to inline. */
262 int txq_inline_max; /* Max packet size for inlining with SEND. */
263 int txq_inline_mpw; /* Max packet size for inlining with eMPW. */
264 struct mlx5_hca_attr hca_attr; /* HCA attributes. */
265 struct mlx5_lro_config lro; /* LRO configuration. */
268 struct mlx5_devx_wq_attr {
270 uint32_t wq_signature:1;
271 uint32_t end_padding_mode:2;
273 uint32_t hds_skip_first_sge:1;
274 uint32_t log2_hds_buf_size:3;
275 uint32_t page_offset:5;
278 uint32_t uar_page:24;
282 uint32_t log_wq_stride:4;
283 uint32_t log_wq_pg_sz:5;
284 uint32_t log_wq_sz:5;
285 uint32_t dbr_umem_valid:1;
286 uint32_t wq_umem_valid:1;
287 uint32_t log_hairpin_num_packets:5;
288 uint32_t log_hairpin_data_sz:5;
289 uint32_t single_wqe_log_num_of_strides:4;
290 uint32_t two_byte_shift_en:1;
291 uint32_t single_stride_log_num_of_bytes:3;
292 uint32_t dbr_umem_id;
294 uint64_t wq_umem_offset;
297 /* Create RQ attributes structure, used by create RQ operation. */
298 struct mlx5_devx_create_rq_attr {
300 uint32_t delay_drop_en:1;
301 uint32_t scatter_fcs:1;
303 uint32_t mem_rq_type:4;
305 uint32_t flush_in_error_en:1;
307 uint32_t user_index:24;
309 uint32_t counter_set_id:8;
311 struct mlx5_devx_wq_attr wq_attr;
314 /* Modify RQ attributes structure, used by modify RQ operation. */
315 struct mlx5_devx_modify_rq_attr {
317 uint32_t rq_state:4; /* Current RQ state. */
318 uint32_t state:4; /* Required RQ state. */
319 uint32_t scatter_fcs:1;
321 uint32_t counter_set_id:8;
322 uint32_t hairpin_peer_sq:24;
323 uint32_t hairpin_peer_vhca:16;
324 uint64_t modify_bitmask;
325 uint32_t lwm:16; /* Contained WQ lwm. */
328 struct mlx5_rx_hash_field_select {
329 uint32_t l3_prot_type:1;
330 uint32_t l4_prot_type:1;
331 uint32_t selected_fields:30;
334 /* TIR attributes structure, used by TIR operations. */
335 struct mlx5_devx_tir_attr {
336 uint32_t disp_type:4;
337 uint32_t lro_timeout_period_usecs:16;
338 uint32_t lro_enable_mask:4;
339 uint32_t lro_max_msg_sz:8;
340 uint32_t inline_rqn:24;
341 uint32_t rx_hash_symmetric:1;
342 uint32_t tunneled_offload_en:1;
343 uint32_t indirect_table:24;
344 uint32_t rx_hash_fn:4;
345 uint32_t self_lb_block:2;
346 uint32_t transport_domain:24;
347 uint32_t rx_hash_toeplitz_key[10];
348 struct mlx5_rx_hash_field_select rx_hash_field_selector_outer;
349 struct mlx5_rx_hash_field_select rx_hash_field_selector_inner;
352 /* RQT attributes structure, used by RQT operations. */
353 struct mlx5_devx_rqt_attr {
354 uint32_t rqt_max_size:16;
355 uint32_t rqt_actual_size:16;
359 /* TIS attributes structure. */
360 struct mlx5_devx_tis_attr {
361 uint32_t strict_lag_tx_port_affinity:1;
363 uint32_t lag_tx_port_affinity:4;
365 uint32_t transport_domain:24;
368 /* SQ attributes structure, used by SQ create operation. */
369 struct mlx5_devx_create_sq_attr {
371 uint32_t cd_master:1;
373 uint32_t flush_in_error_en:1;
374 uint32_t allow_multi_pkt_send_wqe:1;
375 uint32_t min_wqe_inline_mode:3;
378 uint32_t allow_swp:1;
380 uint32_t user_index:24;
382 uint32_t packet_pacing_rate_limit_index:16;
383 uint32_t tis_lst_sz:16;
385 struct mlx5_devx_wq_attr wq_attr;
388 /* SQ attributes structure, used by SQ modify operation. */
389 struct mlx5_devx_modify_sq_attr {
392 uint32_t hairpin_peer_rq:24;
393 uint32_t hairpin_peer_vhca:16;
397 * Type of object being allocated.
399 enum mlx5_verbs_alloc_type {
400 MLX5_VERBS_ALLOC_TYPE_NONE,
401 MLX5_VERBS_ALLOC_TYPE_TX_QUEUE,
402 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE,
405 /* VLAN netdev for VLAN workaround. */
406 struct mlx5_vlan_dev {
408 uint32_t ifindex; /**< Own interface index. */
411 /* Structure for VF VLAN workaround. */
412 struct mlx5_vf_vlan {
418 * Array of VLAN devices created on the base of VF
419 * used for workaround in virtual environments.
421 struct mlx5_vlan_vmwa_context {
425 struct rte_eth_dev *dev;
426 struct mlx5_vlan_dev vlan_dev[4096];
430 * Verbs allocator needs a context to know in the callback which kind of
431 * resources it is allocating.
433 struct mlx5_verbs_alloc_ctx {
434 enum mlx5_verbs_alloc_type type; /* Kind of object being allocated. */
435 const void *obj; /* Pointer to the DPDK object. */
438 LIST_HEAD(mlx5_mr_list, mlx5_mr);
440 /* Flow drop context necessary due to Verbs API. */
442 struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */
443 struct mlx5_rxq_obj *rxq; /* Rx queue object. */
446 #define MLX5_COUNTERS_PER_POOL 512
447 #define MLX5_MAX_PENDING_QUERIES 4
449 struct mlx5_flow_counter_pool;
451 struct flow_counter_stats {
456 /* Counters information. */
457 struct mlx5_flow_counter {
458 TAILQ_ENTRY(mlx5_flow_counter) next;
459 /**< Pointer to the next flow counter structure. */
460 uint32_t shared:1; /**< Share counter ID with other flow rules. */
462 /**< Whether the counter was allocated by batch command. */
463 uint32_t ref_cnt:30; /**< Reference counter. */
464 uint32_t id; /**< Counter ID. */
465 union { /**< Holds the counters for the rule. */
466 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42)
467 struct ibv_counter_set *cs;
468 #elif defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
469 struct ibv_counters *cs;
471 struct mlx5_devx_obj *dcs; /**< Counter Devx object. */
472 struct mlx5_flow_counter_pool *pool; /**< The counter pool. */
475 uint64_t hits; /**< Reset value of hits packets. */
476 int64_t query_gen; /**< Generation of the last release. */
478 uint64_t bytes; /**< Reset value of bytes. */
479 void *action; /**< Pointer to the dv action. */
482 TAILQ_HEAD(mlx5_counters, mlx5_flow_counter);
484 /* Counter pool structure - query is in pool resolution. */
485 struct mlx5_flow_counter_pool {
486 TAILQ_ENTRY(mlx5_flow_counter_pool) next;
487 struct mlx5_counters counters; /* Free counter list. */
489 struct mlx5_devx_obj *min_dcs;
490 rte_atomic64_t a64_dcs;
492 /* The devx object of the minimum counter ID. */
493 rte_atomic64_t query_gen;
494 uint32_t n_counters: 16; /* Number of devx allocated counters. */
495 rte_spinlock_t sl; /* The pool lock. */
496 struct mlx5_counter_stats_raw *raw;
497 struct mlx5_counter_stats_raw *raw_hw; /* The raw on HW working. */
498 struct mlx5_flow_counter counters_raw[]; /* The pool counters memory. */
501 struct mlx5_counter_stats_raw;
503 /* Memory management structure for group of counter statistics raws. */
504 struct mlx5_counter_stats_mem_mng {
505 LIST_ENTRY(mlx5_counter_stats_mem_mng) next;
506 struct mlx5_counter_stats_raw *raws;
507 struct mlx5_devx_obj *dm;
508 struct mlx5dv_devx_umem *umem;
511 /* Raw memory structure for the counter statistics values of a pool. */
512 struct mlx5_counter_stats_raw {
513 LIST_ENTRY(mlx5_counter_stats_raw) next;
515 struct mlx5_counter_stats_mem_mng *mem_mng;
516 volatile struct flow_counter_stats *data;
519 TAILQ_HEAD(mlx5_counter_pools, mlx5_flow_counter_pool);
521 /* Container structure for counter pools. */
522 struct mlx5_pools_container {
523 rte_atomic16_t n_valid; /* Number of valid pools. */
524 uint16_t n; /* Number of pools. */
525 struct mlx5_counter_pools pool_list; /* Counter pool list. */
526 struct mlx5_flow_counter_pool **pools; /* Counter pool array. */
527 struct mlx5_counter_stats_mem_mng *init_mem_mng;
528 /* Hold the memory management for the next allocated pools raws. */
531 /* Counter global management structure. */
532 struct mlx5_flow_counter_mng {
533 uint8_t mhi[2]; /* master \ host container index. */
534 struct mlx5_pools_container ccont[2 * 2];
535 /* 2 containers for single and for batch for double-buffer. */
536 struct mlx5_counters flow_counters; /* Legacy flow counter list. */
537 uint8_t pending_queries;
540 uint8_t query_thread_on;
541 LIST_HEAD(mem_mngs, mlx5_counter_stats_mem_mng) mem_mngs;
542 LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws;
545 /* Per port data of shared IB device. */
546 struct mlx5_ibv_shared_port {
548 uint32_t devx_ih_port_id;
550 * Interrupt handler port_id. Used by shared interrupt
551 * handler to find the corresponding rte_eth device
552 * by IB port index. If value is equal or greater
553 * RTE_MAX_ETHPORTS it means there is no subhandler
554 * installed for specified IB port index.
558 /* Table structure. */
559 struct mlx5_flow_tbl_resource {
560 void *obj; /**< Pointer to DR table object. */
561 rte_atomic32_t refcnt; /**< Reference counter. */
564 #define MLX5_MAX_TABLES UINT16_MAX
565 #define MLX5_HAIRPIN_TX_TABLE (UINT16_MAX - 1)
566 #define MLX5_MAX_TABLES_FDB UINT16_MAX
568 #define MLX5_DBR_PAGE_SIZE 4096 /* Must be >= 512. */
569 #define MLX5_DBR_SIZE 8
570 #define MLX5_DBR_PER_PAGE (MLX5_DBR_PAGE_SIZE / MLX5_DBR_SIZE)
571 #define MLX5_DBR_BITMAP_SIZE (MLX5_DBR_PER_PAGE / 64)
573 struct mlx5_devx_dbr_page {
574 /* Door-bell records, must be first member in structure. */
575 uint8_t dbrs[MLX5_DBR_PAGE_SIZE];
576 LIST_ENTRY(mlx5_devx_dbr_page) next; /* Pointer to the next element. */
577 struct mlx5dv_devx_umem *umem;
578 uint32_t dbr_count; /* Number of door-bell records in use. */
579 /* 1 bit marks matching door-bell is in use. */
580 uint64_t dbr_bitmap[MLX5_DBR_BITMAP_SIZE];
583 /* ID generation structure. */
584 struct mlx5_flow_id_pool {
585 uint32_t *free_arr; /**< Pointer to the a array of free values. */
587 /**< The next index that can be used without any free elements. */
588 uint32_t *curr; /**< Pointer to the index to pop. */
589 uint32_t *last; /**< Pointer to the last element in the empty arrray. */
593 * Shared Infiniband device context for Master/Representors
594 * which belong to same IB device with multiple IB ports.
596 struct mlx5_ibv_shared {
597 LIST_ENTRY(mlx5_ibv_shared) next;
599 uint32_t devx:1; /* Opened with DV. */
600 uint32_t max_port; /* Maximal IB device port index. */
601 struct ibv_context *ctx; /* Verbs/DV context. */
602 struct ibv_pd *pd; /* Protection Domain. */
603 uint32_t pdn; /* Protection Domain number. */
604 uint32_t tdn; /* Transport Domain number. */
605 char ibdev_name[IBV_SYSFS_NAME_MAX]; /* IB device name. */
606 char ibdev_path[IBV_SYSFS_PATH_MAX]; /* IB device path for secondary */
607 struct ibv_device_attr_ex device_attr; /* Device properties. */
608 LIST_ENTRY(mlx5_ibv_shared) mem_event_cb;
609 /**< Called by memory event callback. */
611 uint32_t dev_gen; /* Generation number to flush local caches. */
612 rte_rwlock_t rwlock; /* MR Lock. */
613 struct mlx5_mr_btree cache; /* Global MR cache table. */
614 struct mlx5_mr_list mr_list; /* Registered MR list. */
615 struct mlx5_mr_list mr_free_list; /* Freed MR list. */
617 /* Shared DV/DR flow data section. */
618 pthread_mutex_t dv_mutex; /* DV context mutex. */
619 uint32_t dv_refcnt; /* DV/DR data reference counter. */
620 void *fdb_domain; /* FDB Direct Rules name space handle. */
621 struct mlx5_flow_tbl_resource fdb_tbl[MLX5_MAX_TABLES_FDB];
622 /* FDB Direct Rules tables. */
623 void *rx_domain; /* RX Direct Rules name space handle. */
624 struct mlx5_flow_tbl_resource rx_tbl[MLX5_MAX_TABLES];
625 /* RX Direct Rules tables. */
626 void *tx_domain; /* TX Direct Rules name space handle. */
627 struct mlx5_flow_tbl_resource tx_tbl[MLX5_MAX_TABLES];
628 /* TX Direct Rules tables. */
629 void *esw_drop_action; /* Pointer to DR E-Switch drop action. */
630 void *pop_vlan_action; /* Pointer to DR pop VLAN action. */
631 /* TX Direct Rules tables/ */
632 LIST_HEAD(matchers, mlx5_flow_dv_matcher) matchers;
633 LIST_HEAD(encap_decap, mlx5_flow_dv_encap_decap_resource) encaps_decaps;
634 LIST_HEAD(modify_cmd, mlx5_flow_dv_modify_hdr_resource) modify_cmds;
635 LIST_HEAD(tag, mlx5_flow_dv_tag_resource) tags;
636 LIST_HEAD(jump, mlx5_flow_dv_jump_tbl_resource) jump_tbl;
637 LIST_HEAD(port_id_action_list, mlx5_flow_dv_port_id_action_resource)
638 port_id_action_list; /* List of port ID actions. */
639 LIST_HEAD(push_vlan_action_list, mlx5_flow_dv_push_vlan_action_resource)
640 push_vlan_action_list; /* List of push VLAN actions. */
641 struct mlx5_flow_counter_mng cmng; /* Counters management structure. */
642 /* Shared interrupt handler section. */
643 pthread_mutex_t intr_mutex; /* Interrupt config mutex. */
644 uint32_t intr_cnt; /* Interrupt handler reference counter. */
645 struct rte_intr_handle intr_handle; /* Interrupt handler for device. */
646 uint32_t devx_intr_cnt; /* Devx interrupt handler reference counter. */
647 struct rte_intr_handle intr_handle_devx; /* DEVX interrupt handler. */
648 struct mlx5dv_devx_cmd_comp *devx_comp; /* DEVX async comp obj. */
649 struct mlx5_devx_obj *tis; /* TIS object. */
650 struct mlx5_devx_obj *td; /* Transport domain. */
651 struct mlx5_flow_id_pool *flow_id_pool; /* Flow ID pool. */
652 struct mlx5_ibv_shared_port port[]; /* per device port data array. */
655 /* Per-process private structure. */
656 struct mlx5_proc_priv {
658 /* Size of UAR register table. */
660 /* Table of UAR registers for each process. */
663 #define MLX5_PROC_PRIV(port_id) \
664 ((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private)
667 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */
668 struct mlx5_ibv_shared *sh; /* Shared IB device context. */
669 uint32_t ibv_port; /* IB device port number. */
670 struct rte_pci_device *pci_dev; /* Backend PCI device. */
671 struct rte_ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */
672 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES);
673 /* Bit-field of MAC addresses owned by the PMD. */
674 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */
675 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */
676 /* Device properties. */
677 uint16_t mtu; /* Configured MTU. */
678 unsigned int isolated:1; /* Whether isolated mode is enabled. */
679 unsigned int representor:1; /* Device is a port representor. */
680 unsigned int master:1; /* Device is a E-Switch master. */
681 unsigned int dr_shared:1; /* DV/DR data is shared. */
682 unsigned int counter_fallback:1; /* Use counter fallback management. */
683 uint16_t domain_id; /* Switch domain identifier. */
684 uint16_t vport_id; /* Associated VF vport index (if any). */
685 uint32_t vport_meta_tag; /* Used for vport index match ove VF LAG. */
686 uint32_t vport_meta_mask; /* Used for vport index field match mask. */
687 int32_t representor_id; /* Port representor identifier. */
688 int32_t pf_bond; /* >=0 means PF index in bonding configuration. */
689 unsigned int if_index; /* Associated kernel network device index. */
691 unsigned int rxqs_n; /* RX queues array size. */
692 unsigned int txqs_n; /* TX queues array size. */
693 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */
694 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */
695 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
696 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */
697 unsigned int (*reta_idx)[]; /* RETA index table. */
698 unsigned int reta_idx_n; /* RETA index size. */
699 struct mlx5_drop drop_queue; /* Flow drop queues. */
700 struct mlx5_flows flows; /* RTE Flow rules. */
701 struct mlx5_flows ctrl_flows; /* Control flow rules. */
702 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */
703 LIST_HEAD(rxqobj, mlx5_rxq_obj) rxqsobj; /* Verbs/DevX Rx queues. */
704 LIST_HEAD(hrxq, mlx5_hrxq) hrxqs; /* Verbs Hash Rx queues. */
705 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */
706 LIST_HEAD(txqobj, mlx5_txq_obj) txqsobj; /* Verbs/DevX Tx queues. */
707 /* Indirection tables. */
708 LIST_HEAD(ind_tables, mlx5_ind_table_obj) ind_tbls;
709 /* Pointer to next element. */
710 rte_atomic32_t refcnt; /**< Reference counter. */
711 struct ibv_flow_action *verbs_action;
712 /**< Verbs modify header action object. */
713 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
714 uint8_t max_lro_msg_size;
715 /* Tags resources cache. */
716 uint32_t link_speed_capa; /* Link speed capabilities. */
717 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */
718 struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */
719 struct mlx5_dev_config config; /* Device configuration. */
720 struct mlx5_verbs_alloc_ctx verbs_alloc_ctx;
721 /* Context for Verbs allocator. */
722 int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */
723 int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */
724 uint32_t nl_sn; /* Netlink message sequence number. */
725 LIST_HEAD(dbrpage, mlx5_devx_dbr_page) dbrpgs; /* Door-bell pages. */
726 struct mlx5_vlan_vmwa_context *vmwa_context; /* VLAN WA context. */
728 rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */
729 rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX];
730 /* UAR same-page access control required in 32bit implementations. */
732 uint8_t skip_default_rss_reta; /* Skip configuration of default reta. */
735 #define PORT_ID(priv) ((priv)->dev_data->port_id)
736 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)])
740 int mlx5_getenv_int(const char *);
741 int mlx5_proc_priv_init(struct rte_eth_dev *dev);
742 int64_t mlx5_get_dbr(struct rte_eth_dev *dev,
743 struct mlx5_devx_dbr_page **dbr_page);
744 int32_t mlx5_release_dbr(struct rte_eth_dev *dev, uint32_t umem_id,
746 int mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev,
747 struct rte_eth_udp_tunnel *udp_tunnel);
748 uint16_t mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev);
750 /* Macro to iterate over all valid ports for mlx5 driver. */
751 #define MLX5_ETH_FOREACH_DEV(port_id, pci_dev) \
752 for (port_id = mlx5_eth_find_next(0, pci_dev); \
753 port_id < RTE_MAX_ETHPORTS; \
754 port_id = mlx5_eth_find_next(port_id + 1, pci_dev))
758 int mlx5_get_ifname(const struct rte_eth_dev *dev, char (*ifname)[IF_NAMESIZE]);
759 int mlx5_get_master_ifname(const char *ibdev_path, char (*ifname)[IF_NAMESIZE]);
760 unsigned int mlx5_ifindex(const struct rte_eth_dev *dev);
761 int mlx5_ifreq(const struct rte_eth_dev *dev, int req, struct ifreq *ifr);
762 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu);
763 int mlx5_set_flags(struct rte_eth_dev *dev, unsigned int keep,
765 int mlx5_dev_configure(struct rte_eth_dev *dev);
766 int mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info);
767 int mlx5_read_clock(struct rte_eth_dev *dev, uint64_t *clock);
768 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size);
769 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev);
770 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete);
771 int mlx5_force_link_status_change(struct rte_eth_dev *dev, int status);
772 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
773 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev,
774 struct rte_eth_fc_conf *fc_conf);
775 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev,
776 struct rte_eth_fc_conf *fc_conf);
777 int mlx5_dev_to_pci_addr(const char *dev_path,
778 struct rte_pci_addr *pci_addr);
779 void mlx5_dev_link_status_handler(void *arg);
780 void mlx5_dev_interrupt_handler(void *arg);
781 void mlx5_dev_interrupt_handler_devx(void *arg);
782 void mlx5_dev_interrupt_handler_uninstall(struct rte_eth_dev *dev);
783 void mlx5_dev_interrupt_handler_install(struct rte_eth_dev *dev);
784 void mlx5_dev_interrupt_handler_devx_uninstall(struct rte_eth_dev *dev);
785 void mlx5_dev_interrupt_handler_devx_install(struct rte_eth_dev *dev);
786 int mlx5_set_link_down(struct rte_eth_dev *dev);
787 int mlx5_set_link_up(struct rte_eth_dev *dev);
788 int mlx5_is_removed(struct rte_eth_dev *dev);
789 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev);
790 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev);
791 struct mlx5_priv *mlx5_port_to_eswitch_info(uint16_t port);
792 struct mlx5_priv *mlx5_dev_to_eswitch_info(struct rte_eth_dev *dev);
793 int mlx5_sysfs_switch_info(unsigned int ifindex,
794 struct mlx5_switch_info *info);
795 void mlx5_sysfs_check_switch_info(bool device_dir,
796 struct mlx5_switch_info *switch_info);
797 void mlx5_nl_check_switch_info(bool nun_vf_set,
798 struct mlx5_switch_info *switch_info);
799 void mlx5_translate_port_name(const char *port_name_in,
800 struct mlx5_switch_info *port_info_out);
801 void mlx5_intr_callback_unregister(const struct rte_intr_handle *handle,
802 rte_intr_callback_fn cb_fn, void *cb_arg);
803 int mlx5_get_module_info(struct rte_eth_dev *dev,
804 struct rte_eth_dev_module_info *modinfo);
805 int mlx5_get_module_eeprom(struct rte_eth_dev *dev,
806 struct rte_dev_eeprom_info *info);
807 int mlx5_hairpin_cap_get(struct rte_eth_dev *dev,
808 struct rte_eth_hairpin_cap *cap);
809 int mlx5_dev_configure_rss_reta(struct rte_eth_dev *dev);
813 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]);
814 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
815 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
816 uint32_t index, uint32_t vmdq);
817 int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr);
818 int mlx5_set_mc_addr_list(struct rte_eth_dev *dev,
819 struct rte_ether_addr *mc_addr_set,
820 uint32_t nb_mc_addr);
824 int mlx5_rss_hash_update(struct rte_eth_dev *dev,
825 struct rte_eth_rss_conf *rss_conf);
826 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev,
827 struct rte_eth_rss_conf *rss_conf);
828 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size);
829 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev,
830 struct rte_eth_rss_reta_entry64 *reta_conf,
832 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev,
833 struct rte_eth_rss_reta_entry64 *reta_conf,
838 int mlx5_promiscuous_enable(struct rte_eth_dev *dev);
839 int mlx5_promiscuous_disable(struct rte_eth_dev *dev);
840 int mlx5_allmulticast_enable(struct rte_eth_dev *dev);
841 int mlx5_allmulticast_disable(struct rte_eth_dev *dev);
845 void mlx5_stats_init(struct rte_eth_dev *dev);
846 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
847 int mlx5_stats_reset(struct rte_eth_dev *dev);
848 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats,
850 int mlx5_xstats_reset(struct rte_eth_dev *dev);
851 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
852 struct rte_eth_xstat_name *xstats_names,
857 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
858 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on);
859 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask);
863 int mlx5_dev_start(struct rte_eth_dev *dev);
864 void mlx5_dev_stop(struct rte_eth_dev *dev);
865 int mlx5_traffic_enable(struct rte_eth_dev *dev);
866 void mlx5_traffic_disable(struct rte_eth_dev *dev);
867 int mlx5_traffic_restart(struct rte_eth_dev *dev);
871 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
872 void mlx5_flow_print(struct rte_flow *flow);
873 int mlx5_flow_validate(struct rte_eth_dev *dev,
874 const struct rte_flow_attr *attr,
875 const struct rte_flow_item items[],
876 const struct rte_flow_action actions[],
877 struct rte_flow_error *error);
878 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev,
879 const struct rte_flow_attr *attr,
880 const struct rte_flow_item items[],
881 const struct rte_flow_action actions[],
882 struct rte_flow_error *error);
883 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow,
884 struct rte_flow_error *error);
885 void mlx5_flow_list_flush(struct rte_eth_dev *dev, struct mlx5_flows *list);
886 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error);
887 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow,
888 const struct rte_flow_action *action, void *data,
889 struct rte_flow_error *error);
890 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable,
891 struct rte_flow_error *error);
892 int mlx5_dev_filter_ctrl(struct rte_eth_dev *dev,
893 enum rte_filter_type filter_type,
894 enum rte_filter_op filter_op,
896 int mlx5_flow_start(struct rte_eth_dev *dev, struct mlx5_flows *list);
897 void mlx5_flow_stop(struct rte_eth_dev *dev, struct mlx5_flows *list);
898 int mlx5_flow_verify(struct rte_eth_dev *dev);
899 int mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, uint32_t queue);
900 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev,
901 struct rte_flow_item_eth *eth_spec,
902 struct rte_flow_item_eth *eth_mask,
903 struct rte_flow_item_vlan *vlan_spec,
904 struct rte_flow_item_vlan *vlan_mask);
905 int mlx5_ctrl_flow(struct rte_eth_dev *dev,
906 struct rte_flow_item_eth *eth_spec,
907 struct rte_flow_item_eth *eth_mask);
908 struct rte_flow *mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev);
909 int mlx5_flow_create_drop_queue(struct rte_eth_dev *dev);
910 void mlx5_flow_delete_drop_queue(struct rte_eth_dev *dev);
911 void mlx5_flow_async_pool_query_handle(struct mlx5_ibv_shared *sh,
912 uint64_t async_id, int status);
913 void mlx5_set_query_alarm(struct mlx5_ibv_shared *sh);
914 void mlx5_flow_query_alarm(void *arg);
917 void mlx5_mp_req_start_rxtx(struct rte_eth_dev *dev);
918 void mlx5_mp_req_stop_rxtx(struct rte_eth_dev *dev);
919 int mlx5_mp_req_mr_create(struct rte_eth_dev *dev, uintptr_t addr);
920 int mlx5_mp_req_verbs_cmd_fd(struct rte_eth_dev *dev);
921 int mlx5_mp_req_queue_state_modify(struct rte_eth_dev *dev,
922 struct mlx5_mp_arg_queue_state_modify *sm);
923 int mlx5_mp_init_primary(void);
924 void mlx5_mp_uninit_primary(void);
925 int mlx5_mp_init_secondary(void);
926 void mlx5_mp_uninit_secondary(void);
930 int mlx5_nl_init(int protocol);
931 int mlx5_nl_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
933 int mlx5_nl_mac_addr_remove(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
935 void mlx5_nl_mac_addr_sync(struct rte_eth_dev *dev);
936 void mlx5_nl_mac_addr_flush(struct rte_eth_dev *dev);
937 int mlx5_nl_promisc(struct rte_eth_dev *dev, int enable);
938 int mlx5_nl_allmulti(struct rte_eth_dev *dev, int enable);
939 unsigned int mlx5_nl_portnum(int nl, const char *name);
940 unsigned int mlx5_nl_ifindex(int nl, const char *name, uint32_t pindex);
941 int mlx5_nl_switch_info(int nl, unsigned int ifindex,
942 struct mlx5_switch_info *info);
944 struct mlx5_vlan_vmwa_context *mlx5_vlan_vmwa_init(struct rte_eth_dev *dev,
946 void mlx5_vlan_vmwa_exit(struct mlx5_vlan_vmwa_context *ctx);
947 void mlx5_vlan_vmwa_release(struct rte_eth_dev *dev,
948 struct mlx5_vf_vlan *vf_vlan);
949 void mlx5_vlan_vmwa_acquire(struct rte_eth_dev *dev,
950 struct mlx5_vf_vlan *vf_vlan);
952 /* mlx5_devx_cmds.c */
954 struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(struct ibv_context *ctx,
956 int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj);
957 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
958 int clear, uint32_t n_counters,
959 uint64_t *pkts, uint64_t *bytes,
960 uint32_t mkey, void *addr,
961 struct mlx5dv_devx_cmd_comp *cmd_comp,
963 int mlx5_devx_cmd_query_hca_attr(struct ibv_context *ctx,
964 struct mlx5_hca_attr *attr);
965 struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(struct ibv_context *ctx,
966 struct mlx5_devx_mkey_attr *attr);
967 int mlx5_devx_get_out_command_status(void *out);
968 int mlx5_devx_cmd_qp_query_tis_td(struct ibv_qp *qp, uint32_t tis_num,
970 struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(struct ibv_context *ctx,
971 struct mlx5_devx_create_rq_attr *rq_attr,
973 int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
974 struct mlx5_devx_modify_rq_attr *rq_attr);
975 struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(struct ibv_context *ctx,
976 struct mlx5_devx_tir_attr *tir_attr);
977 struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(struct ibv_context *ctx,
978 struct mlx5_devx_rqt_attr *rqt_attr);
979 struct mlx5_devx_obj *mlx5_devx_cmd_create_sq
980 (struct ibv_context *ctx, struct mlx5_devx_create_sq_attr *sq_attr);
981 int mlx5_devx_cmd_modify_sq
982 (struct mlx5_devx_obj *sq, struct mlx5_devx_modify_sq_attr *sq_attr);
983 struct mlx5_devx_obj *mlx5_devx_cmd_create_tis
984 (struct ibv_context *ctx, struct mlx5_devx_tis_attr *tis_attr);
985 struct mlx5_devx_obj *mlx5_devx_cmd_create_td(struct ibv_context *ctx);
987 #endif /* RTE_PMD_MLX5_H_ */