1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_H_
7 #define RTE_PMD_MLX5_H_
14 #include <netinet/in.h>
15 #include <sys/queue.h>
18 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
20 #pragma GCC diagnostic ignored "-Wpedantic"
22 #include <infiniband/verbs.h>
24 #pragma GCC diagnostic error "-Wpedantic"
28 #include <rte_ether.h>
29 #include <rte_ethdev_driver.h>
30 #include <rte_rwlock.h>
31 #include <rte_interrupts.h>
32 #include <rte_errno.h>
35 #include <mlx5_glue.h>
36 #include <mlx5_devx_cmds.h>
39 #include <mlx5_common_mp.h>
40 #include <mlx5_common_mr.h>
42 #include "mlx5_defs.h"
43 #include "mlx5_utils.h"
44 #include "mlx5_autoconf.h"
47 enum mlx5_ipool_index {
48 MLX5_IPOOL_DECAP_ENCAP = 0, /* Pool for encap/decap resource. */
49 MLX5_IPOOL_PUSH_VLAN, /* Pool for push vlan resource. */
50 MLX5_IPOOL_TAG, /* Pool for tag resource. */
51 MLX5_IPOOL_PORT_ID, /* Pool for port id resource. */
52 MLX5_IPOOL_JUMP, /* Pool for jump resource. */
56 /** Key string for IPC. */
57 #define MLX5_MP_NAME "net_mlx5_mp"
60 LIST_HEAD(mlx5_dev_list, mlx5_ibv_shared);
62 /* Shared data between primary and secondary processes. */
63 struct mlx5_shared_data {
65 /* Global spinlock for primary and secondary processes. */
66 int init_done; /* Whether primary has done initialization. */
67 unsigned int secondary_cnt; /* Number of secondary processes init'd. */
68 struct mlx5_dev_list mem_event_cb_list;
69 rte_rwlock_t mem_event_rwlock;
72 /* Per-process data structure, not visible to other processes. */
73 struct mlx5_local_data {
74 int init_done; /* Whether a secondary has done initialization. */
77 extern struct mlx5_shared_data *mlx5_shared_data;
79 struct mlx5_counter_ctrl {
80 /* Name of the counter. */
81 char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE];
82 /* Name of the counter on the device table. */
83 char ctr_name[RTE_ETH_XSTATS_NAME_SIZE];
84 uint32_t ib:1; /**< Nonzero for IB counters. */
87 struct mlx5_xstats_ctrl {
88 /* Number of device stats. */
90 /* Number of device stats identified by PMD. */
91 uint16_t mlx5_stats_n;
92 /* Index in the device counters table. */
93 uint16_t dev_table_idx[MLX5_MAX_XSTATS];
94 uint64_t base[MLX5_MAX_XSTATS];
95 uint64_t xstats[MLX5_MAX_XSTATS];
96 uint64_t hw_stats[MLX5_MAX_XSTATS];
97 struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS];
100 struct mlx5_stats_ctrl {
101 /* Base for imissed counter. */
102 uint64_t imissed_base;
107 TAILQ_HEAD(mlx5_flows, rte_flow);
109 /* Default PMD specific parameter value. */
110 #define MLX5_ARG_UNSET (-1)
112 #define MLX5_LRO_SUPPORTED(dev) \
113 (((struct mlx5_priv *)((dev)->data->dev_private))->config.lro.supported)
115 /* Maximal size of coalesced segment for LRO is set in chunks of 256 Bytes. */
116 #define MLX5_LRO_SEG_CHUNK_SIZE 256u
118 /* Maximal size of aggregated LRO packet. */
119 #define MLX5_MAX_LRO_SIZE (UINT8_MAX * MLX5_LRO_SEG_CHUNK_SIZE)
121 /* LRO configurations structure. */
122 struct mlx5_lro_config {
123 uint32_t supported:1; /* Whether LRO is supported. */
124 uint32_t timeout; /* User configuration. */
128 * Device configuration structure.
130 * Merged configuration from:
132 * - Device capabilities,
133 * - User device parameters disabled features.
135 struct mlx5_dev_config {
136 unsigned int hw_csum:1; /* Checksum offload is supported. */
137 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */
138 unsigned int hw_vlan_insert:1; /* VLAN insertion in WQE is supported. */
139 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */
140 unsigned int hw_padding:1; /* End alignment padding is supported. */
141 unsigned int vf:1; /* This is a VF. */
142 unsigned int tunnel_en:1;
143 /* Whether tunnel stateless offloads are supported. */
144 unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */
145 unsigned int cqe_comp:1; /* CQE compression is enabled. */
146 unsigned int cqe_pad:1; /* CQE padding is enabled. */
147 unsigned int tso:1; /* Whether TSO is supported. */
148 unsigned int rx_vec_en:1; /* Rx vector is enabled. */
149 unsigned int mr_ext_memseg_en:1;
150 /* Whether memseg should be extended for MR creation. */
151 unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */
152 unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */
153 unsigned int dv_esw_en:1; /* Enable E-Switch DV flow. */
154 unsigned int dv_flow_en:1; /* Enable DV flow. */
155 unsigned int dv_xmeta_en:2; /* Enable extensive flow metadata. */
156 unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */
157 unsigned int devx:1; /* Whether devx interface is available or not. */
158 unsigned int dest_tir:1; /* Whether advanced DR API is available. */
160 unsigned int enabled:1; /* Whether MPRQ is enabled. */
161 unsigned int stride_num_n; /* Number of strides. */
162 unsigned int stride_size_n; /* Size of a stride. */
163 unsigned int min_stride_size_n; /* Min size of a stride. */
164 unsigned int max_stride_size_n; /* Max size of a stride. */
165 unsigned int max_memcpy_len;
166 /* Maximum packet size to memcpy Rx packets. */
167 unsigned int min_rxqs_num;
168 /* Rx queue count threshold to enable MPRQ. */
169 } mprq; /* Configurations for Multi-Packet RQ. */
170 int mps; /* Multi-packet send supported mode. */
171 int dbnc; /* Skip doorbell register write barrier. */
172 unsigned int flow_prio; /* Number of flow priorities. */
173 enum modify_reg flow_mreg_c[MLX5_MREG_C_NUM];
174 /* Availibility of mreg_c's. */
175 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */
176 unsigned int ind_table_max_size; /* Maximum indirection table size. */
177 unsigned int max_dump_files_num; /* Maximum dump files per queue. */
178 unsigned int log_hp_size; /* Single hairpin queue data size in total. */
179 int txqs_inline; /* Queue number threshold for inlining. */
180 int txq_inline_min; /* Minimal amount of data bytes to inline. */
181 int txq_inline_max; /* Max packet size for inlining with SEND. */
182 int txq_inline_mpw; /* Max packet size for inlining with eMPW. */
183 struct mlx5_hca_attr hca_attr; /* HCA attributes. */
184 struct mlx5_lro_config lro; /* LRO configuration. */
189 * Type of object being allocated.
191 enum mlx5_verbs_alloc_type {
192 MLX5_VERBS_ALLOC_TYPE_NONE,
193 MLX5_VERBS_ALLOC_TYPE_TX_QUEUE,
194 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE,
197 /* Structure for VF VLAN workaround. */
198 struct mlx5_vf_vlan {
204 * Verbs allocator needs a context to know in the callback which kind of
205 * resources it is allocating.
207 struct mlx5_verbs_alloc_ctx {
208 enum mlx5_verbs_alloc_type type; /* Kind of object being allocated. */
209 const void *obj; /* Pointer to the DPDK object. */
212 /* Flow drop context necessary due to Verbs API. */
214 struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */
215 struct mlx5_rxq_obj *rxq; /* Rx queue object. */
218 #define MLX5_COUNTERS_PER_POOL 512
219 #define MLX5_MAX_PENDING_QUERIES 4
220 #define MLX5_CNT_CONTAINER_RESIZE 64
222 * The pool index and offset of counter in the pool array makes up the
223 * counter index. In case the counter is from pool 0 and offset 0, it
224 * should plus 1 to avoid index 0, since 0 means invalid counter index
227 #define MLX5_MAKE_CNT_IDX(pi, offset) \
228 ((pi) * MLX5_COUNTERS_PER_POOL + (offset) + 1)
229 #define MLX5_CNT_TO_CNT_EXT(pool, cnt) (&((struct mlx5_flow_counter_ext *) \
230 ((pool) + 1))[((cnt) - (pool)->counters_raw)])
231 #define MLX5_GET_POOL_CNT_EXT(pool, offset) \
232 (&((struct mlx5_flow_counter_ext *) \
233 ((pool) + 1))[offset])
235 struct mlx5_flow_counter_pool;
237 struct flow_counter_stats {
242 /* Generic counters information. */
243 struct mlx5_flow_counter {
244 TAILQ_ENTRY(mlx5_flow_counter) next;
245 /**< Pointer to the next flow counter structure. */
247 uint64_t hits; /**< Reset value of hits packets. */
248 int64_t query_gen; /**< Generation of the last release. */
250 uint64_t bytes; /**< Reset value of bytes. */
251 void *action; /**< Pointer to the dv action. */
254 /* Extend counters information for none batch counters. */
255 struct mlx5_flow_counter_ext {
256 uint32_t shared:1; /**< Share counter ID with other flow rules. */
258 /**< Whether the counter was allocated by batch command. */
259 uint32_t ref_cnt:30; /**< Reference counter. */
260 uint32_t id; /**< User counter ID. */
261 union { /**< Holds the counters for the rule. */
262 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42)
263 struct ibv_counter_set *cs;
264 #elif defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
265 struct ibv_counters *cs;
267 struct mlx5_devx_obj *dcs; /**< Counter Devx object. */
272 TAILQ_HEAD(mlx5_counters, mlx5_flow_counter);
274 /* Generic counter pool structure - query is in pool resolution. */
275 struct mlx5_flow_counter_pool {
276 TAILQ_ENTRY(mlx5_flow_counter_pool) next;
277 struct mlx5_counters counters; /* Free counter list. */
279 struct mlx5_devx_obj *min_dcs;
280 rte_atomic64_t a64_dcs;
282 /* The devx object of the minimum counter ID. */
283 rte_atomic64_t start_query_gen; /* Query start round. */
284 rte_atomic64_t end_query_gen; /* Query end round. */
285 uint32_t index; /* Pool index in container. */
286 rte_spinlock_t sl; /* The pool lock. */
287 struct mlx5_counter_stats_raw *raw;
288 struct mlx5_counter_stats_raw *raw_hw; /* The raw on HW working. */
289 struct mlx5_flow_counter counters_raw[MLX5_COUNTERS_PER_POOL];
290 /* The pool counters memory. */
293 struct mlx5_counter_stats_raw;
295 /* Memory management structure for group of counter statistics raws. */
296 struct mlx5_counter_stats_mem_mng {
297 LIST_ENTRY(mlx5_counter_stats_mem_mng) next;
298 struct mlx5_counter_stats_raw *raws;
299 struct mlx5_devx_obj *dm;
300 struct mlx5dv_devx_umem *umem;
303 /* Raw memory structure for the counter statistics values of a pool. */
304 struct mlx5_counter_stats_raw {
305 LIST_ENTRY(mlx5_counter_stats_raw) next;
307 struct mlx5_counter_stats_mem_mng *mem_mng;
308 volatile struct flow_counter_stats *data;
311 TAILQ_HEAD(mlx5_counter_pools, mlx5_flow_counter_pool);
313 /* Container structure for counter pools. */
314 struct mlx5_pools_container {
315 rte_atomic16_t n_valid; /* Number of valid pools. */
316 uint16_t n; /* Number of pools. */
317 struct mlx5_counter_pools pool_list; /* Counter pool list. */
318 struct mlx5_flow_counter_pool **pools; /* Counter pool array. */
319 struct mlx5_counter_stats_mem_mng *init_mem_mng;
320 /* Hold the memory management for the next allocated pools raws. */
323 /* Counter global management structure. */
324 struct mlx5_flow_counter_mng {
325 uint8_t mhi[2]; /* master \ host container index. */
326 struct mlx5_pools_container ccont[2 * 2];
327 /* 2 containers for single and for batch for double-buffer. */
328 struct mlx5_counters flow_counters; /* Legacy flow counter list. */
329 uint8_t pending_queries;
332 uint8_t query_thread_on;
333 LIST_HEAD(mem_mngs, mlx5_counter_stats_mem_mng) mem_mngs;
334 LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws;
337 /* Per port data of shared IB device. */
338 struct mlx5_ibv_shared_port {
340 uint32_t devx_ih_port_id;
342 * Interrupt handler port_id. Used by shared interrupt
343 * handler to find the corresponding rte_eth device
344 * by IB port index. If value is equal or greater
345 * RTE_MAX_ETHPORTS it means there is no subhandler
346 * installed for specified IB port index.
350 /* Table key of the hash organization. */
351 union mlx5_flow_tbl_key {
353 /* Table ID should be at the lowest address. */
354 uint32_t table_id; /**< ID of the table. */
355 uint16_t reserved; /**< must be zero for comparison. */
356 uint8_t domain; /**< 1 - FDB, 0 - NIC TX/RX. */
357 uint8_t direction; /**< 1 - egress, 0 - ingress. */
359 uint64_t v64; /**< full 64bits value of key */
362 /* Table structure. */
363 struct mlx5_flow_tbl_resource {
364 void *obj; /**< Pointer to DR table object. */
365 rte_atomic32_t refcnt; /**< Reference counter. */
368 #define MLX5_MAX_TABLES UINT16_MAX
369 #define MLX5_FLOW_TABLE_LEVEL_METER (UINT16_MAX - 3)
370 #define MLX5_FLOW_TABLE_LEVEL_SUFFIX (UINT16_MAX - 2)
371 #define MLX5_HAIRPIN_TX_TABLE (UINT16_MAX - 1)
372 /* Reserve the last two tables for metadata register copy. */
373 #define MLX5_FLOW_MREG_ACT_TABLE_GROUP (MLX5_MAX_TABLES - 1)
374 #define MLX5_FLOW_MREG_CP_TABLE_GROUP (MLX5_MAX_TABLES - 2)
375 /* Tables for metering splits should be added here. */
376 #define MLX5_MAX_TABLES_EXTERNAL (MLX5_MAX_TABLES - 3)
377 #define MLX5_MAX_TABLES_FDB UINT16_MAX
379 #define MLX5_DBR_PAGE_SIZE 4096 /* Must be >= 512. */
380 #define MLX5_DBR_SIZE 8
381 #define MLX5_DBR_PER_PAGE (MLX5_DBR_PAGE_SIZE / MLX5_DBR_SIZE)
382 #define MLX5_DBR_BITMAP_SIZE (MLX5_DBR_PER_PAGE / 64)
384 struct mlx5_devx_dbr_page {
385 /* Door-bell records, must be first member in structure. */
386 uint8_t dbrs[MLX5_DBR_PAGE_SIZE];
387 LIST_ENTRY(mlx5_devx_dbr_page) next; /* Pointer to the next element. */
388 struct mlx5dv_devx_umem *umem;
389 uint32_t dbr_count; /* Number of door-bell records in use. */
390 /* 1 bit marks matching door-bell is in use. */
391 uint64_t dbr_bitmap[MLX5_DBR_BITMAP_SIZE];
394 /* ID generation structure. */
395 struct mlx5_flow_id_pool {
396 uint32_t *free_arr; /**< Pointer to the a array of free values. */
398 /**< The next index that can be used without any free elements. */
399 uint32_t *curr; /**< Pointer to the index to pop. */
400 uint32_t *last; /**< Pointer to the last element in the empty arrray. */
401 uint32_t max_id; /**< Maximum id can be allocated from the pool. */
405 * Shared Infiniband device context for Master/Representors
406 * which belong to same IB device with multiple IB ports.
408 struct mlx5_ibv_shared {
409 LIST_ENTRY(mlx5_ibv_shared) next;
411 uint32_t devx:1; /* Opened with DV. */
412 uint32_t max_port; /* Maximal IB device port index. */
413 struct ibv_context *ctx; /* Verbs/DV context. */
414 struct ibv_pd *pd; /* Protection Domain. */
415 uint32_t pdn; /* Protection Domain number. */
416 uint32_t tdn; /* Transport Domain number. */
417 char ibdev_name[IBV_SYSFS_NAME_MAX]; /* IB device name. */
418 char ibdev_path[IBV_SYSFS_PATH_MAX]; /* IB device path for secondary */
419 struct ibv_device_attr_ex device_attr; /* Device properties. */
420 LIST_ENTRY(mlx5_ibv_shared) mem_event_cb;
421 /**< Called by memory event callback. */
422 struct mlx5_mr_share_cache share_cache;
423 /* Shared DV/DR flow data section. */
424 pthread_mutex_t dv_mutex; /* DV context mutex. */
425 uint32_t dv_meta_mask; /* flow META metadata supported mask. */
426 uint32_t dv_mark_mask; /* flow MARK metadata supported mask. */
427 uint32_t dv_regc0_mask; /* available bits of metatada reg_c[0]. */
428 uint32_t dv_refcnt; /* DV/DR data reference counter. */
429 void *fdb_domain; /* FDB Direct Rules name space handle. */
430 void *rx_domain; /* RX Direct Rules name space handle. */
431 void *tx_domain; /* TX Direct Rules name space handle. */
432 struct mlx5_hlist *flow_tbls;
433 /* Direct Rules tables for FDB, NIC TX+RX */
434 void *esw_drop_action; /* Pointer to DR E-Switch drop action. */
435 void *pop_vlan_action; /* Pointer to DR pop VLAN action. */
436 uint32_t encaps_decaps; /* Encap/decap action indexed memory list. */
437 LIST_HEAD(modify_cmd, mlx5_flow_dv_modify_hdr_resource) modify_cmds;
438 struct mlx5_hlist *tag_table;
439 uint32_t port_id_action_list; /* List of port ID actions. */
440 uint32_t push_vlan_action_list; /* List of push VLAN actions. */
441 struct mlx5_flow_counter_mng cmng; /* Counters management structure. */
442 struct mlx5_indexed_pool *ipool[MLX5_IPOOL_MAX];
443 /* Memory Pool for mlx5 flow resources. */
444 /* Shared interrupt handler section. */
445 pthread_mutex_t intr_mutex; /* Interrupt config mutex. */
446 uint32_t intr_cnt; /* Interrupt handler reference counter. */
447 struct rte_intr_handle intr_handle; /* Interrupt handler for device. */
448 uint32_t devx_intr_cnt; /* Devx interrupt handler reference counter. */
449 struct rte_intr_handle intr_handle_devx; /* DEVX interrupt handler. */
450 struct mlx5dv_devx_cmd_comp *devx_comp; /* DEVX async comp obj. */
451 struct mlx5_devx_obj *tis; /* TIS object. */
452 struct mlx5_devx_obj *td; /* Transport domain. */
453 struct mlx5_flow_id_pool *flow_id_pool; /* Flow ID pool. */
454 struct mlx5_ibv_shared_port port[]; /* per device port data array. */
457 /* Per-process private structure. */
458 struct mlx5_proc_priv {
460 /* Size of UAR register table. */
462 /* Table of UAR registers for each process. */
465 /* MTR profile list. */
466 TAILQ_HEAD(mlx5_mtr_profiles, mlx5_flow_meter_profile);
468 TAILQ_HEAD(mlx5_flow_meters, mlx5_flow_meter);
470 #define MLX5_PROC_PRIV(port_id) \
471 ((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private)
474 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */
475 struct mlx5_ibv_shared *sh; /* Shared IB device context. */
476 uint32_t ibv_port; /* IB device port number. */
477 struct rte_pci_device *pci_dev; /* Backend PCI device. */
478 struct rte_ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */
479 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES);
480 /* Bit-field of MAC addresses owned by the PMD. */
481 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */
482 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */
483 /* Device properties. */
484 uint16_t mtu; /* Configured MTU. */
485 unsigned int isolated:1; /* Whether isolated mode is enabled. */
486 unsigned int representor:1; /* Device is a port representor. */
487 unsigned int master:1; /* Device is a E-Switch master. */
488 unsigned int dr_shared:1; /* DV/DR data is shared. */
489 unsigned int counter_fallback:1; /* Use counter fallback management. */
490 unsigned int mtr_en:1; /* Whether support meter. */
491 unsigned int mtr_reg_share:1; /* Whether support meter REG_C share. */
492 uint16_t domain_id; /* Switch domain identifier. */
493 uint16_t vport_id; /* Associated VF vport index (if any). */
494 uint32_t vport_meta_tag; /* Used for vport index match ove VF LAG. */
495 uint32_t vport_meta_mask; /* Used for vport index field match mask. */
496 int32_t representor_id; /* Port representor identifier. */
497 int32_t pf_bond; /* >=0 means PF index in bonding configuration. */
498 unsigned int if_index; /* Associated kernel network device index. */
500 unsigned int rxqs_n; /* RX queues array size. */
501 unsigned int txqs_n; /* TX queues array size. */
502 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */
503 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */
504 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
505 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */
506 unsigned int (*reta_idx)[]; /* RETA index table. */
507 unsigned int reta_idx_n; /* RETA index size. */
508 struct mlx5_drop drop_queue; /* Flow drop queues. */
509 struct mlx5_flows flows; /* RTE Flow rules. */
510 struct mlx5_flows ctrl_flows; /* Control flow rules. */
511 void *inter_flows; /* Intermediate resources for flow creation. */
512 int flow_idx; /* Intermediate device flow index. */
513 int flow_nested_idx; /* Intermediate device flow index, nested. */
514 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */
515 LIST_HEAD(rxqobj, mlx5_rxq_obj) rxqsobj; /* Verbs/DevX Rx queues. */
516 LIST_HEAD(hrxq, mlx5_hrxq) hrxqs; /* Verbs Hash Rx queues. */
517 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */
518 LIST_HEAD(txqobj, mlx5_txq_obj) txqsobj; /* Verbs/DevX Tx queues. */
519 /* Indirection tables. */
520 LIST_HEAD(ind_tables, mlx5_ind_table_obj) ind_tbls;
521 /* Pointer to next element. */
522 rte_atomic32_t refcnt; /**< Reference counter. */
523 struct ibv_flow_action *verbs_action;
524 /**< Verbs modify header action object. */
525 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
526 uint8_t max_lro_msg_size;
527 /* Tags resources cache. */
528 uint32_t link_speed_capa; /* Link speed capabilities. */
529 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */
530 struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */
531 struct mlx5_dev_config config; /* Device configuration. */
532 struct mlx5_verbs_alloc_ctx verbs_alloc_ctx;
533 /* Context for Verbs allocator. */
534 int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */
535 int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */
536 LIST_HEAD(dbrpage, mlx5_devx_dbr_page) dbrpgs; /* Door-bell pages. */
537 struct mlx5_nl_vlan_vmwa_context *vmwa_context; /* VLAN WA context. */
538 struct mlx5_flow_id_pool *qrss_id_pool;
539 struct mlx5_hlist *mreg_cp_tbl;
540 /* Hash table of Rx metadata register copy table. */
541 uint8_t mtr_sfx_reg; /* Meter prefix-suffix flow match REG_C. */
542 uint8_t mtr_color_reg; /* Meter color match REG_C. */
543 struct mlx5_mtr_profiles flow_meter_profiles; /* MTR profile list. */
544 struct mlx5_flow_meters flow_meters; /* MTR list. */
546 rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */
547 rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX];
548 /* UAR same-page access control required in 32bit implementations. */
550 uint8_t skip_default_rss_reta; /* Skip configuration of default reta. */
551 uint8_t fdb_def_rule; /* Whether fdb jump to table 1 is configured. */
552 struct mlx5_mp_id mp_id; /* ID of a multi-process process */
555 #define PORT_ID(priv) ((priv)->dev_data->port_id)
556 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)])
560 int mlx5_getenv_int(const char *);
561 int mlx5_proc_priv_init(struct rte_eth_dev *dev);
562 int64_t mlx5_get_dbr(struct rte_eth_dev *dev,
563 struct mlx5_devx_dbr_page **dbr_page);
564 int32_t mlx5_release_dbr(struct rte_eth_dev *dev, uint32_t umem_id,
566 int mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev,
567 struct rte_eth_udp_tunnel *udp_tunnel);
568 uint16_t mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev);
570 /* Macro to iterate over all valid ports for mlx5 driver. */
571 #define MLX5_ETH_FOREACH_DEV(port_id, pci_dev) \
572 for (port_id = mlx5_eth_find_next(0, pci_dev); \
573 port_id < RTE_MAX_ETHPORTS; \
574 port_id = mlx5_eth_find_next(port_id + 1, pci_dev))
578 int mlx5_get_ifname(const struct rte_eth_dev *dev, char (*ifname)[IF_NAMESIZE]);
579 int mlx5_get_master_ifname(const char *ibdev_path, char (*ifname)[IF_NAMESIZE]);
580 unsigned int mlx5_ifindex(const struct rte_eth_dev *dev);
581 int mlx5_ifreq(const struct rte_eth_dev *dev, int req, struct ifreq *ifr);
582 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu);
583 int mlx5_set_flags(struct rte_eth_dev *dev, unsigned int keep,
585 int mlx5_dev_configure(struct rte_eth_dev *dev);
586 int mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info);
587 int mlx5_read_clock(struct rte_eth_dev *dev, uint64_t *clock);
588 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size);
589 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev);
590 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete);
591 int mlx5_force_link_status_change(struct rte_eth_dev *dev, int status);
592 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
593 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev,
594 struct rte_eth_fc_conf *fc_conf);
595 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev,
596 struct rte_eth_fc_conf *fc_conf);
597 void mlx5_dev_link_status_handler(void *arg);
598 void mlx5_dev_interrupt_handler(void *arg);
599 void mlx5_dev_interrupt_handler_devx(void *arg);
600 void mlx5_dev_interrupt_handler_uninstall(struct rte_eth_dev *dev);
601 void mlx5_dev_interrupt_handler_install(struct rte_eth_dev *dev);
602 void mlx5_dev_interrupt_handler_devx_uninstall(struct rte_eth_dev *dev);
603 void mlx5_dev_interrupt_handler_devx_install(struct rte_eth_dev *dev);
604 int mlx5_set_link_down(struct rte_eth_dev *dev);
605 int mlx5_set_link_up(struct rte_eth_dev *dev);
606 int mlx5_is_removed(struct rte_eth_dev *dev);
607 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev);
608 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev);
609 struct mlx5_priv *mlx5_port_to_eswitch_info(uint16_t port, bool valid);
610 struct mlx5_priv *mlx5_dev_to_eswitch_info(struct rte_eth_dev *dev);
611 int mlx5_sysfs_switch_info(unsigned int ifindex,
612 struct mlx5_switch_info *info);
613 void mlx5_sysfs_check_switch_info(bool device_dir,
614 struct mlx5_switch_info *switch_info);
615 void mlx5_translate_port_name(const char *port_name_in,
616 struct mlx5_switch_info *port_info_out);
617 void mlx5_intr_callback_unregister(const struct rte_intr_handle *handle,
618 rte_intr_callback_fn cb_fn, void *cb_arg);
619 int mlx5_get_module_info(struct rte_eth_dev *dev,
620 struct rte_eth_dev_module_info *modinfo);
621 int mlx5_get_module_eeprom(struct rte_eth_dev *dev,
622 struct rte_dev_eeprom_info *info);
623 int mlx5_hairpin_cap_get(struct rte_eth_dev *dev,
624 struct rte_eth_hairpin_cap *cap);
625 int mlx5_dev_configure_rss_reta(struct rte_eth_dev *dev);
629 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]);
630 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
631 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
632 uint32_t index, uint32_t vmdq);
633 struct mlx5_nl_vlan_vmwa_context *mlx5_vlan_vmwa_init
634 (struct rte_eth_dev *dev, uint32_t ifindex);
635 int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr);
636 int mlx5_set_mc_addr_list(struct rte_eth_dev *dev,
637 struct rte_ether_addr *mc_addr_set,
638 uint32_t nb_mc_addr);
642 int mlx5_rss_hash_update(struct rte_eth_dev *dev,
643 struct rte_eth_rss_conf *rss_conf);
644 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev,
645 struct rte_eth_rss_conf *rss_conf);
646 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size);
647 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev,
648 struct rte_eth_rss_reta_entry64 *reta_conf,
650 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev,
651 struct rte_eth_rss_reta_entry64 *reta_conf,
656 int mlx5_promiscuous_enable(struct rte_eth_dev *dev);
657 int mlx5_promiscuous_disable(struct rte_eth_dev *dev);
658 int mlx5_allmulticast_enable(struct rte_eth_dev *dev);
659 int mlx5_allmulticast_disable(struct rte_eth_dev *dev);
663 void mlx5_stats_init(struct rte_eth_dev *dev);
664 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
665 int mlx5_stats_reset(struct rte_eth_dev *dev);
666 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats,
668 int mlx5_xstats_reset(struct rte_eth_dev *dev);
669 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
670 struct rte_eth_xstat_name *xstats_names,
675 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
676 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on);
677 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask);
678 void mlx5_vlan_vmwa_exit(struct mlx5_nl_vlan_vmwa_context *ctx);
679 void mlx5_vlan_vmwa_release(struct rte_eth_dev *dev,
680 struct mlx5_vf_vlan *vf_vlan);
681 void mlx5_vlan_vmwa_acquire(struct rte_eth_dev *dev,
682 struct mlx5_vf_vlan *vf_vlan);
686 int mlx5_dev_start(struct rte_eth_dev *dev);
687 void mlx5_dev_stop(struct rte_eth_dev *dev);
688 int mlx5_traffic_enable(struct rte_eth_dev *dev);
689 void mlx5_traffic_disable(struct rte_eth_dev *dev);
690 int mlx5_traffic_restart(struct rte_eth_dev *dev);
694 int mlx5_flow_discover_mreg_c(struct rte_eth_dev *eth_dev);
695 bool mlx5_flow_ext_mreg_supported(struct rte_eth_dev *dev);
696 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
697 void mlx5_flow_print(struct rte_flow *flow);
698 int mlx5_flow_validate(struct rte_eth_dev *dev,
699 const struct rte_flow_attr *attr,
700 const struct rte_flow_item items[],
701 const struct rte_flow_action actions[],
702 struct rte_flow_error *error);
703 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev,
704 const struct rte_flow_attr *attr,
705 const struct rte_flow_item items[],
706 const struct rte_flow_action actions[],
707 struct rte_flow_error *error);
708 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow,
709 struct rte_flow_error *error);
710 void mlx5_flow_list_flush(struct rte_eth_dev *dev, struct mlx5_flows *list,
712 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error);
713 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow,
714 const struct rte_flow_action *action, void *data,
715 struct rte_flow_error *error);
716 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable,
717 struct rte_flow_error *error);
718 int mlx5_dev_filter_ctrl(struct rte_eth_dev *dev,
719 enum rte_filter_type filter_type,
720 enum rte_filter_op filter_op,
722 int mlx5_flow_start(struct rte_eth_dev *dev, struct mlx5_flows *list);
723 void mlx5_flow_stop(struct rte_eth_dev *dev, struct mlx5_flows *list);
724 int mlx5_flow_start_default(struct rte_eth_dev *dev);
725 void mlx5_flow_stop_default(struct rte_eth_dev *dev);
726 void mlx5_flow_alloc_intermediate(struct rte_eth_dev *dev);
727 void mlx5_flow_free_intermediate(struct rte_eth_dev *dev);
728 int mlx5_flow_verify(struct rte_eth_dev *dev);
729 int mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, uint32_t queue);
730 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev,
731 struct rte_flow_item_eth *eth_spec,
732 struct rte_flow_item_eth *eth_mask,
733 struct rte_flow_item_vlan *vlan_spec,
734 struct rte_flow_item_vlan *vlan_mask);
735 int mlx5_ctrl_flow(struct rte_eth_dev *dev,
736 struct rte_flow_item_eth *eth_spec,
737 struct rte_flow_item_eth *eth_mask);
738 struct rte_flow *mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev);
739 int mlx5_flow_create_drop_queue(struct rte_eth_dev *dev);
740 void mlx5_flow_delete_drop_queue(struct rte_eth_dev *dev);
741 void mlx5_flow_async_pool_query_handle(struct mlx5_ibv_shared *sh,
742 uint64_t async_id, int status);
743 void mlx5_set_query_alarm(struct mlx5_ibv_shared *sh);
744 void mlx5_flow_query_alarm(void *arg);
745 uint32_t mlx5_counter_alloc(struct rte_eth_dev *dev);
746 void mlx5_counter_free(struct rte_eth_dev *dev, uint32_t cnt);
747 int mlx5_counter_query(struct rte_eth_dev *dev, uint32_t cnt,
748 bool clear, uint64_t *pkts, uint64_t *bytes);
749 int mlx5_flow_dev_dump(struct rte_eth_dev *dev, FILE *file,
750 struct rte_flow_error *error);
753 int mlx5_mp_primary_handle(const struct rte_mp_msg *mp_msg, const void *peer);
754 int mlx5_mp_secondary_handle(const struct rte_mp_msg *mp_msg, const void *peer);
755 void mlx5_mp_req_start_rxtx(struct rte_eth_dev *dev);
756 void mlx5_mp_req_stop_rxtx(struct rte_eth_dev *dev);
760 int mlx5_pmd_socket_init(void);
762 /* mlx5_flow_meter.c */
764 int mlx5_flow_meter_ops_get(struct rte_eth_dev *dev, void *arg);
765 struct mlx5_flow_meter *mlx5_flow_meter_find(struct mlx5_priv *priv,
767 struct mlx5_flow_meter *mlx5_flow_meter_attach
768 (struct mlx5_priv *priv,
770 const struct rte_flow_attr *attr,
771 struct rte_flow_error *error);
772 void mlx5_flow_meter_detach(struct mlx5_flow_meter *fm);
774 #endif /* RTE_PMD_MLX5_H_ */