1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_H_
7 #define RTE_PMD_MLX5_H_
14 #include <netinet/in.h>
15 #include <sys/queue.h>
18 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
20 #pragma GCC diagnostic ignored "-Wpedantic"
22 #include <infiniband/verbs.h>
24 #pragma GCC diagnostic error "-Wpedantic"
28 #include <rte_ether.h>
29 #include <rte_ethdev_driver.h>
30 #include <rte_rwlock.h>
31 #include <rte_interrupts.h>
32 #include <rte_errno.h>
35 #include "mlx5_utils.h"
37 #include "mlx5_autoconf.h"
38 #include "mlx5_defs.h"
41 PCI_VENDOR_ID_MELLANOX = 0x15b3,
45 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013,
46 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014,
47 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015,
48 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016,
49 PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017,
50 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018,
51 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019,
52 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a,
53 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF = 0xa2d2,
54 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF = 0xa2d3,
55 PCI_DEVICE_ID_MELLANOX_CONNECTX6 = 0x101b,
56 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF = 0x101c,
59 /* Request types for IPC. */
60 enum mlx5_mp_req_type {
61 MLX5_MP_REQ_VERBS_CMD_FD = 1,
62 MLX5_MP_REQ_CREATE_MR,
63 MLX5_MP_REQ_START_RXTX,
64 MLX5_MP_REQ_STOP_RXTX,
65 MLX5_MP_REQ_QUEUE_STATE_MODIFY,
68 struct mlx5_mp_arg_queue_state_modify {
69 uint8_t is_wq; /* Set if WQ. */
70 uint16_t queue_id; /* DPDK queue ID. */
71 enum ibv_wq_state state; /* WQ requested state. */
74 /* Pameters for IPC. */
75 struct mlx5_mp_param {
76 enum mlx5_mp_req_type type;
81 uintptr_t addr; /* MLX5_MP_REQ_CREATE_MR */
82 struct mlx5_mp_arg_queue_state_modify state_modify;
83 /* MLX5_MP_REQ_QUEUE_STATE_MODIFY */
87 /** Request timeout for IPC. */
88 #define MLX5_MP_REQ_TIMEOUT_SEC 5
90 /** Key string for IPC. */
91 #define MLX5_MP_NAME "net_mlx5_mp"
93 /* Recognized Infiniband device physical port name types. */
94 enum mlx5_phys_port_name_type {
95 MLX5_PHYS_PORT_NAME_TYPE_NOTSET = 0, /* Not set. */
96 MLX5_PHYS_PORT_NAME_TYPE_LEGACY, /* before kernel ver < 5.0 */
97 MLX5_PHYS_PORT_NAME_TYPE_UPLINK, /* p0, kernel ver >= 5.0 */
98 MLX5_PHYS_PORT_NAME_TYPE_PFVF, /* pf0vf0, kernel ver >= 5.0 */
99 MLX5_PHYS_PORT_NAME_TYPE_UNKNOWN, /* Unrecognized. */
102 /** Switch information returned by mlx5_nl_switch_info(). */
103 struct mlx5_switch_info {
104 uint32_t master:1; /**< Master device. */
105 uint32_t representor:1; /**< Representor device. */
106 enum mlx5_phys_port_name_type name_type; /** < Port name type. */
107 int32_t pf_num; /**< PF number (valid for pfxvfx format only). */
108 int32_t port_name; /**< Representor port name. */
109 uint64_t switch_id; /**< Switch identifier. */
112 LIST_HEAD(mlx5_dev_list, mlx5_ibv_shared);
114 /* Shared data between primary and secondary processes. */
115 struct mlx5_shared_data {
117 /* Global spinlock for primary and secondary processes. */
118 int init_done; /* Whether primary has done initialization. */
119 unsigned int secondary_cnt; /* Number of secondary processes init'd. */
120 struct mlx5_dev_list mem_event_cb_list;
121 rte_rwlock_t mem_event_rwlock;
124 /* Per-process data structure, not visible to other processes. */
125 struct mlx5_local_data {
126 int init_done; /* Whether a secondary has done initialization. */
129 extern struct mlx5_shared_data *mlx5_shared_data;
131 struct mlx5_counter_ctrl {
132 /* Name of the counter. */
133 char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE];
134 /* Name of the counter on the device table. */
135 char ctr_name[RTE_ETH_XSTATS_NAME_SIZE];
136 uint32_t ib:1; /**< Nonzero for IB counters. */
139 struct mlx5_xstats_ctrl {
140 /* Number of device stats. */
142 /* Number of device stats identified by PMD. */
143 uint16_t mlx5_stats_n;
144 /* Index in the device counters table. */
145 uint16_t dev_table_idx[MLX5_MAX_XSTATS];
146 uint64_t base[MLX5_MAX_XSTATS];
147 struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS];
150 struct mlx5_stats_ctrl {
151 /* Base for imissed counter. */
152 uint64_t imissed_base;
155 /* devX creation object */
156 struct mlx5_devx_obj {
157 struct mlx5dv_devx_obj *obj; /* The DV object. */
158 int id; /* The object ID. */
161 struct mlx5_devx_mkey_attr {
168 /* HCA supports this number of time periods for LRO. */
169 #define MLX5_LRO_NUM_SUPP_PERIODS 4
171 /* HCA attributes. */
172 struct mlx5_hca_attr {
173 uint32_t eswitch_manager:1;
174 uint32_t flow_counters_dump:1;
175 uint8_t flow_counter_bulk_alloc_bitmap;
176 uint32_t eth_net_offloads:1;
178 uint32_t wqe_vlan_insert:1;
179 uint32_t wqe_inline_mode:2;
180 uint32_t vport_inline_mode:3;
182 uint32_t tunnel_lro_gre:1;
183 uint32_t tunnel_lro_vxlan:1;
184 uint32_t lro_max_msg_sz_mode:2;
185 uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS];
189 TAILQ_HEAD(mlx5_flows, rte_flow);
191 /* Default PMD specific parameter value. */
192 #define MLX5_ARG_UNSET (-1)
194 #define MLX5_LRO_SUPPORTED(dev) \
195 (((struct mlx5_priv *)((dev)->data->dev_private))->config.lro.supported)
197 #define MLX5_LRO_ENABLED(dev) \
198 ((dev)->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO)
200 #define MLX5_FLOW_IPV4_LRO (1 << 0)
201 #define MLX5_FLOW_IPV6_LRO (1 << 1)
203 /* LRO configurations structure. */
204 struct mlx5_lro_config {
205 uint32_t supported:1; /* Whether LRO is supported. */
206 uint32_t timeout; /* User configuration. */
210 * Device configuration structure.
212 * Merged configuration from:
214 * - Device capabilities,
215 * - User device parameters disabled features.
217 struct mlx5_dev_config {
218 unsigned int hw_csum:1; /* Checksum offload is supported. */
219 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */
220 unsigned int hw_vlan_insert:1; /* VLAN insertion in WQE is supported. */
221 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */
222 unsigned int hw_padding:1; /* End alignment padding is supported. */
223 unsigned int vf:1; /* This is a VF. */
224 unsigned int tunnel_en:1;
225 /* Whether tunnel stateless offloads are supported. */
226 unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */
227 unsigned int cqe_comp:1; /* CQE compression is enabled. */
228 unsigned int cqe_pad:1; /* CQE padding is enabled. */
229 unsigned int tso:1; /* Whether TSO is supported. */
230 unsigned int rx_vec_en:1; /* Rx vector is enabled. */
231 unsigned int mr_ext_memseg_en:1;
232 /* Whether memseg should be extended for MR creation. */
233 unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */
234 unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */
235 unsigned int dv_esw_en:1; /* Enable E-Switch DV flow. */
236 unsigned int dv_flow_en:1; /* Enable DV flow. */
237 unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */
238 unsigned int devx:1; /* Whether devx interface is available or not. */
240 unsigned int enabled:1; /* Whether MPRQ is enabled. */
241 unsigned int stride_num_n; /* Number of strides. */
242 unsigned int min_stride_size_n; /* Min size of a stride. */
243 unsigned int max_stride_size_n; /* Max size of a stride. */
244 unsigned int max_memcpy_len;
245 /* Maximum packet size to memcpy Rx packets. */
246 unsigned int min_rxqs_num;
247 /* Rx queue count threshold to enable MPRQ. */
248 } mprq; /* Configurations for Multi-Packet RQ. */
249 int mps; /* Multi-packet send supported mode. */
250 unsigned int flow_prio; /* Number of flow priorities. */
251 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */
252 unsigned int ind_table_max_size; /* Maximum indirection table size. */
253 unsigned int max_dump_files_num; /* Maximum dump files per queue. */
254 int txqs_inline; /* Queue number threshold for inlining. */
255 int txq_inline_min; /* Minimal amount of data bytes to inline. */
256 int txq_inline_max; /* Max packet size for inlining with SEND. */
257 int txq_inline_mpw; /* Max packet size for inlining with eMPW. */
258 struct mlx5_hca_attr hca_attr; /* HCA attributes. */
259 struct mlx5_lro_config lro; /* LRO configuration. */
263 * Type of object being allocated.
265 enum mlx5_verbs_alloc_type {
266 MLX5_VERBS_ALLOC_TYPE_NONE,
267 MLX5_VERBS_ALLOC_TYPE_TX_QUEUE,
268 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE,
272 * Verbs allocator needs a context to know in the callback which kind of
273 * resources it is allocating.
275 struct mlx5_verbs_alloc_ctx {
276 enum mlx5_verbs_alloc_type type; /* Kind of object being allocated. */
277 const void *obj; /* Pointer to the DPDK object. */
280 LIST_HEAD(mlx5_mr_list, mlx5_mr);
282 /* Flow drop context necessary due to Verbs API. */
284 struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */
285 struct mlx5_rxq_ibv *rxq; /* Verbs Rx queue. */
288 #define MLX5_COUNTERS_PER_POOL 512
289 #define MLX5_MAX_PENDING_QUERIES 4
291 struct mlx5_flow_counter_pool;
293 struct flow_counter_stats {
298 /* Counters information. */
299 struct mlx5_flow_counter {
300 TAILQ_ENTRY(mlx5_flow_counter) next;
301 /**< Pointer to the next flow counter structure. */
302 uint32_t shared:1; /**< Share counter ID with other flow rules. */
304 /**< Whether the counter was allocated by batch command. */
305 uint32_t ref_cnt:30; /**< Reference counter. */
306 uint32_t id; /**< Counter ID. */
307 union { /**< Holds the counters for the rule. */
308 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42)
309 struct ibv_counter_set *cs;
310 #elif defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
311 struct ibv_counters *cs;
313 struct mlx5_devx_obj *dcs; /**< Counter Devx object. */
314 struct mlx5_flow_counter_pool *pool; /**< The counter pool. */
317 uint64_t hits; /**< Reset value of hits packets. */
318 int64_t query_gen; /**< Generation of the last release. */
320 uint64_t bytes; /**< Reset value of bytes. */
321 void *action; /**< Pointer to the dv action. */
324 TAILQ_HEAD(mlx5_counters, mlx5_flow_counter);
326 /* Counter pool structure - query is in pool resolution. */
327 struct mlx5_flow_counter_pool {
328 TAILQ_ENTRY(mlx5_flow_counter_pool) next;
329 struct mlx5_counters counters; /* Free counter list. */
331 struct mlx5_devx_obj *min_dcs;
332 rte_atomic64_t a64_dcs;
334 /* The devx object of the minimum counter ID. */
335 rte_atomic64_t query_gen;
336 uint32_t n_counters: 16; /* Number of devx allocated counters. */
337 rte_spinlock_t sl; /* The pool lock. */
338 struct mlx5_counter_stats_raw *raw;
339 struct mlx5_counter_stats_raw *raw_hw; /* The raw on HW working. */
340 struct mlx5_flow_counter counters_raw[]; /* The pool counters memory. */
343 struct mlx5_counter_stats_raw;
345 /* Memory management structure for group of counter statistics raws. */
346 struct mlx5_counter_stats_mem_mng {
347 LIST_ENTRY(mlx5_counter_stats_mem_mng) next;
348 struct mlx5_counter_stats_raw *raws;
349 struct mlx5_devx_obj *dm;
350 struct mlx5dv_devx_umem *umem;
353 /* Raw memory structure for the counter statistics values of a pool. */
354 struct mlx5_counter_stats_raw {
355 LIST_ENTRY(mlx5_counter_stats_raw) next;
357 struct mlx5_counter_stats_mem_mng *mem_mng;
358 volatile struct flow_counter_stats *data;
361 TAILQ_HEAD(mlx5_counter_pools, mlx5_flow_counter_pool);
363 /* Container structure for counter pools. */
364 struct mlx5_pools_container {
365 rte_atomic16_t n_valid; /* Number of valid pools. */
366 uint16_t n; /* Number of pools. */
367 struct mlx5_counter_pools pool_list; /* Counter pool list. */
368 struct mlx5_flow_counter_pool **pools; /* Counter pool array. */
369 struct mlx5_counter_stats_mem_mng *init_mem_mng;
370 /* Hold the memory management for the next allocated pools raws. */
373 /* Counter global management structure. */
374 struct mlx5_flow_counter_mng {
375 uint8_t mhi[2]; /* master \ host container index. */
376 struct mlx5_pools_container ccont[2 * 2];
377 /* 2 containers for single and for batch for double-buffer. */
378 struct mlx5_counters flow_counters; /* Legacy flow counter list. */
379 uint8_t pending_queries;
382 uint8_t query_thread_on;
383 LIST_HEAD(mem_mngs, mlx5_counter_stats_mem_mng) mem_mngs;
384 LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws;
387 /* Per port data of shared IB device. */
388 struct mlx5_ibv_shared_port {
391 * Interrupt handler port_id. Used by shared interrupt
392 * handler to find the corresponding rte_eth device
393 * by IB port index. If value is equal or greater
394 * RTE_MAX_ETHPORTS it means there is no subhandler
395 * installed for specified IB port index.
399 /* Table structure. */
400 struct mlx5_flow_tbl_resource {
401 void *obj; /**< Pointer to DR table object. */
402 rte_atomic32_t refcnt; /**< Reference counter. */
405 #define MLX5_MAX_TABLES 1024
406 #define MLX5_MAX_TABLES_FDB 32
407 #define MLX5_GROUP_FACTOR 1
410 * Shared Infiniband device context for Master/Representors
411 * which belong to same IB device with multiple IB ports.
413 struct mlx5_ibv_shared {
414 LIST_ENTRY(mlx5_ibv_shared) next;
416 uint32_t devx:1; /* Opened with DV. */
417 uint32_t max_port; /* Maximal IB device port index. */
418 struct ibv_context *ctx; /* Verbs/DV context. */
419 struct ibv_pd *pd; /* Protection Domain. */
420 char ibdev_name[IBV_SYSFS_NAME_MAX]; /* IB device name. */
421 char ibdev_path[IBV_SYSFS_PATH_MAX]; /* IB device path for secondary */
422 struct ibv_device_attr_ex device_attr; /* Device properties. */
423 struct rte_pci_device *pci_dev; /* Backend PCI device. */
424 LIST_ENTRY(mlx5_ibv_shared) mem_event_cb;
425 /**< Called by memory event callback. */
427 uint32_t dev_gen; /* Generation number to flush local caches. */
428 rte_rwlock_t rwlock; /* MR Lock. */
429 struct mlx5_mr_btree cache; /* Global MR cache table. */
430 struct mlx5_mr_list mr_list; /* Registered MR list. */
431 struct mlx5_mr_list mr_free_list; /* Freed MR list. */
433 /* Shared DV/DR flow data section. */
434 pthread_mutex_t dv_mutex; /* DV context mutex. */
435 uint32_t dv_refcnt; /* DV/DR data reference counter. */
436 void *fdb_domain; /* FDB Direct Rules name space handle. */
437 struct mlx5_flow_tbl_resource fdb_tbl[MLX5_MAX_TABLES_FDB];
438 /* FDB Direct Rules tables. */
439 void *rx_domain; /* RX Direct Rules name space handle. */
440 struct mlx5_flow_tbl_resource rx_tbl[MLX5_MAX_TABLES];
441 /* RX Direct Rules tables. */
442 void *tx_domain; /* TX Direct Rules name space handle. */
443 struct mlx5_flow_tbl_resource tx_tbl[MLX5_MAX_TABLES];
444 void *esw_drop_action; /* Pointer to DR E-Switch drop action. */
445 /* TX Direct Rules tables/ */
446 LIST_HEAD(matchers, mlx5_flow_dv_matcher) matchers;
447 LIST_HEAD(encap_decap, mlx5_flow_dv_encap_decap_resource) encaps_decaps;
448 LIST_HEAD(modify_cmd, mlx5_flow_dv_modify_hdr_resource) modify_cmds;
449 LIST_HEAD(tag, mlx5_flow_dv_tag_resource) tags;
450 LIST_HEAD(jump, mlx5_flow_dv_jump_tbl_resource) jump_tbl;
451 LIST_HEAD(port_id_action_list, mlx5_flow_dv_port_id_action_resource)
452 port_id_action_list; /* List of port ID actions. */
453 struct mlx5_flow_counter_mng cmng; /* Counters management structure. */
454 /* Shared interrupt handler section. */
455 pthread_mutex_t intr_mutex; /* Interrupt config mutex. */
456 uint32_t intr_cnt; /* Interrupt handler reference counter. */
457 struct rte_intr_handle intr_handle; /* Interrupt handler for device. */
458 struct rte_intr_handle intr_handle_devx; /* DEVX interrupt handler. */
459 struct mlx5dv_devx_cmd_comp *devx_comp; /* DEVX async comp obj. */
460 struct mlx5_ibv_shared_port port[]; /* per device port data array. */
463 /* Per-process private structure. */
464 struct mlx5_proc_priv {
466 /* Size of UAR register table. */
468 /* Table of UAR registers for each process. */
471 #define MLX5_PROC_PRIV(port_id) \
472 ((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private)
475 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */
476 struct mlx5_ibv_shared *sh; /* Shared IB device context. */
477 uint32_t ibv_port; /* IB device port number. */
478 struct rte_ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */
479 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES);
480 /* Bit-field of MAC addresses owned by the PMD. */
481 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */
482 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */
483 /* Device properties. */
484 uint16_t mtu; /* Configured MTU. */
485 unsigned int isolated:1; /* Whether isolated mode is enabled. */
486 unsigned int representor:1; /* Device is a port representor. */
487 unsigned int master:1; /* Device is a E-Switch master. */
488 unsigned int dr_shared:1; /* DV/DR data is shared. */
489 unsigned int counter_fallback:1; /* Use counter fallback management. */
490 uint16_t domain_id; /* Switch domain identifier. */
491 uint16_t vport_id; /* Associated VF vport index (if any). */
492 int32_t representor_id; /* Port representor identifier. */
493 unsigned int if_index; /* Associated kernel network device index. */
495 unsigned int rxqs_n; /* RX queues array size. */
496 unsigned int txqs_n; /* TX queues array size. */
497 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */
498 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */
499 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
500 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */
501 unsigned int (*reta_idx)[]; /* RETA index table. */
502 unsigned int reta_idx_n; /* RETA index size. */
503 struct mlx5_drop drop_queue; /* Flow drop queues. */
504 struct mlx5_flows flows; /* RTE Flow rules. */
505 struct mlx5_flows ctrl_flows; /* Control flow rules. */
506 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */
507 LIST_HEAD(rxqibv, mlx5_rxq_ibv) rxqsibv; /* Verbs Rx queues. */
508 LIST_HEAD(hrxq, mlx5_hrxq) hrxqs; /* Verbs Hash Rx queues. */
509 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */
510 LIST_HEAD(txqibv, mlx5_txq_ibv) txqsibv; /* Verbs Tx queues. */
511 /* Verbs Indirection tables. */
512 LIST_HEAD(ind_tables, mlx5_ind_table_ibv) ind_tbls;
513 /* Pointer to next element. */
514 rte_atomic32_t refcnt; /**< Reference counter. */
515 struct ibv_flow_action *verbs_action;
516 /**< Verbs modify header action object. */
517 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
518 /* Tags resources cache. */
519 uint32_t link_speed_capa; /* Link speed capabilities. */
520 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */
521 struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */
522 struct mlx5_dev_config config; /* Device configuration. */
523 struct mlx5_verbs_alloc_ctx verbs_alloc_ctx;
524 /* Context for Verbs allocator. */
525 int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */
526 int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */
527 uint32_t nl_sn; /* Netlink message sequence number. */
529 rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */
530 rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX];
531 /* UAR same-page access control required in 32bit implementations. */
535 #define PORT_ID(priv) ((priv)->dev_data->port_id)
536 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)])
540 int mlx5_getenv_int(const char *);
541 int mlx5_proc_priv_init(struct rte_eth_dev *dev);
545 int mlx5_get_ifname(const struct rte_eth_dev *dev, char (*ifname)[IF_NAMESIZE]);
546 int mlx5_get_master_ifname(const char *ibdev_path, char (*ifname)[IF_NAMESIZE]);
547 unsigned int mlx5_ifindex(const struct rte_eth_dev *dev);
548 int mlx5_ifreq(const struct rte_eth_dev *dev, int req, struct ifreq *ifr);
549 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu);
550 int mlx5_set_flags(struct rte_eth_dev *dev, unsigned int keep,
552 int mlx5_dev_configure(struct rte_eth_dev *dev);
553 void mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info);
554 int mlx5_read_clock(struct rte_eth_dev *dev, uint64_t *clock);
555 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size);
556 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev);
557 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete);
558 int mlx5_force_link_status_change(struct rte_eth_dev *dev, int status);
559 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
560 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev,
561 struct rte_eth_fc_conf *fc_conf);
562 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev,
563 struct rte_eth_fc_conf *fc_conf);
564 int mlx5_ibv_device_to_pci_addr(const struct ibv_device *device,
565 struct rte_pci_addr *pci_addr);
566 void mlx5_dev_link_status_handler(void *arg);
567 void mlx5_dev_interrupt_handler(void *arg);
568 void mlx5_dev_interrupt_handler_devx(void *arg);
569 void mlx5_dev_interrupt_handler_uninstall(struct rte_eth_dev *dev);
570 void mlx5_dev_interrupt_handler_install(struct rte_eth_dev *dev);
571 int mlx5_set_link_down(struct rte_eth_dev *dev);
572 int mlx5_set_link_up(struct rte_eth_dev *dev);
573 int mlx5_is_removed(struct rte_eth_dev *dev);
574 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev);
575 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev);
576 unsigned int mlx5_dev_to_port_id(const struct rte_device *dev,
578 unsigned int port_list_n);
579 int mlx5_port_to_eswitch_info(uint16_t port, uint16_t *es_domain_id,
580 uint16_t *es_port_id);
581 int mlx5_sysfs_switch_info(unsigned int ifindex,
582 struct mlx5_switch_info *info);
583 void mlx5_sysfs_check_switch_info(bool device_dir,
584 struct mlx5_switch_info *switch_info);
585 void mlx5_nl_check_switch_info(bool nun_vf_set,
586 struct mlx5_switch_info *switch_info);
587 void mlx5_translate_port_name(const char *port_name_in,
588 struct mlx5_switch_info *port_info_out);
589 void mlx5_intr_callback_unregister(const struct rte_intr_handle *handle,
590 rte_intr_callback_fn cb_fn, void *cb_arg);
594 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]);
595 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
596 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
597 uint32_t index, uint32_t vmdq);
598 int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr);
599 int mlx5_set_mc_addr_list(struct rte_eth_dev *dev,
600 struct rte_ether_addr *mc_addr_set,
601 uint32_t nb_mc_addr);
605 int mlx5_rss_hash_update(struct rte_eth_dev *dev,
606 struct rte_eth_rss_conf *rss_conf);
607 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev,
608 struct rte_eth_rss_conf *rss_conf);
609 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size);
610 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev,
611 struct rte_eth_rss_reta_entry64 *reta_conf,
613 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev,
614 struct rte_eth_rss_reta_entry64 *reta_conf,
619 void mlx5_promiscuous_enable(struct rte_eth_dev *dev);
620 void mlx5_promiscuous_disable(struct rte_eth_dev *dev);
621 void mlx5_allmulticast_enable(struct rte_eth_dev *dev);
622 void mlx5_allmulticast_disable(struct rte_eth_dev *dev);
626 void mlx5_stats_init(struct rte_eth_dev *dev);
627 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
628 void mlx5_stats_reset(struct rte_eth_dev *dev);
629 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats,
631 void mlx5_xstats_reset(struct rte_eth_dev *dev);
632 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
633 struct rte_eth_xstat_name *xstats_names,
638 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
639 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on);
640 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask);
644 int mlx5_dev_start(struct rte_eth_dev *dev);
645 void mlx5_dev_stop(struct rte_eth_dev *dev);
646 int mlx5_traffic_enable(struct rte_eth_dev *dev);
647 void mlx5_traffic_disable(struct rte_eth_dev *dev);
648 int mlx5_traffic_restart(struct rte_eth_dev *dev);
652 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
653 void mlx5_flow_print(struct rte_flow *flow);
654 int mlx5_flow_validate(struct rte_eth_dev *dev,
655 const struct rte_flow_attr *attr,
656 const struct rte_flow_item items[],
657 const struct rte_flow_action actions[],
658 struct rte_flow_error *error);
659 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev,
660 const struct rte_flow_attr *attr,
661 const struct rte_flow_item items[],
662 const struct rte_flow_action actions[],
663 struct rte_flow_error *error);
664 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow,
665 struct rte_flow_error *error);
666 void mlx5_flow_list_flush(struct rte_eth_dev *dev, struct mlx5_flows *list);
667 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error);
668 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow,
669 const struct rte_flow_action *action, void *data,
670 struct rte_flow_error *error);
671 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable,
672 struct rte_flow_error *error);
673 int mlx5_dev_filter_ctrl(struct rte_eth_dev *dev,
674 enum rte_filter_type filter_type,
675 enum rte_filter_op filter_op,
677 int mlx5_flow_start(struct rte_eth_dev *dev, struct mlx5_flows *list);
678 void mlx5_flow_stop(struct rte_eth_dev *dev, struct mlx5_flows *list);
679 int mlx5_flow_verify(struct rte_eth_dev *dev);
680 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev,
681 struct rte_flow_item_eth *eth_spec,
682 struct rte_flow_item_eth *eth_mask,
683 struct rte_flow_item_vlan *vlan_spec,
684 struct rte_flow_item_vlan *vlan_mask);
685 int mlx5_ctrl_flow(struct rte_eth_dev *dev,
686 struct rte_flow_item_eth *eth_spec,
687 struct rte_flow_item_eth *eth_mask);
688 int mlx5_flow_create_drop_queue(struct rte_eth_dev *dev);
689 void mlx5_flow_delete_drop_queue(struct rte_eth_dev *dev);
690 void mlx5_flow_async_pool_query_handle(struct mlx5_ibv_shared *sh,
691 uint64_t async_id, int status);
692 void mlx5_set_query_alarm(struct mlx5_ibv_shared *sh);
693 void mlx5_flow_query_alarm(void *arg);
696 void mlx5_mp_req_start_rxtx(struct rte_eth_dev *dev);
697 void mlx5_mp_req_stop_rxtx(struct rte_eth_dev *dev);
698 int mlx5_mp_req_mr_create(struct rte_eth_dev *dev, uintptr_t addr);
699 int mlx5_mp_req_verbs_cmd_fd(struct rte_eth_dev *dev);
700 int mlx5_mp_req_queue_state_modify(struct rte_eth_dev *dev,
701 struct mlx5_mp_arg_queue_state_modify *sm);
702 int mlx5_mp_init_primary(void);
703 void mlx5_mp_uninit_primary(void);
704 int mlx5_mp_init_secondary(void);
705 void mlx5_mp_uninit_secondary(void);
709 int mlx5_nl_init(int protocol);
710 int mlx5_nl_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
712 int mlx5_nl_mac_addr_remove(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
714 void mlx5_nl_mac_addr_sync(struct rte_eth_dev *dev);
715 void mlx5_nl_mac_addr_flush(struct rte_eth_dev *dev);
716 int mlx5_nl_promisc(struct rte_eth_dev *dev, int enable);
717 int mlx5_nl_allmulti(struct rte_eth_dev *dev, int enable);
718 unsigned int mlx5_nl_portnum(int nl, const char *name);
719 unsigned int mlx5_nl_ifindex(int nl, const char *name, uint32_t pindex);
720 int mlx5_nl_switch_info(int nl, unsigned int ifindex,
721 struct mlx5_switch_info *info);
723 /* mlx5_devx_cmds.c */
725 struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(struct ibv_context *ctx,
727 int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj);
728 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
729 int clear, uint32_t n_counters,
730 uint64_t *pkts, uint64_t *bytes,
731 uint32_t mkey, void *addr,
732 struct mlx5dv_devx_cmd_comp *cmd_comp,
734 int mlx5_devx_cmd_query_hca_attr(struct ibv_context *ctx,
735 struct mlx5_hca_attr *attr);
736 struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(struct ibv_context *ctx,
737 struct mlx5_devx_mkey_attr *attr);
738 int mlx5_devx_get_out_command_status(void *out);
739 #endif /* RTE_PMD_MLX5_H_ */