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5 * Copyright 2015 Mellanox.
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34 #ifndef RTE_PMD_MLX5_DEFS_H_
35 #define RTE_PMD_MLX5_DEFS_H_
37 #include "mlx5_autoconf.h"
39 /* Reported driver name. */
40 #define MLX5_DRIVER_NAME "librte_pmd_mlx5"
42 /* Maximum number of simultaneous MAC addresses. */
43 #define MLX5_MAX_MAC_ADDRESSES 128
45 /* Maximum number of simultaneous VLAN filters. */
46 #define MLX5_MAX_VLAN_IDS 128
48 /* Maximum number of special flows. */
49 #define MLX5_MAX_SPECIAL_FLOWS 4
51 /* Request send completion once in every 64 sends, might be less. */
52 #define MLX5_PMD_TX_PER_COMP_REQ 64
54 /* RSS Indirection table size. */
55 #define RSS_INDIRECTION_TABLE_SIZE 256
57 /* Maximum number of Scatter/Gather Elements per Work Request. */
58 #ifndef MLX5_PMD_SGE_WR_N
59 #define MLX5_PMD_SGE_WR_N 4
62 /* Maximum size for inline data. */
63 #ifndef MLX5_PMD_MAX_INLINE
64 #define MLX5_PMD_MAX_INLINE 0
68 * Maximum number of cached Memory Pools (MPs) per TX queue. Each RTE MP
69 * from which buffers are to be transmitted will have to be mapped by this
70 * driver to their own Memory Region (MR). This is a slow operation.
72 * This value is always 1 for RX queues.
74 #ifndef MLX5_PMD_TX_MP_CACHE
75 #define MLX5_PMD_TX_MP_CACHE 8
79 * If defined, only use software counters. The PMD will never ask the hardware
80 * for these, and many of them won't be available.
82 #ifndef MLX5_PMD_SOFT_COUNTERS
83 #define MLX5_PMD_SOFT_COUNTERS 1
87 #define MLX5_ALARM_TIMEOUT_US 100000
90 * Extended flow priorities necessary to support flow director are available
91 * since MLNX_OFED 3.2. Considering this version adds support for VLAN
92 * offloads as well, their availability means flow director can be used.
94 #ifdef HAVE_EXP_DEVICE_ATTR_VLAN_OFFLOADS
95 #define MLX5_FDIR_SUPPORT 1
98 #endif /* RTE_PMD_MLX5_DEFS_H_ */