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5 * Copyright 2015 Mellanox.
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34 #ifndef RTE_PMD_MLX5_DEFS_H_
35 #define RTE_PMD_MLX5_DEFS_H_
37 /* Reported driver name. */
38 #define MLX5_DRIVER_NAME "librte_pmd_mlx5"
40 /* Maximum number of simultaneous MAC addresses. */
41 #define MLX5_MAX_MAC_ADDRESSES 128
43 /* Maximum number of simultaneous VLAN filters. */
44 #define MLX5_MAX_VLAN_IDS 128
46 /* Maximum number of special flows. */
47 #define MLX5_MAX_SPECIAL_FLOWS 2
49 /* Request send completion once in every 64 sends, might be less. */
50 #define MLX5_PMD_TX_PER_COMP_REQ 64
52 /* RSS Indirection table size. */
53 #define RSS_INDIRECTION_TABLE_SIZE 512
55 /* Maximum number of Scatter/Gather Elements per Work Request. */
56 #ifndef MLX5_PMD_SGE_WR_N
57 #define MLX5_PMD_SGE_WR_N 4
60 /* Maximum size for inline data. */
61 #ifndef MLX5_PMD_MAX_INLINE
62 #define MLX5_PMD_MAX_INLINE 0
66 * Maximum number of cached Memory Pools (MPs) per TX queue. Each RTE MP
67 * from which buffers are to be transmitted will have to be mapped by this
68 * driver to their own Memory Region (MR). This is a slow operation.
70 * This value is always 1 for RX queues.
72 #ifndef MLX5_PMD_TX_MP_CACHE
73 #define MLX5_PMD_TX_MP_CACHE 8
77 * If defined, only use software counters. The PMD will never ask the hardware
78 * for these, and many of them won't be available.
80 #ifndef MLX5_PMD_SOFT_COUNTERS
81 #define MLX5_PMD_SOFT_COUNTERS 1
85 #define MLX5_ALARM_TIMEOUT_US 100000
87 #endif /* RTE_PMD_MLX5_DEFS_H_ */