1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_DEFS_H_
7 #define RTE_PMD_MLX5_DEFS_H_
9 #include <rte_ethdev_driver.h>
11 #include "mlx5_autoconf.h"
13 /* Reported driver name. */
14 #define MLX5_DRIVER_NAME "net_mlx5"
16 /* Maximum number of simultaneous unicast MAC addresses. */
17 #define MLX5_MAX_UC_MAC_ADDRESSES 128
18 /* Maximum number of simultaneous Multicast MAC addresses. */
19 #define MLX5_MAX_MC_MAC_ADDRESSES 128
20 /* Maximum number of simultaneous MAC addresses. */
21 #define MLX5_MAX_MAC_ADDRESSES \
22 (MLX5_MAX_UC_MAC_ADDRESSES + MLX5_MAX_MC_MAC_ADDRESSES)
24 /* Maximum number of simultaneous VLAN filters. */
25 #define MLX5_MAX_VLAN_IDS 128
28 * Request TX completion every time descriptors reach this threshold since
29 * the previous request. Must be a power of two for performance reasons.
31 #define MLX5_TX_COMP_THRESH 32
34 * Request TX completion every time the total number of WQEBBs used for inlining
35 * packets exceeds the size of WQ divided by this divisor. Better to be power of
36 * two for performance.
38 #define MLX5_TX_COMP_THRESH_INLINE_DIV (1 << 3)
41 * Maximum number of cached Memory Pools (MPs) per TX queue. Each RTE MP
42 * from which buffers are to be transmitted will have to be mapped by this
43 * driver to their own Memory Region (MR). This is a slow operation.
45 * This value is always 1 for RX queues.
47 #ifndef MLX5_PMD_TX_MP_CACHE
48 #define MLX5_PMD_TX_MP_CACHE 8
52 * If defined, only use software counters. The PMD will never ask the hardware
53 * for these, and many of them won't be available.
55 #ifndef MLX5_PMD_SOFT_COUNTERS
56 #define MLX5_PMD_SOFT_COUNTERS 1
60 #define MLX5_ALARM_TIMEOUT_US 100000
62 /* Maximum number of extended statistics counters. */
63 #define MLX5_MAX_XSTATS 32
65 /* Maximum Packet headers size (L2+L3+L4) for TSO. */
66 #define MLX5_MAX_TSO_HEADER 192
68 /* Default minimum number of Tx queues for vectorized Tx. */
69 #define MLX5_VPMD_MIN_TXQS 4
71 /* Threshold of buffer replenishment for vectorized Rx. */
72 #define MLX5_VPMD_RXQ_RPLNSH_THRESH 64U
74 /* Maximum size of burst for vectorized Rx. */
75 #define MLX5_VPMD_RX_MAX_BURST MLX5_VPMD_RXQ_RPLNSH_THRESH
78 * Maximum size of burst for vectorized Tx. This is related to the maximum size
79 * of Enhanced MPW (eMPW) WQE as vectorized Tx is supported with eMPW.
80 * Careful when changing, large value can cause WQE DS to overlap.
82 #define MLX5_VPMD_TX_MAX_BURST 32U
84 /* Number of packets vectorized Rx can simultaneously process in a loop. */
85 #define MLX5_VPMD_DESCS_PER_LOOP 4
88 #define MLX5_RSS_HF_MASK (~(ETH_RSS_IP | ETH_RSS_UDP | ETH_RSS_TCP))
90 /* Timeout in seconds to get a valid link status. */
91 #define MLX5_LINK_STATUS_TIMEOUT 10
93 /* Reserved address space for UAR mapping. */
94 #define MLX5_UAR_SIZE (1ULL << 32)
96 /* Offset of reserved UAR address space to hugepage memory. Offset is used here
97 * to minimize possibility of address next to hugepage being used by other code
98 * in either primary or secondary process, failing to map TX UAR would make TX
99 * packets invisible to HW.
101 #define MLX5_UAR_OFFSET (1ULL << 32)
103 #endif /* RTE_PMD_MLX5_DEFS_H_ */