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5 * Copyright 2015 Mellanox.
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34 #ifndef RTE_PMD_MLX5_DEFS_H_
35 #define RTE_PMD_MLX5_DEFS_H_
37 #include "mlx5_autoconf.h"
39 /* Reported driver name. */
40 #define MLX5_DRIVER_NAME "net_mlx5"
42 /* Maximum number of simultaneous MAC addresses. */
43 #define MLX5_MAX_MAC_ADDRESSES 128
45 /* Maximum number of simultaneous VLAN filters. */
46 #define MLX5_MAX_VLAN_IDS 128
48 /* Maximum number of special flows. */
49 #define MLX5_MAX_SPECIAL_FLOWS 4
52 * Request TX completion every time descriptors reach this threshold since
53 * the previous request. Must be a power of two for performance reasons.
55 #define MLX5_TX_COMP_THRESH 32
57 /* RSS Indirection table size. */
58 #define RSS_INDIRECTION_TABLE_SIZE 256
61 * Maximum number of cached Memory Pools (MPs) per TX queue. Each RTE MP
62 * from which buffers are to be transmitted will have to be mapped by this
63 * driver to their own Memory Region (MR). This is a slow operation.
65 * This value is always 1 for RX queues.
67 #ifndef MLX5_PMD_TX_MP_CACHE
68 #define MLX5_PMD_TX_MP_CACHE 8
72 * If defined, only use software counters. The PMD will never ask the hardware
73 * for these, and many of them won't be available.
75 #ifndef MLX5_PMD_SOFT_COUNTERS
76 #define MLX5_PMD_SOFT_COUNTERS 1
80 #define MLX5_ALARM_TIMEOUT_US 100000
82 #endif /* RTE_PMD_MLX5_DEFS_H_ */