1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_DEFS_H_
7 #define RTE_PMD_MLX5_DEFS_H_
9 #include <ethdev_driver.h>
10 #include <rte_vxlan.h>
12 #include <mlx5_common_defs.h>
14 #include "mlx5_autoconf.h"
16 /* Maximum number of simultaneous VLAN filters. */
17 #define MLX5_MAX_VLAN_IDS 128
20 * Request TX completion every time descriptors reach this threshold since
21 * the previous request. Must be a power of two for performance reasons.
23 #define MLX5_TX_COMP_THRESH 32u
26 * Request TX completion every time the total number of WQEBBs used for inlining
27 * packets exceeds the size of WQ divided by this divisor. Better to be power of
28 * two for performance.
30 #define MLX5_TX_COMP_THRESH_INLINE_DIV (1 << 3)
33 * Maximal amount of normal completion CQEs
34 * processed in one call of tx_burst() routine.
36 #define MLX5_TX_COMP_MAX_CQE 2u
39 * If defined, only use software counters. The PMD will never ask the hardware
40 * for these, and many of them won't be available.
42 #ifndef MLX5_PMD_SOFT_COUNTERS
43 #define MLX5_PMD_SOFT_COUNTERS 1
47 #define MLX5_ALARM_TIMEOUT_US 100000
49 /* Maximum number of extended statistics counters. */
50 #define MLX5_MAX_XSTATS 32
52 /* Maximum Packet headers size (L2+L3+L4) for TSO. */
53 #define MLX5_MAX_TSO_HEADER (128u + 34u)
55 /* Inline data size required by NICs. */
56 #define MLX5_INLINE_HSIZE_NONE 0
57 #define MLX5_INLINE_HSIZE_L2 (sizeof(struct rte_ether_hdr) + \
58 sizeof(struct rte_vlan_hdr))
59 #define MLX5_INLINE_HSIZE_L3 (MLX5_INLINE_HSIZE_L2 + \
60 sizeof(struct rte_ipv6_hdr))
61 #define MLX5_INLINE_HSIZE_L4 (MLX5_INLINE_HSIZE_L3 + \
62 sizeof(struct rte_tcp_hdr))
63 #define MLX5_INLINE_HSIZE_INNER_L2 (MLX5_INLINE_HSIZE_L3 + \
64 sizeof(struct rte_udp_hdr) + \
65 sizeof(struct rte_vxlan_hdr) + \
66 sizeof(struct rte_ether_hdr) + \
67 sizeof(struct rte_vlan_hdr))
68 #define MLX5_INLINE_HSIZE_INNER_L3 (MLX5_INLINE_HSIZE_INNER_L2 + \
69 sizeof(struct rte_ipv6_hdr))
70 #define MLX5_INLINE_HSIZE_INNER_L4 (MLX5_INLINE_HSIZE_INNER_L3 + \
71 sizeof(struct rte_tcp_hdr))
73 /* Threshold of buffer replenishment for vectorized Rx. */
74 #define MLX5_VPMD_RXQ_RPLNSH_THRESH(n) \
75 (RTE_MIN(MLX5_VPMD_RX_MAX_BURST, (unsigned int)(n) >> 2))
77 /* Maximum size of burst for vectorized Rx. */
78 #define MLX5_VPMD_RX_MAX_BURST 64U
80 /* Recommended optimal burst size. */
81 #define MLX5_RX_DEFAULT_BURST 64U
82 #define MLX5_TX_DEFAULT_BURST 64U
84 /* Number of packets vectorized Rx can simultaneously process in a loop. */
85 #define MLX5_VPMD_DESCS_PER_LOOP 4
87 /* Mask of RSS on source only or destination only. */
88 #define MLX5_RSS_SRC_DST_ONLY (RTE_ETH_RSS_L3_SRC_ONLY | RTE_ETH_RSS_L3_DST_ONLY | \
89 RTE_ETH_RSS_L4_SRC_ONLY | RTE_ETH_RSS_L4_DST_ONLY)
92 #define MLX5_RSS_HF_MASK (~(RTE_ETH_RSS_IP | RTE_ETH_RSS_UDP | RTE_ETH_RSS_TCP | \
93 MLX5_RSS_SRC_DST_ONLY))
95 /* Timeout in seconds to get a valid link status. */
96 #define MLX5_LINK_STATUS_TIMEOUT 10
98 /* Number of times to retry retrieving the physical link information. */
99 #define MLX5_GET_LINK_STATUS_RETRY_COUNT 3
101 /* Maximum number of UAR pages used by a port,
102 * These are the size and mask for an array of mutexes used to synchronize
103 * the access to port's UARs on platforms that do not support 64 bit writes.
104 * In such systems it is possible to issue the 64 bits DoorBells through two
105 * consecutive writes, each write 32 bits. The access to a UAR page (which can
106 * be accessible by all threads in the process) must be synchronized
107 * (for example, using a semaphore). Such a synchronization is not required
108 * when ringing DoorBells on different UAR pages.
109 * A port with 512 Tx queues uses 8, 4kBytes, UAR pages which are shared
112 #define MLX5_UAR_PAGE_NUM_MAX 64
113 #define MLX5_UAR_PAGE_NUM_MASK ((MLX5_UAR_PAGE_NUM_MAX) - 1)
115 /* Fields of memory mapping type in offset parameter of mmap() */
116 #define MLX5_UAR_MMAP_CMD_SHIFT 8
117 #define MLX5_UAR_MMAP_CMD_MASK 0xff
119 #ifndef HAVE_MLX5DV_MMAP_GET_NC_PAGES_CMD
120 #define MLX5_MMAP_GET_NC_PAGES_CMD 3
123 /* Log 2 of the default number of strides per WQE for Multi-Packet RQ. */
124 #define MLX5_MPRQ_STRIDE_NUM_N 6U
126 /* Log 2 of the default size of a stride per WQE for Multi-Packet RQ. */
127 #define MLX5_MPRQ_STRIDE_SIZE_N 11U
129 /* Two-byte shift is disabled for Multi-Packet RQ. */
130 #define MLX5_MPRQ_TWO_BYTE_SHIFT 0
133 * Minimum size of packet to be memcpy'd instead of being attached as an
136 #define MLX5_MPRQ_MEMCPY_DEFAULT_LEN 128
138 /* Minimum number Rx queues to enable Multi-Packet RQ. */
139 #define MLX5_MPRQ_MIN_RXQS 12
141 /* Cache size of mempool for Multi-Packet RQ. */
142 #define MLX5_MPRQ_MP_CACHE_SZ 32U
144 /* MLX5_DV_XMETA_EN supported values. */
145 #define MLX5_XMETA_MODE_LEGACY 0
146 #define MLX5_XMETA_MODE_META16 1
147 #define MLX5_XMETA_MODE_META32 2
148 /* Provide info on patrial hw miss. Implies MLX5_XMETA_MODE_META16 */
149 #define MLX5_XMETA_MODE_MISS_INFO 3
151 /* Tx accurate scheduling on timestamps parameters. */
152 #define MLX5_TXPP_WAIT_INIT_TS 1000ul /* How long to wait timestamp. */
153 #define MLX5_TXPP_CLKQ_SIZE 1
154 #define MLX5_TXPP_REARM ((1UL << MLX5_WQ_INDEX_WIDTH) / 4)
155 #define MLX5_TXPP_REARM_SQ_SIZE (((1UL << MLX5_CQ_INDEX_WIDTH) / \
156 MLX5_TXPP_REARM) * 2)
157 #define MLX5_TXPP_REARM_CQ_SIZE (MLX5_TXPP_REARM_SQ_SIZE / 2)
158 /* The minimal size test packet to put into one WQE, padded by HW. */
159 #define MLX5_TXPP_TEST_PKT_SIZE (sizeof(struct rte_ether_hdr) + \
160 sizeof(struct rte_ipv4_hdr))
162 /* Size of the simple hash table for metadata register table. */
163 #define MLX5_FLOW_MREG_HTABLE_SZ 64
164 #define MLX5_FLOW_MREG_HNAME "MARK_COPY_TABLE"
165 #define MLX5_DEFAULT_COPY_ID UINT32_MAX
167 /* Size of the simple hash table for header modify table. */
168 #define MLX5_FLOW_HDR_MODIFY_HTABLE_SZ (1 << 15)
170 /* Size of the simple hash table for encap decap table. */
171 #define MLX5_FLOW_ENCAP_DECAP_HTABLE_SZ (1 << 12)
173 /* Size of the hash table for tag table. */
174 #define MLX5_TAGS_HLIST_ARRAY_SIZE (1 << 15)
176 /* Size fo the hash table for SFT table. */
177 #define MLX5_FLOW_SFT_HLIST_ARRAY_SIZE 4096
179 /* Hairpin TX/RX queue configuration parameters. */
180 #define MLX5_HAIRPIN_QUEUE_STRIDE 6
181 #define MLX5_HAIRPIN_JUMBO_LOG_SIZE (14 + 2)
183 /* Maximum number of indirect actions supported by rte_flow */
184 #define MLX5_MAX_INDIRECT_ACTIONS 3
187 * Linux definition of static_assert is found in /usr/include/assert.h.
188 * Windows does not require a redefinition.
190 #if !defined(HAVE_STATIC_ASSERT) && !defined(RTE_EXEC_ENV_WINDOWS)
191 #define static_assert _Static_assert
194 #endif /* RTE_PMD_MLX5_DEFS_H_ */