1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2020 Mellanox Technologies, Ltd
10 #include <sys/queue.h>
12 #include <rte_malloc.h>
13 #include <rte_common.h>
14 #include <rte_eal_paging.h>
16 #include <mlx5_glue.h>
17 #include <mlx5_devx_cmds.h>
18 #include <mlx5_common_devx.h>
19 #include <mlx5_malloc.h>
22 #include "mlx5_common_os.h"
25 #include "mlx5_utils.h"
26 #include "mlx5_devx.h"
27 #include "mlx5_flow.h"
28 #include "mlx5_flow_os.h"
31 * Modify RQ vlan stripping offload
36 * Enable/disable VLAN stripping.
39 * 0 on success, non-0 otherwise
42 mlx5_rxq_obj_modify_rq_vlan_strip(struct mlx5_rxq_priv *rxq, int on)
44 struct mlx5_devx_modify_rq_attr rq_attr;
46 memset(&rq_attr, 0, sizeof(rq_attr));
47 rq_attr.rq_state = MLX5_RQC_STATE_RDY;
48 rq_attr.state = MLX5_RQC_STATE_RDY;
49 rq_attr.vsd = (on ? 0 : 1);
50 rq_attr.modify_bitmask = MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD;
51 return mlx5_devx_cmd_modify_rq(rxq->devx_rq.rq, &rq_attr);
55 * Modify RQ using DevX API.
60 * Type of change queue state.
63 * 0 on success, a negative errno value otherwise and rte_errno is set.
66 mlx5_devx_modify_rq(struct mlx5_rxq_priv *rxq, uint8_t type)
68 struct mlx5_devx_modify_rq_attr rq_attr;
70 memset(&rq_attr, 0, sizeof(rq_attr));
72 case MLX5_RXQ_MOD_ERR2RST:
73 rq_attr.rq_state = MLX5_RQC_STATE_ERR;
74 rq_attr.state = MLX5_RQC_STATE_RST;
76 case MLX5_RXQ_MOD_RST2RDY:
77 rq_attr.rq_state = MLX5_RQC_STATE_RST;
78 rq_attr.state = MLX5_RQC_STATE_RDY;
80 case MLX5_RXQ_MOD_RDY2ERR:
81 rq_attr.rq_state = MLX5_RQC_STATE_RDY;
82 rq_attr.state = MLX5_RQC_STATE_ERR;
84 case MLX5_RXQ_MOD_RDY2RST:
85 rq_attr.rq_state = MLX5_RQC_STATE_RDY;
86 rq_attr.state = MLX5_RQC_STATE_RST;
91 if (rxq->ctrl->type == MLX5_RXQ_TYPE_HAIRPIN)
92 return mlx5_devx_cmd_modify_rq(rxq->ctrl->obj->rq, &rq_attr);
93 return mlx5_devx_cmd_modify_rq(rxq->devx_rq.rq, &rq_attr);
97 * Modify SQ using DevX API.
100 * DevX Tx queue object.
102 * Type of change queue state.
107 * 0 on success, a negative errno value otherwise and rte_errno is set.
110 mlx5_txq_devx_modify(struct mlx5_txq_obj *obj, enum mlx5_txq_modify_type type,
113 struct mlx5_devx_modify_sq_attr msq_attr = { 0 };
116 if (type != MLX5_TXQ_MOD_RST2RDY) {
117 /* Change queue state to reset. */
118 if (type == MLX5_TXQ_MOD_ERR2RDY)
119 msq_attr.sq_state = MLX5_SQC_STATE_ERR;
121 msq_attr.sq_state = MLX5_SQC_STATE_RDY;
122 msq_attr.state = MLX5_SQC_STATE_RST;
123 ret = mlx5_devx_cmd_modify_sq(obj->sq_obj.sq, &msq_attr);
125 DRV_LOG(ERR, "Cannot change the Tx SQ state to RESET"
126 " %s", strerror(errno));
131 if (type != MLX5_TXQ_MOD_RDY2RST) {
132 /* Change queue state to ready. */
133 msq_attr.sq_state = MLX5_SQC_STATE_RST;
134 msq_attr.state = MLX5_SQC_STATE_RDY;
135 ret = mlx5_devx_cmd_modify_sq(obj->sq_obj.sq, &msq_attr);
137 DRV_LOG(ERR, "Cannot change the Tx SQ state to READY"
138 " %s", strerror(errno));
144 * The dev_port variable is relevant only in Verbs API, and there is a
145 * pointer that points to this function and a parallel function in verbs
146 * intermittently, so they should have the same parameters.
153 * Release an Rx DevX queue object.
159 mlx5_rxq_devx_obj_release(struct mlx5_rxq_priv *rxq)
161 struct mlx5_rxq_obj *rxq_obj = rxq->ctrl->obj;
165 if (rxq_obj->rxq_ctrl->type == MLX5_RXQ_TYPE_HAIRPIN) {
166 if (rxq_obj->rq == NULL)
168 mlx5_devx_modify_rq(rxq, MLX5_RXQ_MOD_RDY2RST);
169 claim_zero(mlx5_devx_cmd_destroy(rxq_obj->rq));
171 if (rxq->devx_rq.rq == NULL)
173 mlx5_devx_rq_destroy(&rxq->devx_rq);
174 if (rxq->devx_rq.rmp != NULL && rxq->devx_rq.rmp->ref_cnt > 0)
176 mlx5_devx_cq_destroy(&rxq_obj->cq_obj);
177 memset(&rxq_obj->cq_obj, 0, sizeof(rxq_obj->cq_obj));
178 if (rxq_obj->devx_channel) {
179 mlx5_os_devx_destroy_event_channel
180 (rxq_obj->devx_channel);
181 rxq_obj->devx_channel = NULL;
184 rxq->ctrl->started = false;
188 * Get event for an Rx DevX queue object.
191 * DevX Rx queue object.
194 * 0 on success, a negative errno value otherwise and rte_errno is set.
197 mlx5_rx_devx_get_event(struct mlx5_rxq_obj *rxq_obj)
199 #ifdef HAVE_IBV_DEVX_EVENT
201 struct mlx5dv_devx_async_event_hdr event_resp;
202 uint8_t buf[sizeof(struct mlx5dv_devx_async_event_hdr) + 128];
204 int ret = mlx5_glue->devx_get_event(rxq_obj->devx_channel,
212 if (out.event_resp.cookie != (uint64_t)(uintptr_t)rxq_obj->cq_obj.cq) {
221 #endif /* HAVE_IBV_DEVX_EVENT */
225 * Create a RQ object using DevX.
228 * Pointer to Rx queue.
231 * 0 on success, a negative errno value otherwise and rte_errno is set.
234 mlx5_rxq_create_devx_rq_resources(struct mlx5_rxq_priv *rxq)
236 struct mlx5_priv *priv = rxq->priv;
237 struct mlx5_common_device *cdev = priv->sh->cdev;
238 struct mlx5_rxq_ctrl *rxq_ctrl = rxq->ctrl;
239 struct mlx5_rxq_data *rxq_data = &rxq->ctrl->rxq;
240 struct mlx5_devx_create_rq_attr rq_attr = { 0 };
241 uint16_t log_desc_n = rxq_data->elts_n - rxq_data->sges_n;
242 uint32_t wqe_size, log_wqe_size;
244 /* Fill RQ attributes. */
245 rq_attr.mem_rq_type = MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE;
246 rq_attr.flush_in_error_en = 1;
247 rq_attr.vsd = (rxq_data->vlan_strip) ? 0 : 1;
248 rq_attr.cqn = rxq_ctrl->obj->cq_obj.cq->id;
249 rq_attr.scatter_fcs = (rxq_data->crc_present) ? 1 : 0;
251 mlx5_ts_format_conv(cdev->config.hca_attr.rq_ts_format);
252 /* Fill WQ attributes for this RQ. */
253 if (mlx5_rxq_mprq_enabled(rxq_data)) {
254 rq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ;
256 * Number of strides in each WQE:
257 * 512*2^single_wqe_log_num_of_strides.
259 rq_attr.wq_attr.single_wqe_log_num_of_strides =
260 rxq_data->strd_num_n -
261 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
262 /* Stride size = (2^single_stride_log_num_of_bytes)*64B. */
263 rq_attr.wq_attr.single_stride_log_num_of_bytes =
264 rxq_data->strd_sz_n -
265 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
266 wqe_size = sizeof(struct mlx5_wqe_mprq);
268 rq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC;
269 wqe_size = sizeof(struct mlx5_wqe_data_seg);
271 log_wqe_size = log2above(wqe_size) + rxq_data->sges_n;
272 wqe_size = 1 << log_wqe_size; /* round up power of two.*/
273 rq_attr.wq_attr.log_wq_stride = log_wqe_size;
274 rq_attr.wq_attr.log_wq_sz = log_desc_n;
275 rq_attr.wq_attr.end_padding_mode = priv->config.hw_padding ?
276 MLX5_WQ_END_PAD_MODE_ALIGN :
277 MLX5_WQ_END_PAD_MODE_NONE;
278 rq_attr.wq_attr.pd = cdev->pdn;
279 rq_attr.counter_set_id = priv->counter_set_id;
280 rq_attr.delay_drop_en = rxq_data->delay_drop;
281 rq_attr.user_index = rte_cpu_to_be_16(priv->dev_data->port_id);
282 if (rxq_data->shared) /* Create RMP based RQ. */
283 rxq->devx_rq.rmp = &rxq_ctrl->obj->devx_rmp;
284 /* Create RQ using DevX API. */
285 return mlx5_devx_rq_create(cdev->ctx, &rxq->devx_rq, wqe_size,
286 log_desc_n, &rq_attr, rxq_ctrl->socket);
290 * Create a DevX CQ object for an Rx queue.
293 * Pointer to Rx queue.
296 * 0 on success, a negative errno value otherwise and rte_errno is set.
299 mlx5_rxq_create_devx_cq_resources(struct mlx5_rxq_priv *rxq)
301 struct mlx5_devx_cq *cq_obj = 0;
302 struct mlx5_devx_cq_attr cq_attr = { 0 };
303 struct mlx5_priv *priv = rxq->priv;
304 struct mlx5_dev_ctx_shared *sh = priv->sh;
305 uint16_t port_id = priv->dev_data->port_id;
306 struct mlx5_rxq_ctrl *rxq_ctrl = rxq->ctrl;
307 struct mlx5_rxq_data *rxq_data = &rxq_ctrl->rxq;
308 unsigned int cqe_n = mlx5_rxq_cqe_num(rxq_data);
310 uint16_t event_nums[1] = { 0 };
313 if (rxq_ctrl->started)
315 if (priv->config.cqe_comp && !rxq_data->hw_timestamp &&
317 cq_attr.cqe_comp_en = 1u;
318 rxq_data->mcqe_format = priv->config.cqe_comp_fmt;
319 rxq_data->byte_mask = UINT32_MAX;
320 switch (priv->config.cqe_comp_fmt) {
321 case MLX5_CQE_RESP_FORMAT_HASH:
323 case MLX5_CQE_RESP_FORMAT_CSUM:
325 * Select CSUM miniCQE format only for non-vectorized
326 * MPRQ Rx burst, use HASH miniCQE format for others.
328 if (mlx5_rxq_check_vec_support(rxq_data) < 0 &&
329 mlx5_rxq_mprq_enabled(rxq_data))
330 cq_attr.mini_cqe_res_format =
331 MLX5_CQE_RESP_FORMAT_CSUM_STRIDX;
333 cq_attr.mini_cqe_res_format =
334 MLX5_CQE_RESP_FORMAT_HASH;
335 rxq_data->mcqe_format = cq_attr.mini_cqe_res_format;
337 case MLX5_CQE_RESP_FORMAT_FTAG_STRIDX:
338 rxq_data->byte_mask = MLX5_LEN_WITH_MARK_MASK;
340 case MLX5_CQE_RESP_FORMAT_CSUM_STRIDX:
341 cq_attr.mini_cqe_res_format = priv->config.cqe_comp_fmt;
343 case MLX5_CQE_RESP_FORMAT_L34H_STRIDX:
344 cq_attr.mini_cqe_res_format = 0;
345 cq_attr.mini_cqe_res_format_ext = 1;
349 "Port %u Rx CQE compression is enabled, format %d.",
350 port_id, priv->config.cqe_comp_fmt);
352 * For vectorized Rx, it must not be doubled in order to
353 * make cq_ci and rq_ci aligned.
355 if (mlx5_rxq_check_vec_support(rxq_data) < 0)
357 } else if (priv->config.cqe_comp && rxq_data->hw_timestamp) {
359 "Port %u Rx CQE compression is disabled for HW timestamp.",
361 } else if (priv->config.cqe_comp && rxq_data->lro) {
363 "Port %u Rx CQE compression is disabled for LRO.",
366 cq_attr.uar_page_id = mlx5_os_get_devx_uar_page_id(sh->devx_rx_uar);
367 log_cqe_n = log2above(cqe_n);
368 /* Create CQ using DevX API. */
369 ret = mlx5_devx_cq_create(sh->cdev->ctx, &rxq_ctrl->obj->cq_obj,
370 log_cqe_n, &cq_attr, sh->numa_node);
373 cq_obj = &rxq_ctrl->obj->cq_obj;
374 rxq_data->cqes = (volatile struct mlx5_cqe (*)[])
375 (uintptr_t)cq_obj->cqes;
376 rxq_data->cq_db = cq_obj->db_rec;
377 rxq_data->cq_uar = mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar);
378 rxq_data->cqe_n = log_cqe_n;
379 rxq_data->cqn = cq_obj->cq->id;
381 if (rxq_ctrl->obj->devx_channel) {
382 ret = mlx5_os_devx_subscribe_devx_event
383 (rxq_ctrl->obj->devx_channel,
387 (uint64_t)(uintptr_t)cq_obj->cq);
389 DRV_LOG(ERR, "Fail to subscribe CQ to event channel.");
391 mlx5_devx_cq_destroy(cq_obj);
392 memset(cq_obj, 0, sizeof(*cq_obj));
401 * Create the Rx hairpin queue object.
404 * Pointer to Rx queue.
407 * 0 on success, a negative errno value otherwise and rte_errno is set.
410 mlx5_rxq_obj_hairpin_new(struct mlx5_rxq_priv *rxq)
412 uint16_t idx = rxq->idx;
413 struct mlx5_priv *priv = rxq->priv;
414 struct mlx5_rxq_ctrl *rxq_ctrl = rxq->ctrl;
415 struct mlx5_devx_create_rq_attr attr = { 0 };
416 struct mlx5_rxq_obj *tmpl = rxq_ctrl->obj;
417 uint32_t max_wq_data;
419 MLX5_ASSERT(rxq != NULL && rxq->ctrl != NULL && tmpl != NULL);
420 tmpl->rxq_ctrl = rxq_ctrl;
422 max_wq_data = priv->config.hca_attr.log_max_hairpin_wq_data_sz;
423 /* Jumbo frames > 9KB should be supported, and more packets. */
424 if (priv->config.log_hp_size != (uint32_t)MLX5_ARG_UNSET) {
425 if (priv->config.log_hp_size > max_wq_data) {
426 DRV_LOG(ERR, "Total data size %u power of 2 is "
427 "too large for hairpin.",
428 priv->config.log_hp_size);
432 attr.wq_attr.log_hairpin_data_sz = priv->config.log_hp_size;
434 attr.wq_attr.log_hairpin_data_sz =
435 (max_wq_data < MLX5_HAIRPIN_JUMBO_LOG_SIZE) ?
436 max_wq_data : MLX5_HAIRPIN_JUMBO_LOG_SIZE;
438 /* Set the packets number to the maximum value for performance. */
439 attr.wq_attr.log_hairpin_num_packets =
440 attr.wq_attr.log_hairpin_data_sz -
441 MLX5_HAIRPIN_QUEUE_STRIDE;
442 attr.counter_set_id = priv->counter_set_id;
443 rxq_ctrl->rxq.delay_drop = priv->config.hp_delay_drop;
444 attr.delay_drop_en = priv->config.hp_delay_drop;
445 tmpl->rq = mlx5_devx_cmd_create_rq(priv->sh->cdev->ctx, &attr,
449 "Port %u Rx hairpin queue %u can't create rq object.",
450 priv->dev_data->port_id, idx);
454 priv->dev_data->rx_queue_state[idx] = RTE_ETH_QUEUE_STATE_HAIRPIN;
459 * Create the Rx queue DevX object.
462 * Pointer to Rx queue.
465 * 0 on success, a negative errno value otherwise and rte_errno is set.
468 mlx5_rxq_devx_obj_new(struct mlx5_rxq_priv *rxq)
470 struct mlx5_priv *priv = rxq->priv;
471 struct mlx5_rxq_ctrl *rxq_ctrl = rxq->ctrl;
472 struct mlx5_rxq_data *rxq_data = &rxq_ctrl->rxq;
473 struct mlx5_rxq_obj *tmpl = rxq_ctrl->obj;
476 MLX5_ASSERT(rxq_data);
478 if (rxq_ctrl->type == MLX5_RXQ_TYPE_HAIRPIN)
479 return mlx5_rxq_obj_hairpin_new(rxq);
480 tmpl->rxq_ctrl = rxq_ctrl;
481 if (rxq_ctrl->irq && !rxq_ctrl->started) {
483 MLX5DV_DEVX_CREATE_EVENT_CHANNEL_FLAGS_OMIT_EV_DATA;
485 tmpl->devx_channel = mlx5_os_devx_create_event_channel
486 (priv->sh->cdev->ctx,
488 if (!tmpl->devx_channel) {
490 DRV_LOG(ERR, "Failed to create event channel %d.",
494 tmpl->fd = mlx5_os_get_devx_channel_fd(tmpl->devx_channel);
496 /* Create CQ using DevX API. */
497 ret = mlx5_rxq_create_devx_cq_resources(rxq);
499 DRV_LOG(ERR, "Failed to create CQ.");
502 rxq_data->delay_drop = priv->config.std_delay_drop;
503 /* Create RQ using DevX API. */
504 ret = mlx5_rxq_create_devx_rq_resources(rxq);
506 DRV_LOG(ERR, "Port %u Rx queue %u RQ creation failure.",
507 priv->dev_data->port_id, rxq->idx);
511 /* Change queue state to ready. */
512 ret = mlx5_devx_modify_rq(rxq, MLX5_RXQ_MOD_RST2RDY);
515 if (!rxq_data->shared) {
516 rxq_data->wqes = (void *)(uintptr_t)rxq->devx_rq.wq.umem_buf;
517 rxq_data->rq_db = (uint32_t *)(uintptr_t)rxq->devx_rq.wq.db_rec;
518 } else if (!rxq_ctrl->started) {
519 rxq_data->wqes = (void *)(uintptr_t)tmpl->devx_rmp.wq.umem_buf;
521 (uint32_t *)(uintptr_t)tmpl->devx_rmp.wq.db_rec;
523 if (!rxq_ctrl->started) {
524 mlx5_rxq_initialize(rxq_data);
525 rxq_ctrl->wqn = rxq->devx_rq.rq->id;
527 priv->dev_data->rx_queue_state[rxq->idx] = RTE_ETH_QUEUE_STATE_STARTED;
530 ret = rte_errno; /* Save rte_errno before cleanup. */
531 mlx5_rxq_devx_obj_release(rxq);
532 rte_errno = ret; /* Restore rte_errno. */
537 * Prepare RQT attribute structure for DevX RQT API.
540 * Pointer to Ethernet device.
542 * Log of number of queues in the array.
544 * List of RX queue indices or NULL, in which case
545 * the attribute will be filled by drop queue ID.
547 * Size of @p queues array or 0 if it is NULL.
549 * DevX indirection table object.
552 * The RQT attr object initialized, NULL otherwise and rte_errno is set.
554 static struct mlx5_devx_rqt_attr *
555 mlx5_devx_ind_table_create_rqt_attr(struct rte_eth_dev *dev,
556 const unsigned int log_n,
557 const uint16_t *queues,
558 const uint32_t queues_n)
560 struct mlx5_priv *priv = dev->data->dev_private;
561 struct mlx5_devx_rqt_attr *rqt_attr = NULL;
562 const unsigned int rqt_n = 1 << log_n;
565 rqt_attr = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt_attr) +
566 rqt_n * sizeof(uint32_t), 0, SOCKET_ID_ANY);
568 DRV_LOG(ERR, "Port %u cannot allocate RQT resources.",
573 rqt_attr->rqt_max_size = priv->config.ind_table_max_size;
574 rqt_attr->rqt_actual_size = rqt_n;
575 if (queues == NULL) {
576 for (i = 0; i < rqt_n; i++)
577 rqt_attr->rq_list[i] =
578 priv->drop_queue.rxq->devx_rq.rq->id;
581 for (i = 0; i != queues_n; ++i) {
582 struct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, queues[i]);
584 MLX5_ASSERT(rxq != NULL);
585 if (rxq->ctrl->type == MLX5_RXQ_TYPE_HAIRPIN)
586 rqt_attr->rq_list[i] = rxq->ctrl->obj->rq->id;
588 rqt_attr->rq_list[i] = rxq->devx_rq.rq->id;
591 for (j = 0; i != rqt_n; ++j, ++i)
592 rqt_attr->rq_list[i] = rqt_attr->rq_list[j];
597 * Create RQT using DevX API as a filed of indirection table.
600 * Pointer to Ethernet device.
602 * Log of number of queues in the array.
604 * DevX indirection table object.
607 * 0 on success, a negative errno value otherwise and rte_errno is set.
610 mlx5_devx_ind_table_new(struct rte_eth_dev *dev, const unsigned int log_n,
611 struct mlx5_ind_table_obj *ind_tbl)
613 struct mlx5_priv *priv = dev->data->dev_private;
614 struct mlx5_devx_rqt_attr *rqt_attr = NULL;
615 const uint16_t *queues = dev->data->dev_started ? ind_tbl->queues :
618 MLX5_ASSERT(ind_tbl);
619 rqt_attr = mlx5_devx_ind_table_create_rqt_attr(dev, log_n, queues,
623 ind_tbl->rqt = mlx5_devx_cmd_create_rqt(priv->sh->cdev->ctx, rqt_attr);
626 DRV_LOG(ERR, "Port %u cannot create DevX RQT.",
635 * Modify RQT using DevX API as a filed of indirection table.
638 * Pointer to Ethernet device.
640 * Log of number of queues in the array.
642 * DevX indirection table object.
645 * 0 on success, a negative errno value otherwise and rte_errno is set.
648 mlx5_devx_ind_table_modify(struct rte_eth_dev *dev, const unsigned int log_n,
649 const uint16_t *queues, const uint32_t queues_n,
650 struct mlx5_ind_table_obj *ind_tbl)
653 struct mlx5_devx_rqt_attr *rqt_attr = NULL;
655 MLX5_ASSERT(ind_tbl);
656 rqt_attr = mlx5_devx_ind_table_create_rqt_attr(dev, log_n,
661 ret = mlx5_devx_cmd_modify_rqt(ind_tbl->rqt, rqt_attr);
664 DRV_LOG(ERR, "Port %u cannot modify DevX RQT.",
670 * Destroy the DevX RQT object.
673 * Indirection table to release.
676 mlx5_devx_ind_table_destroy(struct mlx5_ind_table_obj *ind_tbl)
678 claim_zero(mlx5_devx_cmd_destroy(ind_tbl->rqt));
682 * Set TIR attribute struct with relevant input values.
685 * Pointer to Ethernet device.
687 * RSS key for the Rx hash queue.
688 * @param[in] hash_fields
689 * Verbs protocol hash field to make the RSS on.
691 * Indirection table for TIR. If table queues array is NULL,
692 * a TIR for drop queue is assumed.
695 * @param[out] tir_attr
696 * Parameters structure for TIR creation/modification.
699 * The Verbs/DevX object initialised index, 0 otherwise and rte_errno is set.
702 mlx5_devx_tir_attr_set(struct rte_eth_dev *dev, const uint8_t *rss_key,
703 uint64_t hash_fields,
704 const struct mlx5_ind_table_obj *ind_tbl,
705 int tunnel, struct mlx5_devx_tir_attr *tir_attr)
707 struct mlx5_priv *priv = dev->data->dev_private;
708 enum mlx5_rxq_type rxq_obj_type;
712 /* NULL queues designate drop queue. */
713 if (ind_tbl->queues != NULL) {
714 struct mlx5_rxq_ctrl *rxq_ctrl =
715 mlx5_rxq_ctrl_get(dev, ind_tbl->queues[0]);
716 rxq_obj_type = rxq_ctrl != NULL ? rxq_ctrl->type :
717 MLX5_RXQ_TYPE_STANDARD;
719 /* Enable TIR LRO only if all the queues were configured for. */
720 for (i = 0; i < ind_tbl->queues_n; ++i) {
721 struct mlx5_rxq_data *rxq_i =
722 mlx5_rxq_data_get(dev, ind_tbl->queues[i]);
724 if (rxq_i != NULL && !rxq_i->lro) {
730 rxq_obj_type = priv->drop_queue.rxq->ctrl->type;
732 memset(tir_attr, 0, sizeof(*tir_attr));
733 tir_attr->disp_type = MLX5_TIRC_DISP_TYPE_INDIRECT;
734 tir_attr->rx_hash_fn = MLX5_RX_HASH_FN_TOEPLITZ;
735 tir_attr->tunneled_offload_en = !!tunnel;
736 /* If needed, translate hash_fields bitmap to PRM format. */
738 struct mlx5_rx_hash_field_select *rx_hash_field_select =
739 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
740 hash_fields & IBV_RX_HASH_INNER ?
741 &tir_attr->rx_hash_field_selector_inner :
743 &tir_attr->rx_hash_field_selector_outer;
744 /* 1 bit: 0: IPv4, 1: IPv6. */
745 rx_hash_field_select->l3_prot_type =
746 !!(hash_fields & MLX5_IPV6_IBV_RX_HASH);
747 /* 1 bit: 0: TCP, 1: UDP. */
748 rx_hash_field_select->l4_prot_type =
749 !!(hash_fields & MLX5_UDP_IBV_RX_HASH);
750 /* Bitmask which sets which fields to use in RX Hash. */
751 rx_hash_field_select->selected_fields =
752 ((!!(hash_fields & MLX5_L3_SRC_IBV_RX_HASH)) <<
753 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP) |
754 (!!(hash_fields & MLX5_L3_DST_IBV_RX_HASH)) <<
755 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP |
756 (!!(hash_fields & MLX5_L4_SRC_IBV_RX_HASH)) <<
757 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT |
758 (!!(hash_fields & MLX5_L4_DST_IBV_RX_HASH)) <<
759 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT;
761 if (rxq_obj_type == MLX5_RXQ_TYPE_HAIRPIN)
762 tir_attr->transport_domain = priv->sh->td->id;
764 tir_attr->transport_domain = priv->sh->tdn;
765 memcpy(tir_attr->rx_hash_toeplitz_key, rss_key, MLX5_RSS_HASH_KEY_LEN);
766 tir_attr->indirect_table = ind_tbl->rqt->id;
767 if (dev->data->dev_conf.lpbk_mode)
768 tir_attr->self_lb_block =
769 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
771 tir_attr->lro_timeout_period_usecs = priv->config.lro.timeout;
772 tir_attr->lro_max_msg_sz = priv->max_lro_msg_size;
773 tir_attr->lro_enable_mask =
774 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
775 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO;
780 * Create an Rx Hash queue.
783 * Pointer to Ethernet device.
785 * Pointer to Rx Hash queue.
790 * 0 on success, a negative errno value otherwise and rte_errno is set.
793 mlx5_devx_hrxq_new(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq,
794 int tunnel __rte_unused)
796 struct mlx5_priv *priv = dev->data->dev_private;
797 struct mlx5_devx_tir_attr tir_attr = {0};
800 mlx5_devx_tir_attr_set(dev, hrxq->rss_key, hrxq->hash_fields,
801 hrxq->ind_table, tunnel, &tir_attr);
802 hrxq->tir = mlx5_devx_cmd_create_tir(priv->sh->cdev->ctx, &tir_attr);
804 DRV_LOG(ERR, "Port %u cannot create DevX TIR.",
809 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
810 if (mlx5_flow_os_create_flow_action_dest_devx_tir(hrxq->tir,
818 err = rte_errno; /* Save rte_errno before cleanup. */
820 claim_zero(mlx5_devx_cmd_destroy(hrxq->tir));
821 rte_errno = err; /* Restore rte_errno. */
826 * Destroy a DevX TIR object.
829 * Hash Rx queue to release its tir.
832 mlx5_devx_tir_destroy(struct mlx5_hrxq *hrxq)
834 claim_zero(mlx5_devx_cmd_destroy(hrxq->tir));
838 * Modify an Rx Hash queue configuration.
841 * Pointer to Ethernet device.
843 * Hash Rx queue to modify.
845 * RSS key for the Rx hash queue.
847 * Verbs protocol hash field to make the RSS on.
849 * Indirection table for TIR.
852 * 0 on success, a negative errno value otherwise and rte_errno is set.
855 mlx5_devx_hrxq_modify(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq,
856 const uint8_t *rss_key,
857 uint64_t hash_fields,
858 const struct mlx5_ind_table_obj *ind_tbl)
860 struct mlx5_devx_modify_tir_attr modify_tir = {0};
863 * untested for modification fields:
864 * - rx_hash_symmetric not set in hrxq_new(),
865 * - rx_hash_fn set hard-coded in hrxq_new(),
866 * - lro_xxx not set after rxq setup
868 if (ind_tbl != hrxq->ind_table)
869 modify_tir.modify_bitmask |=
870 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE;
871 if (hash_fields != hrxq->hash_fields ||
872 memcmp(hrxq->rss_key, rss_key, MLX5_RSS_HASH_KEY_LEN))
873 modify_tir.modify_bitmask |=
874 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH;
875 mlx5_devx_tir_attr_set(dev, rss_key, hash_fields, ind_tbl,
876 0, /* N/A - tunnel modification unsupported */
878 modify_tir.tirn = hrxq->tir->id;
879 if (mlx5_devx_cmd_modify_tir(hrxq->tir, &modify_tir)) {
880 DRV_LOG(ERR, "port %u cannot modify DevX TIR",
889 * Create a DevX drop Rx queue.
892 * Pointer to Ethernet device.
895 * 0 on success, a negative errno value otherwise and rte_errno is set.
898 mlx5_rxq_devx_obj_drop_create(struct rte_eth_dev *dev)
900 struct mlx5_priv *priv = dev->data->dev_private;
901 int socket_id = dev->device->numa_node;
902 struct mlx5_rxq_priv *rxq;
903 struct mlx5_rxq_ctrl *rxq_ctrl = NULL;
904 struct mlx5_rxq_obj *rxq_obj = NULL;
908 * Initialize dummy control structures.
909 * They are required to hold pointers for cleanup
910 * and are only accessible via drop queue DevX objects.
912 rxq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rxq), 0, socket_id);
914 DRV_LOG(ERR, "Port %u could not allocate drop queue private",
919 rxq_ctrl = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rxq_ctrl),
921 if (rxq_ctrl == NULL) {
922 DRV_LOG(ERR, "Port %u could not allocate drop queue control",
927 rxq_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rxq_obj), 0, socket_id);
928 if (rxq_obj == NULL) {
929 DRV_LOG(ERR, "Port %u could not allocate drop queue object",
934 rxq_obj->rxq_ctrl = rxq_ctrl;
935 rxq_ctrl->type = MLX5_RXQ_TYPE_STANDARD;
936 rxq_ctrl->sh = priv->sh;
937 rxq_ctrl->obj = rxq_obj;
938 rxq->ctrl = rxq_ctrl;
940 LIST_INSERT_HEAD(&rxq_ctrl->owners, rxq, owner_entry);
941 /* Create CQ using DevX API. */
942 ret = mlx5_rxq_create_devx_cq_resources(rxq);
944 DRV_LOG(ERR, "Port %u drop queue CQ creation failed.",
948 rxq_ctrl->rxq.delay_drop = 0;
949 /* Create RQ using DevX API. */
950 ret = mlx5_rxq_create_devx_rq_resources(rxq);
952 DRV_LOG(ERR, "Port %u drop queue RQ creation failed.",
957 /* Change queue state to ready. */
958 ret = mlx5_devx_modify_rq(rxq, MLX5_RXQ_MOD_RST2RDY);
961 /* Initialize drop queue. */
962 priv->drop_queue.rxq = rxq;
965 ret = rte_errno; /* Save rte_errno before cleanup. */
966 if (rxq != NULL && rxq->devx_rq.rq != NULL)
967 mlx5_devx_rq_destroy(&rxq->devx_rq);
968 if (rxq_obj != NULL) {
969 if (rxq_obj->cq_obj.cq != NULL)
970 mlx5_devx_cq_destroy(&rxq_obj->cq_obj);
971 if (rxq_obj->devx_channel)
972 mlx5_os_devx_destroy_event_channel
973 (rxq_obj->devx_channel);
976 if (rxq_ctrl != NULL)
980 rte_errno = ret; /* Restore rte_errno. */
985 * Release drop Rx queue resources.
988 * Pointer to Ethernet device.
991 mlx5_rxq_devx_obj_drop_release(struct rte_eth_dev *dev)
993 struct mlx5_priv *priv = dev->data->dev_private;
994 struct mlx5_rxq_priv *rxq = priv->drop_queue.rxq;
995 struct mlx5_rxq_ctrl *rxq_ctrl = rxq->ctrl;
997 mlx5_rxq_devx_obj_release(rxq);
998 mlx5_free(rxq_ctrl->obj);
1001 priv->drop_queue.rxq = NULL;
1005 * Release a drop hash Rx queue.
1008 * Pointer to Ethernet device.
1011 mlx5_devx_drop_action_destroy(struct rte_eth_dev *dev)
1013 struct mlx5_priv *priv = dev->data->dev_private;
1014 struct mlx5_hrxq *hrxq = priv->drop_queue.hrxq;
1016 if (hrxq->tir != NULL)
1017 mlx5_devx_tir_destroy(hrxq);
1018 if (hrxq->ind_table->ind_table != NULL)
1019 mlx5_devx_ind_table_destroy(hrxq->ind_table);
1020 if (priv->drop_queue.rxq->devx_rq.rq != NULL)
1021 mlx5_rxq_devx_obj_drop_release(dev);
1025 * Create a DevX drop action for Rx Hash queue.
1028 * Pointer to Ethernet device.
1031 * 0 on success, a negative errno value otherwise and rte_errno is set.
1034 mlx5_devx_drop_action_create(struct rte_eth_dev *dev)
1036 struct mlx5_priv *priv = dev->data->dev_private;
1037 struct mlx5_hrxq *hrxq = priv->drop_queue.hrxq;
1040 ret = mlx5_rxq_devx_obj_drop_create(dev);
1042 DRV_LOG(ERR, "Cannot create drop RX queue");
1045 /* hrxq->ind_table queues are NULL, drop RX queue ID will be used */
1046 ret = mlx5_devx_ind_table_new(dev, 0, hrxq->ind_table);
1048 DRV_LOG(ERR, "Cannot create drop hash RX queue indirection table");
1051 ret = mlx5_devx_hrxq_new(dev, hrxq, /* tunnel */ false);
1053 DRV_LOG(ERR, "Cannot create drop hash RX queue");
1058 mlx5_devx_drop_action_destroy(dev);
1063 * Select TXQ TIS number.
1066 * Pointer to Ethernet device.
1068 * Queue index in DPDK Tx queue array.
1071 * > 0 on success, a negative errno value otherwise.
1074 mlx5_get_txq_tis_num(struct rte_eth_dev *dev, uint16_t queue_idx)
1076 struct mlx5_priv *priv = dev->data->dev_private;
1079 if (priv->sh->bond.n_port && priv->sh->lag.affinity_mode ==
1080 MLX5_LAG_MODE_TIS) {
1081 tis_idx = (priv->lag_affinity_idx + queue_idx) %
1082 priv->sh->bond.n_port;
1083 DRV_LOG(INFO, "port %d txq %d gets affinity %d and maps to PF %d.",
1084 dev->data->port_id, queue_idx, tis_idx + 1,
1085 priv->sh->lag.tx_remap_affinity[tis_idx]);
1089 MLX5_ASSERT(priv->sh->tis[tis_idx]);
1090 return priv->sh->tis[tis_idx]->id;
1094 * Create the Tx hairpin queue object.
1097 * Pointer to Ethernet device.
1099 * Queue index in DPDK Tx queue array.
1102 * 0 on success, a negative errno value otherwise and rte_errno is set.
1105 mlx5_txq_obj_hairpin_new(struct rte_eth_dev *dev, uint16_t idx)
1107 struct mlx5_priv *priv = dev->data->dev_private;
1108 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx];
1109 struct mlx5_txq_ctrl *txq_ctrl =
1110 container_of(txq_data, struct mlx5_txq_ctrl, txq);
1111 struct mlx5_devx_create_sq_attr attr = { 0 };
1112 struct mlx5_txq_obj *tmpl = txq_ctrl->obj;
1113 uint32_t max_wq_data;
1115 MLX5_ASSERT(txq_data);
1117 tmpl->txq_ctrl = txq_ctrl;
1119 attr.tis_lst_sz = 1;
1120 max_wq_data = priv->config.hca_attr.log_max_hairpin_wq_data_sz;
1121 /* Jumbo frames > 9KB should be supported, and more packets. */
1122 if (priv->config.log_hp_size != (uint32_t)MLX5_ARG_UNSET) {
1123 if (priv->config.log_hp_size > max_wq_data) {
1124 DRV_LOG(ERR, "Total data size %u power of 2 is "
1125 "too large for hairpin.",
1126 priv->config.log_hp_size);
1130 attr.wq_attr.log_hairpin_data_sz = priv->config.log_hp_size;
1132 attr.wq_attr.log_hairpin_data_sz =
1133 (max_wq_data < MLX5_HAIRPIN_JUMBO_LOG_SIZE) ?
1134 max_wq_data : MLX5_HAIRPIN_JUMBO_LOG_SIZE;
1136 /* Set the packets number to the maximum value for performance. */
1137 attr.wq_attr.log_hairpin_num_packets =
1138 attr.wq_attr.log_hairpin_data_sz -
1139 MLX5_HAIRPIN_QUEUE_STRIDE;
1141 attr.tis_num = mlx5_get_txq_tis_num(dev, idx);
1142 tmpl->sq = mlx5_devx_cmd_create_sq(priv->sh->cdev->ctx, &attr);
1145 "Port %u tx hairpin queue %u can't create SQ object.",
1146 dev->data->port_id, idx);
1153 #if defined(HAVE_MLX5DV_DEVX_UAR_OFFSET) || !defined(HAVE_INFINIBAND_VERBS_H)
1155 * Destroy the Tx queue DevX object.
1158 * Txq object to destroy.
1161 mlx5_txq_release_devx_resources(struct mlx5_txq_obj *txq_obj)
1163 mlx5_devx_sq_destroy(&txq_obj->sq_obj);
1164 memset(&txq_obj->sq_obj, 0, sizeof(txq_obj->sq_obj));
1165 mlx5_devx_cq_destroy(&txq_obj->cq_obj);
1166 memset(&txq_obj->cq_obj, 0, sizeof(txq_obj->cq_obj));
1170 * Create a SQ object and its resources using DevX.
1173 * Pointer to Ethernet device.
1175 * Queue index in DPDK Tx queue array.
1176 * @param[in] log_desc_n
1177 * Log of number of descriptors in queue.
1180 * 0 on success, a negative errno value otherwise and rte_errno is set.
1183 mlx5_txq_create_devx_sq_resources(struct rte_eth_dev *dev, uint16_t idx,
1184 uint16_t log_desc_n)
1186 struct mlx5_priv *priv = dev->data->dev_private;
1187 struct mlx5_common_device *cdev = priv->sh->cdev;
1188 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx];
1189 struct mlx5_txq_ctrl *txq_ctrl =
1190 container_of(txq_data, struct mlx5_txq_ctrl, txq);
1191 struct mlx5_txq_obj *txq_obj = txq_ctrl->obj;
1192 struct mlx5_devx_create_sq_attr sq_attr = {
1193 .flush_in_error_en = 1,
1194 .allow_multi_pkt_send_wqe = !!priv->config.mps,
1195 .min_wqe_inline_mode = priv->config.hca_attr.vport_inline_mode,
1196 .allow_swp = !!priv->config.swp,
1197 .cqn = txq_obj->cq_obj.cq->id,
1199 .wq_attr = (struct mlx5_devx_wq_attr){
1202 mlx5_os_get_devx_uar_page_id(priv->sh->tx_uar),
1205 mlx5_ts_format_conv(cdev->config.hca_attr.sq_ts_format),
1206 .tis_num = mlx5_get_txq_tis_num(dev, idx),
1209 /* Create Send Queue object with DevX. */
1210 return mlx5_devx_sq_create(cdev->ctx, &txq_obj->sq_obj,
1211 log_desc_n, &sq_attr, priv->sh->numa_node);
1216 * Create the Tx queue DevX object.
1219 * Pointer to Ethernet device.
1221 * Queue index in DPDK Tx queue array.
1224 * 0 on success, a negative errno value otherwise and rte_errno is set.
1227 mlx5_txq_devx_obj_new(struct rte_eth_dev *dev, uint16_t idx)
1229 struct mlx5_priv *priv = dev->data->dev_private;
1230 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx];
1231 struct mlx5_txq_ctrl *txq_ctrl =
1232 container_of(txq_data, struct mlx5_txq_ctrl, txq);
1234 if (txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN)
1235 return mlx5_txq_obj_hairpin_new(dev, idx);
1236 #if !defined(HAVE_MLX5DV_DEVX_UAR_OFFSET) && defined(HAVE_INFINIBAND_VERBS_H)
1237 DRV_LOG(ERR, "Port %u Tx queue %u cannot create with DevX, no UAR.",
1238 dev->data->port_id, idx);
1242 struct mlx5_dev_ctx_shared *sh = priv->sh;
1243 struct mlx5_txq_obj *txq_obj = txq_ctrl->obj;
1244 struct mlx5_devx_cq_attr cq_attr = {
1245 .uar_page_id = mlx5_os_get_devx_uar_page_id(sh->tx_uar),
1247 uint32_t cqe_n, log_desc_n;
1248 uint32_t wqe_n, wqe_size;
1251 MLX5_ASSERT(txq_data);
1252 MLX5_ASSERT(txq_obj);
1253 txq_obj->txq_ctrl = txq_ctrl;
1255 cqe_n = (1UL << txq_data->elts_n) / MLX5_TX_COMP_THRESH +
1256 1 + MLX5_TX_COMP_THRESH_INLINE_DIV;
1257 log_desc_n = log2above(cqe_n);
1258 cqe_n = 1UL << log_desc_n;
1259 if (cqe_n > UINT16_MAX) {
1260 DRV_LOG(ERR, "Port %u Tx queue %u requests to many CQEs %u.",
1261 dev->data->port_id, txq_data->idx, cqe_n);
1265 /* Create completion queue object with DevX. */
1266 ret = mlx5_devx_cq_create(sh->cdev->ctx, &txq_obj->cq_obj, log_desc_n,
1267 &cq_attr, priv->sh->numa_node);
1269 DRV_LOG(ERR, "Port %u Tx queue %u CQ creation failure.",
1270 dev->data->port_id, idx);
1273 txq_data->cqe_n = log_desc_n;
1274 txq_data->cqe_s = cqe_n;
1275 txq_data->cqe_m = txq_data->cqe_s - 1;
1276 txq_data->cqes = txq_obj->cq_obj.cqes;
1277 txq_data->cq_ci = 0;
1278 txq_data->cq_pi = 0;
1279 txq_data->cq_db = txq_obj->cq_obj.db_rec;
1280 *txq_data->cq_db = 0;
1282 * Adjust the amount of WQEs depending on inline settings.
1283 * The number of descriptors should be enough to handle
1284 * the specified number of packets. If queue is being created
1285 * with Verbs the rdma-core does queue size adjustment
1286 * internally in the mlx5_calc_sq_size(), we do the same
1287 * for the queue being created with DevX at this point.
1289 wqe_size = txq_data->tso_en ?
1290 RTE_ALIGN(txq_ctrl->max_tso_header, MLX5_WSEG_SIZE) : 0;
1291 wqe_size += sizeof(struct mlx5_wqe_cseg) +
1292 sizeof(struct mlx5_wqe_eseg) +
1293 sizeof(struct mlx5_wqe_dseg);
1294 if (txq_data->inlen_send)
1295 wqe_size = RTE_MAX(wqe_size, sizeof(struct mlx5_wqe_cseg) +
1296 sizeof(struct mlx5_wqe_eseg) +
1297 RTE_ALIGN(txq_data->inlen_send +
1300 wqe_size = RTE_ALIGN(wqe_size, MLX5_WQE_SIZE) / MLX5_WQE_SIZE;
1301 /* Create Send Queue object with DevX. */
1302 wqe_n = RTE_MIN((1UL << txq_data->elts_n) * wqe_size,
1303 (uint32_t)priv->sh->device_attr.max_qp_wr);
1304 log_desc_n = log2above(wqe_n);
1305 ret = mlx5_txq_create_devx_sq_resources(dev, idx, log_desc_n);
1307 DRV_LOG(ERR, "Port %u Tx queue %u SQ creation failure.",
1308 dev->data->port_id, idx);
1312 /* Create the Work Queue. */
1313 txq_data->wqe_n = log_desc_n;
1314 txq_data->wqe_s = 1 << txq_data->wqe_n;
1315 txq_data->wqe_m = txq_data->wqe_s - 1;
1316 txq_data->wqes = (struct mlx5_wqe *)(uintptr_t)txq_obj->sq_obj.wqes;
1317 txq_data->wqes_end = txq_data->wqes + txq_data->wqe_s;
1318 txq_data->wqe_ci = 0;
1319 txq_data->wqe_pi = 0;
1320 txq_data->wqe_comp = 0;
1321 txq_data->wqe_thres = txq_data->wqe_s / MLX5_TX_COMP_THRESH_INLINE_DIV;
1322 txq_data->qp_db = &txq_obj->sq_obj.db_rec[MLX5_SND_DBR];
1323 *txq_data->qp_db = 0;
1324 txq_data->qp_num_8s = txq_obj->sq_obj.sq->id << 8;
1325 /* Change Send Queue state to Ready-to-Send. */
1326 ret = mlx5_txq_devx_modify(txq_obj, MLX5_TXQ_MOD_RST2RDY, 0);
1330 "Port %u Tx queue %u SQ state to SQC_STATE_RDY failed.",
1331 dev->data->port_id, idx);
1334 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1336 * If using DevX need to query and store TIS transport domain value.
1337 * This is done once per port.
1338 * Will use this value on Rx, when creating matching TIR.
1341 priv->sh->tdn = priv->sh->td->id;
1343 MLX5_ASSERT(sh->tx_uar && mlx5_os_get_devx_uar_reg_addr(sh->tx_uar));
1344 txq_ctrl->uar_mmap_offset =
1345 mlx5_os_get_devx_uar_mmap_offset(sh->tx_uar);
1346 txq_uar_init(txq_ctrl, mlx5_os_get_devx_uar_reg_addr(sh->tx_uar));
1347 dev->data->tx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STARTED;
1350 ret = rte_errno; /* Save rte_errno before cleanup. */
1351 mlx5_txq_release_devx_resources(txq_obj);
1352 rte_errno = ret; /* Restore rte_errno. */
1358 * Release an Tx DevX queue object.
1361 * DevX Tx queue object.
1364 mlx5_txq_devx_obj_release(struct mlx5_txq_obj *txq_obj)
1366 MLX5_ASSERT(txq_obj);
1367 if (txq_obj->txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) {
1369 claim_zero(mlx5_devx_cmd_destroy(txq_obj->tis));
1370 #if defined(HAVE_MLX5DV_DEVX_UAR_OFFSET) || !defined(HAVE_INFINIBAND_VERBS_H)
1372 mlx5_txq_release_devx_resources(txq_obj);
1377 struct mlx5_obj_ops devx_obj_ops = {
1378 .rxq_obj_modify_vlan_strip = mlx5_rxq_obj_modify_rq_vlan_strip,
1379 .rxq_obj_new = mlx5_rxq_devx_obj_new,
1380 .rxq_event_get = mlx5_rx_devx_get_event,
1381 .rxq_obj_modify = mlx5_devx_modify_rq,
1382 .rxq_obj_release = mlx5_rxq_devx_obj_release,
1383 .ind_table_new = mlx5_devx_ind_table_new,
1384 .ind_table_modify = mlx5_devx_ind_table_modify,
1385 .ind_table_destroy = mlx5_devx_ind_table_destroy,
1386 .hrxq_new = mlx5_devx_hrxq_new,
1387 .hrxq_destroy = mlx5_devx_tir_destroy,
1388 .hrxq_modify = mlx5_devx_hrxq_modify,
1389 .drop_action_create = mlx5_devx_drop_action_create,
1390 .drop_action_destroy = mlx5_devx_drop_action_destroy,
1391 .txq_obj_new = mlx5_txq_devx_obj_new,
1392 .txq_obj_modify = mlx5_txq_devx_modify,
1393 .txq_obj_release = mlx5_txq_devx_obj_release,
1394 .lb_dummy_queue_create = NULL,
1395 .lb_dummy_queue_release = NULL,