1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2020 Mellanox Technologies, Ltd
10 #include <sys/queue.h>
12 #include <rte_malloc.h>
13 #include <rte_common.h>
14 #include <rte_eal_paging.h>
16 #include <mlx5_glue.h>
17 #include <mlx5_devx_cmds.h>
18 #include <mlx5_malloc.h>
21 #include "mlx5_common_os.h"
22 #include "mlx5_rxtx.h"
23 #include "mlx5_utils.h"
24 #include "mlx5_devx.h"
25 #include "mlx5_flow.h"
29 * Modify RQ vlan stripping offload
35 * 0 on success, non-0 otherwise
38 mlx5_rxq_obj_modify_rq_vlan_strip(struct mlx5_rxq_obj *rxq_obj, int on)
40 struct mlx5_devx_modify_rq_attr rq_attr;
42 memset(&rq_attr, 0, sizeof(rq_attr));
43 rq_attr.rq_state = MLX5_RQC_STATE_RDY;
44 rq_attr.state = MLX5_RQC_STATE_RDY;
45 rq_attr.vsd = (on ? 0 : 1);
46 rq_attr.modify_bitmask = MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD;
47 return mlx5_devx_cmd_modify_rq(rxq_obj->rq, &rq_attr);
51 * Modify RQ using DevX API.
54 * DevX Rx queue object.
56 * Type of change queue state.
59 * 0 on success, a negative errno value otherwise and rte_errno is set.
62 mlx5_devx_modify_rq(struct mlx5_rxq_obj *rxq_obj, uint8_t type)
64 struct mlx5_devx_modify_rq_attr rq_attr;
66 memset(&rq_attr, 0, sizeof(rq_attr));
68 case MLX5_RXQ_MOD_ERR2RST:
69 rq_attr.rq_state = MLX5_RQC_STATE_ERR;
70 rq_attr.state = MLX5_RQC_STATE_RST;
72 case MLX5_RXQ_MOD_RST2RDY:
73 rq_attr.rq_state = MLX5_RQC_STATE_RST;
74 rq_attr.state = MLX5_RQC_STATE_RDY;
76 case MLX5_RXQ_MOD_RDY2ERR:
77 rq_attr.rq_state = MLX5_RQC_STATE_RDY;
78 rq_attr.state = MLX5_RQC_STATE_ERR;
80 case MLX5_RXQ_MOD_RDY2RST:
81 rq_attr.rq_state = MLX5_RQC_STATE_RDY;
82 rq_attr.state = MLX5_RQC_STATE_RST;
87 return mlx5_devx_cmd_modify_rq(rxq_obj->rq, &rq_attr);
91 * Modify SQ using DevX API.
94 * DevX Tx queue object.
96 * Type of change queue state.
101 * 0 on success, a negative errno value otherwise and rte_errno is set.
104 mlx5_devx_modify_sq(struct mlx5_txq_obj *obj, enum mlx5_txq_modify_type type,
107 struct mlx5_devx_modify_sq_attr msq_attr = { 0 };
110 if (type != MLX5_TXQ_MOD_RST2RDY) {
111 /* Change queue state to reset. */
112 if (type == MLX5_TXQ_MOD_ERR2RDY)
113 msq_attr.sq_state = MLX5_SQC_STATE_ERR;
115 msq_attr.sq_state = MLX5_SQC_STATE_RDY;
116 msq_attr.state = MLX5_SQC_STATE_RST;
117 ret = mlx5_devx_cmd_modify_sq(obj->sq_devx, &msq_attr);
119 DRV_LOG(ERR, "Cannot change the Tx SQ state to RESET"
120 " %s", strerror(errno));
125 if (type != MLX5_TXQ_MOD_RDY2RST) {
126 /* Change queue state to ready. */
127 msq_attr.sq_state = MLX5_SQC_STATE_RST;
128 msq_attr.state = MLX5_SQC_STATE_RDY;
129 ret = mlx5_devx_cmd_modify_sq(obj->sq_devx, &msq_attr);
131 DRV_LOG(ERR, "Cannot change the Tx SQ state to READY"
132 " %s", strerror(errno));
138 * The dev_port variable is relevant only in Verbs API, and there is a
139 * pointer that points to this function and a parallel function in verbs
140 * intermittently, so they should have the same parameters.
147 * Release the resources allocated for an RQ DevX object.
150 * DevX Rx queue object.
153 mlx5_rxq_release_devx_rq_resources(struct mlx5_rxq_ctrl *rxq_ctrl)
155 struct mlx5_devx_dbr_page *dbr_page = rxq_ctrl->rq_dbrec_page;
157 if (rxq_ctrl->rxq.wqes) {
158 mlx5_free((void *)(uintptr_t)rxq_ctrl->rxq.wqes);
159 rxq_ctrl->rxq.wqes = NULL;
161 if (rxq_ctrl->wq_umem) {
162 mlx5_glue->devx_umem_dereg(rxq_ctrl->wq_umem);
163 rxq_ctrl->wq_umem = NULL;
166 claim_zero(mlx5_release_dbr(&rxq_ctrl->priv->dbrpgs,
167 mlx5_os_get_umem_id(dbr_page->umem),
168 rxq_ctrl->rq_dbr_offset));
169 rxq_ctrl->rq_dbrec_page = NULL;
174 * Release the resources allocated for the Rx CQ DevX object.
177 * DevX Rx queue object.
180 mlx5_rxq_release_devx_cq_resources(struct mlx5_rxq_ctrl *rxq_ctrl)
182 struct mlx5_devx_dbr_page *dbr_page = rxq_ctrl->cq_dbrec_page;
184 if (rxq_ctrl->rxq.cqes) {
185 rte_free((void *)(uintptr_t)rxq_ctrl->rxq.cqes);
186 rxq_ctrl->rxq.cqes = NULL;
188 if (rxq_ctrl->cq_umem) {
189 mlx5_glue->devx_umem_dereg(rxq_ctrl->cq_umem);
190 rxq_ctrl->cq_umem = NULL;
193 claim_zero(mlx5_release_dbr(&rxq_ctrl->priv->dbrpgs,
194 mlx5_os_get_umem_id(dbr_page->umem),
195 rxq_ctrl->cq_dbr_offset));
196 rxq_ctrl->cq_dbrec_page = NULL;
201 * Release an Rx DevX queue object.
204 * DevX Rx queue object.
207 mlx5_rxq_devx_obj_release(struct mlx5_rxq_obj *rxq_obj)
209 MLX5_ASSERT(rxq_obj);
210 MLX5_ASSERT(rxq_obj->rq);
211 if (rxq_obj->rxq_ctrl->type == MLX5_RXQ_TYPE_HAIRPIN) {
212 mlx5_devx_modify_rq(rxq_obj, MLX5_RXQ_MOD_RDY2RST);
213 claim_zero(mlx5_devx_cmd_destroy(rxq_obj->rq));
215 MLX5_ASSERT(rxq_obj->devx_cq);
216 claim_zero(mlx5_devx_cmd_destroy(rxq_obj->rq));
217 claim_zero(mlx5_devx_cmd_destroy(rxq_obj->devx_cq));
218 if (rxq_obj->devx_channel)
219 mlx5_glue->devx_destroy_event_channel
220 (rxq_obj->devx_channel);
221 mlx5_rxq_release_devx_rq_resources(rxq_obj->rxq_ctrl);
222 mlx5_rxq_release_devx_cq_resources(rxq_obj->rxq_ctrl);
227 * Get event for an Rx DevX queue object.
230 * DevX Rx queue object.
233 * 0 on success, a negative errno value otherwise and rte_errno is set.
236 mlx5_rx_devx_get_event(struct mlx5_rxq_obj *rxq_obj)
238 #ifdef HAVE_IBV_DEVX_EVENT
240 struct mlx5dv_devx_async_event_hdr event_resp;
241 uint8_t buf[sizeof(struct mlx5dv_devx_async_event_hdr) + 128];
243 int ret = mlx5_glue->devx_get_event(rxq_obj->devx_channel,
251 if (out.event_resp.cookie != (uint64_t)(uintptr_t)rxq_obj->devx_cq) {
260 #endif /* HAVE_IBV_DEVX_EVENT */
264 * Fill common fields of create RQ attributes structure.
267 * Pointer to Rx queue data.
269 * CQ number to use with this RQ.
271 * RQ attributes structure to fill..
274 mlx5_devx_create_rq_attr_fill(struct mlx5_rxq_data *rxq_data, uint32_t cqn,
275 struct mlx5_devx_create_rq_attr *rq_attr)
277 rq_attr->state = MLX5_RQC_STATE_RST;
278 rq_attr->vsd = (rxq_data->vlan_strip) ? 0 : 1;
280 rq_attr->scatter_fcs = (rxq_data->crc_present) ? 1 : 0;
284 * Fill common fields of DevX WQ attributes structure.
287 * Pointer to device private data.
289 * Pointer to Rx queue control structure.
291 * WQ attributes structure to fill..
294 mlx5_devx_wq_attr_fill(struct mlx5_priv *priv, struct mlx5_rxq_ctrl *rxq_ctrl,
295 struct mlx5_devx_wq_attr *wq_attr)
297 wq_attr->end_padding_mode = priv->config.hw_padding ?
298 MLX5_WQ_END_PAD_MODE_ALIGN :
299 MLX5_WQ_END_PAD_MODE_NONE;
300 wq_attr->pd = priv->sh->pdn;
301 wq_attr->dbr_addr = rxq_ctrl->rq_dbr_offset;
302 wq_attr->dbr_umem_id =
303 mlx5_os_get_umem_id(rxq_ctrl->rq_dbrec_page->umem);
304 wq_attr->dbr_umem_valid = 1;
305 wq_attr->wq_umem_id = mlx5_os_get_umem_id(rxq_ctrl->wq_umem);
306 wq_attr->wq_umem_valid = 1;
310 * Create a RQ object using DevX.
313 * Pointer to Ethernet device.
315 * Queue index in DPDK Rx queue array.
318 * The DevX RQ object initialized, NULL otherwise and rte_errno is set.
320 static struct mlx5_devx_obj *
321 mlx5_rxq_create_devx_rq_resources(struct rte_eth_dev *dev, uint16_t idx)
323 struct mlx5_priv *priv = dev->data->dev_private;
324 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
325 struct mlx5_rxq_ctrl *rxq_ctrl =
326 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
327 struct mlx5_devx_create_rq_attr rq_attr = { 0 };
328 uint32_t wqe_n = 1 << (rxq_data->elts_n - rxq_data->sges_n);
329 uint32_t cqn = rxq_ctrl->obj->devx_cq->id;
330 struct mlx5_devx_dbr_page *dbr_page;
332 uint32_t wq_size = 0;
333 uint32_t wqe_size = 0;
334 uint32_t log_wqe_size = 0;
336 struct mlx5_devx_obj *rq;
338 /* Fill RQ attributes. */
339 rq_attr.mem_rq_type = MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE;
340 rq_attr.flush_in_error_en = 1;
341 mlx5_devx_create_rq_attr_fill(rxq_data, cqn, &rq_attr);
342 /* Fill WQ attributes for this RQ. */
343 if (mlx5_rxq_mprq_enabled(rxq_data)) {
344 rq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ;
346 * Number of strides in each WQE:
347 * 512*2^single_wqe_log_num_of_strides.
349 rq_attr.wq_attr.single_wqe_log_num_of_strides =
350 rxq_data->strd_num_n -
351 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
352 /* Stride size = (2^single_stride_log_num_of_bytes)*64B. */
353 rq_attr.wq_attr.single_stride_log_num_of_bytes =
354 rxq_data->strd_sz_n -
355 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
356 wqe_size = sizeof(struct mlx5_wqe_mprq);
358 rq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC;
359 wqe_size = sizeof(struct mlx5_wqe_data_seg);
361 log_wqe_size = log2above(wqe_size) + rxq_data->sges_n;
362 rq_attr.wq_attr.log_wq_stride = log_wqe_size;
363 rq_attr.wq_attr.log_wq_sz = rxq_data->elts_n - rxq_data->sges_n;
364 /* Calculate and allocate WQ memory space. */
365 wqe_size = 1 << log_wqe_size; /* round up power of two.*/
366 wq_size = wqe_n * wqe_size;
367 size_t alignment = MLX5_WQE_BUF_ALIGNMENT;
368 if (alignment == (size_t)-1) {
369 DRV_LOG(ERR, "Failed to get mem page size");
373 buf = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, wq_size,
374 alignment, rxq_ctrl->socket);
377 rxq_data->wqes = buf;
378 rxq_ctrl->wq_umem = mlx5_glue->devx_umem_reg(priv->sh->ctx,
380 if (!rxq_ctrl->wq_umem)
382 /* Allocate RQ door-bell. */
383 dbr_offset = mlx5_get_dbr(priv->sh->ctx, &priv->dbrpgs, &dbr_page);
384 if (dbr_offset < 0) {
385 DRV_LOG(ERR, "Failed to allocate RQ door-bell.");
388 rxq_ctrl->rq_dbr_offset = dbr_offset;
389 rxq_ctrl->rq_dbrec_page = dbr_page;
390 rxq_data->rq_db = (uint32_t *)((uintptr_t)dbr_page->dbrs +
391 (uintptr_t)rxq_ctrl->rq_dbr_offset);
392 /* Create RQ using DevX API. */
393 mlx5_devx_wq_attr_fill(priv, rxq_ctrl, &rq_attr.wq_attr);
394 rq = mlx5_devx_cmd_create_rq(priv->sh->ctx, &rq_attr, rxq_ctrl->socket);
399 mlx5_rxq_release_devx_rq_resources(rxq_ctrl);
404 * Create a DevX CQ object for an Rx queue.
407 * Pointer to Ethernet device.
409 * Queue index in DPDK Rx queue array.
412 * The DevX CQ object initialized, NULL otherwise and rte_errno is set.
414 static struct mlx5_devx_obj *
415 mlx5_rxq_create_devx_cq_resources(struct rte_eth_dev *dev, uint16_t idx)
417 struct mlx5_devx_obj *cq_obj = 0;
418 struct mlx5_devx_cq_attr cq_attr = { 0 };
419 struct mlx5_priv *priv = dev->data->dev_private;
420 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
421 struct mlx5_rxq_ctrl *rxq_ctrl =
422 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
423 size_t page_size = rte_mem_page_size();
424 unsigned int cqe_n = mlx5_rxq_cqe_num(rxq_data);
425 struct mlx5_devx_dbr_page *dbr_page;
428 uint16_t event_nums[1] = {0};
433 if (page_size == (size_t)-1) {
434 DRV_LOG(ERR, "Failed to get page_size.");
437 if (priv->config.cqe_comp && !rxq_data->hw_timestamp &&
439 cq_attr.cqe_comp_en = 1u;
440 rxq_data->mcqe_format = priv->config.cqe_comp_fmt;
441 rxq_data->byte_mask = UINT32_MAX;
442 switch (priv->config.cqe_comp_fmt) {
443 case MLX5_CQE_RESP_FORMAT_HASH:
445 case MLX5_CQE_RESP_FORMAT_CSUM:
447 * Select CSUM miniCQE format only for non-vectorized
448 * MPRQ Rx burst, use HASH miniCQE format for others.
450 if (mlx5_rxq_check_vec_support(rxq_data) < 0 &&
451 mlx5_rxq_mprq_enabled(rxq_data))
452 cq_attr.mini_cqe_res_format =
453 MLX5_CQE_RESP_FORMAT_CSUM_STRIDX;
455 cq_attr.mini_cqe_res_format =
456 MLX5_CQE_RESP_FORMAT_HASH;
457 rxq_data->mcqe_format = cq_attr.mini_cqe_res_format;
459 case MLX5_CQE_RESP_FORMAT_FTAG_STRIDX:
460 rxq_data->byte_mask = MLX5_LEN_WITH_MARK_MASK;
462 case MLX5_CQE_RESP_FORMAT_CSUM_STRIDX:
463 cq_attr.mini_cqe_res_format = priv->config.cqe_comp_fmt;
465 case MLX5_CQE_RESP_FORMAT_L34H_STRIDX:
466 cq_attr.mini_cqe_res_format = 0;
467 cq_attr.mini_cqe_res_format_ext = 1;
471 "Port %u Rx CQE compression is enabled, format %d.",
472 dev->data->port_id, priv->config.cqe_comp_fmt);
474 * For vectorized Rx, it must not be doubled in order to
475 * make cq_ci and rq_ci aligned.
477 if (mlx5_rxq_check_vec_support(rxq_data) < 0)
479 } else if (priv->config.cqe_comp && rxq_data->hw_timestamp) {
481 "Port %u Rx CQE compression is disabled for HW"
484 } else if (priv->config.cqe_comp && rxq_data->lro) {
486 "Port %u Rx CQE compression is disabled for LRO.",
489 if (priv->config.cqe_pad)
490 cq_attr.cqe_size = MLX5_CQE_SIZE_128B;
491 log_cqe_n = log2above(cqe_n);
492 cq_size = sizeof(struct mlx5_cqe) * (1 << log_cqe_n);
493 buf = rte_calloc_socket(__func__, 1, cq_size, page_size,
496 DRV_LOG(ERR, "Failed to allocate memory for CQ.");
499 rxq_data->cqes = (volatile struct mlx5_cqe (*)[])(uintptr_t)buf;
500 rxq_ctrl->cq_umem = mlx5_glue->devx_umem_reg(priv->sh->ctx, buf,
502 IBV_ACCESS_LOCAL_WRITE);
503 if (!rxq_ctrl->cq_umem) {
504 DRV_LOG(ERR, "Failed to register umem for CQ.");
507 /* Allocate CQ door-bell. */
508 dbr_offset = mlx5_get_dbr(priv->sh->ctx, &priv->dbrpgs, &dbr_page);
509 if (dbr_offset < 0) {
510 DRV_LOG(ERR, "Failed to allocate CQ door-bell.");
513 rxq_ctrl->cq_dbr_offset = dbr_offset;
514 rxq_ctrl->cq_dbrec_page = dbr_page;
515 rxq_data->cq_db = (uint32_t *)((uintptr_t)dbr_page->dbrs +
516 (uintptr_t)rxq_ctrl->cq_dbr_offset);
518 mlx5_os_get_devx_uar_base_addr(priv->sh->devx_rx_uar);
519 /* Create CQ using DevX API. */
520 cq_attr.eqn = priv->sh->eqn;
521 cq_attr.uar_page_id =
522 mlx5_os_get_devx_uar_page_id(priv->sh->devx_rx_uar);
523 cq_attr.q_umem_id = mlx5_os_get_umem_id(rxq_ctrl->cq_umem);
524 cq_attr.q_umem_valid = 1;
525 cq_attr.log_cq_size = log_cqe_n;
526 cq_attr.log_page_size = rte_log2_u32(page_size);
527 cq_attr.db_umem_offset = rxq_ctrl->cq_dbr_offset;
528 cq_attr.db_umem_id = mlx5_os_get_umem_id(dbr_page->umem);
529 cq_attr.db_umem_valid = 1;
530 cq_obj = mlx5_devx_cmd_create_cq(priv->sh->ctx, &cq_attr);
533 rxq_data->cqe_n = log_cqe_n;
534 rxq_data->cqn = cq_obj->id;
535 if (rxq_ctrl->obj->devx_channel) {
536 ret = mlx5_glue->devx_subscribe_devx_event
537 (rxq_ctrl->obj->devx_channel,
541 (uint64_t)(uintptr_t)cq_obj);
543 DRV_LOG(ERR, "Fail to subscribe CQ to event channel.");
548 /* Initialise CQ to 1's to mark HW ownership for all CQEs. */
549 memset((void *)(uintptr_t)rxq_data->cqes, 0xFF, cq_size);
553 mlx5_devx_cmd_destroy(cq_obj);
554 mlx5_rxq_release_devx_cq_resources(rxq_ctrl);
559 * Create the Rx hairpin queue object.
562 * Pointer to Ethernet device.
564 * Queue index in DPDK Rx queue array.
567 * 0 on success, a negative errno value otherwise and rte_errno is set.
570 mlx5_rxq_obj_hairpin_new(struct rte_eth_dev *dev, uint16_t idx)
572 struct mlx5_priv *priv = dev->data->dev_private;
573 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
574 struct mlx5_rxq_ctrl *rxq_ctrl =
575 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
576 struct mlx5_devx_create_rq_attr attr = { 0 };
577 struct mlx5_rxq_obj *tmpl = rxq_ctrl->obj;
578 uint32_t max_wq_data;
580 MLX5_ASSERT(rxq_data);
582 tmpl->rxq_ctrl = rxq_ctrl;
584 max_wq_data = priv->config.hca_attr.log_max_hairpin_wq_data_sz;
585 /* Jumbo frames > 9KB should be supported, and more packets. */
586 if (priv->config.log_hp_size != (uint32_t)MLX5_ARG_UNSET) {
587 if (priv->config.log_hp_size > max_wq_data) {
588 DRV_LOG(ERR, "Total data size %u power of 2 is "
589 "too large for hairpin.",
590 priv->config.log_hp_size);
594 attr.wq_attr.log_hairpin_data_sz = priv->config.log_hp_size;
596 attr.wq_attr.log_hairpin_data_sz =
597 (max_wq_data < MLX5_HAIRPIN_JUMBO_LOG_SIZE) ?
598 max_wq_data : MLX5_HAIRPIN_JUMBO_LOG_SIZE;
600 /* Set the packets number to the maximum value for performance. */
601 attr.wq_attr.log_hairpin_num_packets =
602 attr.wq_attr.log_hairpin_data_sz -
603 MLX5_HAIRPIN_QUEUE_STRIDE;
604 tmpl->rq = mlx5_devx_cmd_create_rq(priv->sh->ctx, &attr,
608 "Port %u Rx hairpin queue %u can't create rq object.",
609 dev->data->port_id, idx);
613 dev->data->rx_queue_state[idx] = RTE_ETH_QUEUE_STATE_HAIRPIN;
618 * Create the Rx queue DevX object.
621 * Pointer to Ethernet device.
623 * Queue index in DPDK Rx queue array.
626 * 0 on success, a negative errno value otherwise and rte_errno is set.
629 mlx5_rxq_devx_obj_new(struct rte_eth_dev *dev, uint16_t idx)
631 struct mlx5_priv *priv = dev->data->dev_private;
632 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
633 struct mlx5_rxq_ctrl *rxq_ctrl =
634 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
635 struct mlx5_rxq_obj *tmpl = rxq_ctrl->obj;
638 MLX5_ASSERT(rxq_data);
640 if (rxq_ctrl->type == MLX5_RXQ_TYPE_HAIRPIN)
641 return mlx5_rxq_obj_hairpin_new(dev, idx);
642 tmpl->rxq_ctrl = rxq_ctrl;
645 MLX5DV_DEVX_CREATE_EVENT_CHANNEL_FLAGS_OMIT_EV_DATA;
647 tmpl->devx_channel = mlx5_glue->devx_create_event_channel
650 if (!tmpl->devx_channel) {
652 DRV_LOG(ERR, "Failed to create event channel %d.",
656 tmpl->fd = mlx5_os_get_devx_channel_fd(tmpl->devx_channel);
658 /* Create CQ using DevX API. */
659 tmpl->devx_cq = mlx5_rxq_create_devx_cq_resources(dev, idx);
660 if (!tmpl->devx_cq) {
661 DRV_LOG(ERR, "Failed to create CQ.");
664 /* Create RQ using DevX API. */
665 tmpl->rq = mlx5_rxq_create_devx_rq_resources(dev, idx);
667 DRV_LOG(ERR, "Port %u Rx queue %u RQ creation failure.",
668 dev->data->port_id, idx);
672 /* Change queue state to ready. */
673 ret = mlx5_devx_modify_rq(tmpl, MLX5_RXQ_MOD_RST2RDY);
676 rxq_data->cq_arm_sn = 0;
677 mlx5_rxq_initialize(rxq_data);
679 dev->data->rx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STARTED;
680 rxq_ctrl->wqn = tmpl->rq->id;
683 ret = rte_errno; /* Save rte_errno before cleanup. */
685 claim_zero(mlx5_devx_cmd_destroy(tmpl->rq));
687 claim_zero(mlx5_devx_cmd_destroy(tmpl->devx_cq));
688 if (tmpl->devx_channel)
689 mlx5_glue->devx_destroy_event_channel(tmpl->devx_channel);
690 mlx5_rxq_release_devx_rq_resources(rxq_ctrl);
691 mlx5_rxq_release_devx_cq_resources(rxq_ctrl);
692 rte_errno = ret; /* Restore rte_errno. */
697 * Create RQT using DevX API as a filed of indirection table.
700 * Pointer to Ethernet device.
702 * Log of number of queues in the array.
704 * DevX indirection table object.
707 * 0 on success, a negative errno value otherwise and rte_errno is set.
710 mlx5_devx_ind_table_new(struct rte_eth_dev *dev, const unsigned int log_n,
711 struct mlx5_ind_table_obj *ind_tbl)
713 struct mlx5_priv *priv = dev->data->dev_private;
714 struct mlx5_devx_rqt_attr *rqt_attr = NULL;
715 const unsigned int rqt_n = 1 << log_n;
718 MLX5_ASSERT(ind_tbl);
719 rqt_attr = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt_attr) +
720 rqt_n * sizeof(uint32_t), 0, SOCKET_ID_ANY);
722 DRV_LOG(ERR, "Port %u cannot allocate RQT resources.",
727 rqt_attr->rqt_max_size = priv->config.ind_table_max_size;
728 rqt_attr->rqt_actual_size = rqt_n;
729 for (i = 0; i != ind_tbl->queues_n; ++i) {
730 struct mlx5_rxq_data *rxq = (*priv->rxqs)[ind_tbl->queues[i]];
731 struct mlx5_rxq_ctrl *rxq_ctrl =
732 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
734 rqt_attr->rq_list[i] = rxq_ctrl->obj->rq->id;
737 for (j = 0; i != rqt_n; ++j, ++i)
738 rqt_attr->rq_list[i] = rqt_attr->rq_list[j];
739 ind_tbl->rqt = mlx5_devx_cmd_create_rqt(priv->sh->ctx, rqt_attr);
742 DRV_LOG(ERR, "Port %u cannot create DevX RQT.",
751 * Destroy the DevX RQT object.
754 * Indirection table to release.
757 mlx5_devx_ind_table_destroy(struct mlx5_ind_table_obj *ind_tbl)
759 claim_zero(mlx5_devx_cmd_destroy(ind_tbl->rqt));
763 * Set TIR attribute struct with relevant input values.
766 * Pointer to Ethernet device.
768 * RSS key for the Rx hash queue.
769 * @param[in] hash_fields
770 * Verbs protocol hash field to make the RSS on.
772 * Indirection table for TIR.
775 * @param[out] tir_attr
776 * Parameters structure for TIR creation/modification.
779 * The Verbs/DevX object initialised index, 0 otherwise and rte_errno is set.
782 mlx5_devx_tir_attr_set(struct rte_eth_dev *dev, const uint8_t *rss_key,
783 uint64_t hash_fields,
784 const struct mlx5_ind_table_obj *ind_tbl,
785 int tunnel, struct mlx5_devx_tir_attr *tir_attr)
787 struct mlx5_priv *priv = dev->data->dev_private;
788 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[ind_tbl->queues[0]];
789 struct mlx5_rxq_ctrl *rxq_ctrl =
790 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
791 enum mlx5_rxq_type rxq_obj_type = rxq_ctrl->type;
795 /* Enable TIR LRO only if all the queues were configured for. */
796 for (i = 0; i < ind_tbl->queues_n; ++i) {
797 if (!(*priv->rxqs)[ind_tbl->queues[i]]->lro) {
802 memset(tir_attr, 0, sizeof(*tir_attr));
803 tir_attr->disp_type = MLX5_TIRC_DISP_TYPE_INDIRECT;
804 tir_attr->rx_hash_fn = MLX5_RX_HASH_FN_TOEPLITZ;
805 tir_attr->tunneled_offload_en = !!tunnel;
806 /* If needed, translate hash_fields bitmap to PRM format. */
808 struct mlx5_rx_hash_field_select *rx_hash_field_select =
809 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
810 hash_fields & IBV_RX_HASH_INNER ?
811 &tir_attr->rx_hash_field_selector_inner :
813 &tir_attr->rx_hash_field_selector_outer;
814 /* 1 bit: 0: IPv4, 1: IPv6. */
815 rx_hash_field_select->l3_prot_type =
816 !!(hash_fields & MLX5_IPV6_IBV_RX_HASH);
817 /* 1 bit: 0: TCP, 1: UDP. */
818 rx_hash_field_select->l4_prot_type =
819 !!(hash_fields & MLX5_UDP_IBV_RX_HASH);
820 /* Bitmask which sets which fields to use in RX Hash. */
821 rx_hash_field_select->selected_fields =
822 ((!!(hash_fields & MLX5_L3_SRC_IBV_RX_HASH)) <<
823 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP) |
824 (!!(hash_fields & MLX5_L3_DST_IBV_RX_HASH)) <<
825 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP |
826 (!!(hash_fields & MLX5_L4_SRC_IBV_RX_HASH)) <<
827 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT |
828 (!!(hash_fields & MLX5_L4_DST_IBV_RX_HASH)) <<
829 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT;
831 if (rxq_obj_type == MLX5_RXQ_TYPE_HAIRPIN)
832 tir_attr->transport_domain = priv->sh->td->id;
834 tir_attr->transport_domain = priv->sh->tdn;
835 memcpy(tir_attr->rx_hash_toeplitz_key, rss_key, MLX5_RSS_HASH_KEY_LEN);
836 tir_attr->indirect_table = ind_tbl->rqt->id;
837 if (dev->data->dev_conf.lpbk_mode)
838 tir_attr->self_lb_block =
839 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
841 tir_attr->lro_timeout_period_usecs = priv->config.lro.timeout;
842 tir_attr->lro_max_msg_sz = priv->max_lro_msg_size;
843 tir_attr->lro_enable_mask =
844 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
845 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO;
850 * Create an Rx Hash queue.
853 * Pointer to Ethernet device.
855 * Pointer to Rx Hash queue.
860 * 0 on success, a negative errno value otherwise and rte_errno is set.
863 mlx5_devx_hrxq_new(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq,
864 int tunnel __rte_unused)
866 struct mlx5_priv *priv = dev->data->dev_private;
867 struct mlx5_devx_tir_attr tir_attr = {0};
870 mlx5_devx_tir_attr_set(dev, hrxq->rss_key, hrxq->hash_fields,
871 hrxq->ind_table, tunnel, &tir_attr);
872 hrxq->tir = mlx5_devx_cmd_create_tir(priv->sh->ctx, &tir_attr);
874 DRV_LOG(ERR, "Port %u cannot create DevX TIR.",
879 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
880 hrxq->action = mlx5_glue->dv_create_flow_action_dest_devx_tir
889 err = rte_errno; /* Save rte_errno before cleanup. */
891 claim_zero(mlx5_devx_cmd_destroy(hrxq->tir));
892 rte_errno = err; /* Restore rte_errno. */
897 * Destroy a DevX TIR object.
900 * Hash Rx queue to release its tir.
903 mlx5_devx_tir_destroy(struct mlx5_hrxq *hrxq)
905 claim_zero(mlx5_devx_cmd_destroy(hrxq->tir));
909 * Modify an Rx Hash queue configuration.
912 * Pointer to Ethernet device.
914 * Hash Rx queue to modify.
916 * RSS key for the Rx hash queue.
918 * Verbs protocol hash field to make the RSS on.
920 * Indirection table for TIR.
923 * 0 on success, a negative errno value otherwise and rte_errno is set.
926 mlx5_devx_hrxq_modify(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq,
927 const uint8_t *rss_key,
928 uint64_t hash_fields,
929 const struct mlx5_ind_table_obj *ind_tbl)
931 struct mlx5_devx_modify_tir_attr modify_tir = {0};
934 * untested for modification fields:
935 * - rx_hash_symmetric not set in hrxq_new(),
936 * - rx_hash_fn set hard-coded in hrxq_new(),
937 * - lro_xxx not set after rxq setup
939 if (ind_tbl != hrxq->ind_table)
940 modify_tir.modify_bitmask |=
941 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE;
942 if (hash_fields != hrxq->hash_fields ||
943 memcmp(hrxq->rss_key, rss_key, MLX5_RSS_HASH_KEY_LEN))
944 modify_tir.modify_bitmask |=
945 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH;
946 mlx5_devx_tir_attr_set(dev, rss_key, hash_fields, ind_tbl,
947 0, /* N/A - tunnel modification unsupported */
949 modify_tir.tirn = hrxq->tir->id;
950 if (mlx5_devx_cmd_modify_tir(hrxq->tir, &modify_tir)) {
951 DRV_LOG(ERR, "port %u cannot modify DevX TIR",
960 * Create a DevX drop action for Rx Hash queue.
963 * Pointer to Ethernet device.
966 * 0 on success, a negative errno value otherwise and rte_errno is set.
969 mlx5_devx_drop_action_create(struct rte_eth_dev *dev)
972 DRV_LOG(ERR, "DevX drop action is not supported yet.");
978 * Release a drop hash Rx queue.
981 * Pointer to Ethernet device.
984 mlx5_devx_drop_action_destroy(struct rte_eth_dev *dev)
987 DRV_LOG(ERR, "DevX drop action is not supported yet.");
992 * Create the Tx hairpin queue object.
995 * Pointer to Ethernet device.
997 * Queue index in DPDK Tx queue array.
1000 * 0 on success, a negative errno value otherwise and rte_errno is set.
1003 mlx5_txq_obj_hairpin_new(struct rte_eth_dev *dev, uint16_t idx)
1005 struct mlx5_priv *priv = dev->data->dev_private;
1006 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx];
1007 struct mlx5_txq_ctrl *txq_ctrl =
1008 container_of(txq_data, struct mlx5_txq_ctrl, txq);
1009 struct mlx5_devx_create_sq_attr attr = { 0 };
1010 struct mlx5_txq_obj *tmpl = txq_ctrl->obj;
1011 uint32_t max_wq_data;
1013 MLX5_ASSERT(txq_data);
1015 tmpl->txq_ctrl = txq_ctrl;
1017 attr.tis_lst_sz = 1;
1018 max_wq_data = priv->config.hca_attr.log_max_hairpin_wq_data_sz;
1019 /* Jumbo frames > 9KB should be supported, and more packets. */
1020 if (priv->config.log_hp_size != (uint32_t)MLX5_ARG_UNSET) {
1021 if (priv->config.log_hp_size > max_wq_data) {
1022 DRV_LOG(ERR, "Total data size %u power of 2 is "
1023 "too large for hairpin.",
1024 priv->config.log_hp_size);
1028 attr.wq_attr.log_hairpin_data_sz = priv->config.log_hp_size;
1030 attr.wq_attr.log_hairpin_data_sz =
1031 (max_wq_data < MLX5_HAIRPIN_JUMBO_LOG_SIZE) ?
1032 max_wq_data : MLX5_HAIRPIN_JUMBO_LOG_SIZE;
1034 /* Set the packets number to the maximum value for performance. */
1035 attr.wq_attr.log_hairpin_num_packets =
1036 attr.wq_attr.log_hairpin_data_sz -
1037 MLX5_HAIRPIN_QUEUE_STRIDE;
1038 attr.tis_num = priv->sh->tis->id;
1039 tmpl->sq = mlx5_devx_cmd_create_sq(priv->sh->ctx, &attr);
1042 "Port %u tx hairpin queue %u can't create SQ object.",
1043 dev->data->port_id, idx);
1050 #ifdef HAVE_MLX5DV_DEVX_UAR_OFFSET
1052 * Release DevX SQ resources.
1055 * DevX Tx queue object.
1058 mlx5_txq_release_devx_sq_resources(struct mlx5_txq_obj *txq_obj)
1060 if (txq_obj->sq_devx) {
1061 claim_zero(mlx5_devx_cmd_destroy(txq_obj->sq_devx));
1062 txq_obj->sq_devx = NULL;
1064 if (txq_obj->sq_umem) {
1065 claim_zero(mlx5_glue->devx_umem_dereg(txq_obj->sq_umem));
1066 txq_obj->sq_umem = NULL;
1068 if (txq_obj->sq_buf) {
1069 mlx5_free(txq_obj->sq_buf);
1070 txq_obj->sq_buf = NULL;
1072 if (txq_obj->sq_dbrec_page) {
1073 claim_zero(mlx5_release_dbr(&txq_obj->txq_ctrl->priv->dbrpgs,
1075 (txq_obj->sq_dbrec_page->umem),
1076 txq_obj->sq_dbrec_offset));
1077 txq_obj->sq_dbrec_page = NULL;
1082 * Release DevX Tx CQ resources.
1085 * DevX Tx queue object.
1088 mlx5_txq_release_devx_cq_resources(struct mlx5_txq_obj *txq_obj)
1090 if (txq_obj->cq_devx)
1091 claim_zero(mlx5_devx_cmd_destroy(txq_obj->cq_devx));
1092 if (txq_obj->cq_umem)
1093 claim_zero(mlx5_glue->devx_umem_dereg(txq_obj->cq_umem));
1094 if (txq_obj->cq_buf)
1095 mlx5_free(txq_obj->cq_buf);
1096 if (txq_obj->cq_dbrec_page)
1097 claim_zero(mlx5_release_dbr(&txq_obj->txq_ctrl->priv->dbrpgs,
1099 (txq_obj->cq_dbrec_page->umem),
1100 txq_obj->cq_dbrec_offset));
1104 * Destroy the Tx queue DevX object.
1107 * Txq object to destroy.
1110 mlx5_txq_release_devx_resources(struct mlx5_txq_obj *txq_obj)
1112 mlx5_txq_release_devx_cq_resources(txq_obj);
1113 mlx5_txq_release_devx_sq_resources(txq_obj);
1117 * Create a DevX CQ object and its resources for an Tx queue.
1120 * Pointer to Ethernet device.
1122 * Queue index in DPDK Tx queue array.
1125 * Number of CQEs in CQ, 0 otherwise and rte_errno is set.
1128 mlx5_txq_create_devx_cq_resources(struct rte_eth_dev *dev, uint16_t idx)
1130 struct mlx5_priv *priv = dev->data->dev_private;
1131 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx];
1132 struct mlx5_txq_ctrl *txq_ctrl =
1133 container_of(txq_data, struct mlx5_txq_ctrl, txq);
1134 struct mlx5_txq_obj *txq_obj = txq_ctrl->obj;
1135 struct mlx5_devx_cq_attr cq_attr = { 0 };
1136 struct mlx5_cqe *cqe;
1143 MLX5_ASSERT(txq_data);
1144 MLX5_ASSERT(txq_obj);
1145 page_size = rte_mem_page_size();
1146 if (page_size == (size_t)-1) {
1147 DRV_LOG(ERR, "Failed to get mem page size.");
1151 /* Allocate memory buffer for CQEs. */
1152 alignment = MLX5_CQE_BUF_ALIGNMENT;
1153 if (alignment == (size_t)-1) {
1154 DRV_LOG(ERR, "Failed to get CQE buf alignment.");
1158 /* Create the Completion Queue. */
1159 cqe_n = (1UL << txq_data->elts_n) / MLX5_TX_COMP_THRESH +
1160 1 + MLX5_TX_COMP_THRESH_INLINE_DIV;
1161 cqe_n = 1UL << log2above(cqe_n);
1162 if (cqe_n > UINT16_MAX) {
1164 "Port %u Tx queue %u requests to many CQEs %u.",
1165 dev->data->port_id, txq_data->idx, cqe_n);
1169 txq_obj->cq_buf = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO,
1170 cqe_n * sizeof(struct mlx5_cqe),
1172 priv->sh->numa_node);
1173 if (!txq_obj->cq_buf) {
1175 "Port %u Tx queue %u cannot allocate memory (CQ).",
1176 dev->data->port_id, txq_data->idx);
1180 /* Register allocated buffer in user space with DevX. */
1181 txq_obj->cq_umem = mlx5_glue->devx_umem_reg(priv->sh->ctx,
1182 (void *)txq_obj->cq_buf,
1183 cqe_n * sizeof(struct mlx5_cqe),
1184 IBV_ACCESS_LOCAL_WRITE);
1185 if (!txq_obj->cq_umem) {
1188 "Port %u Tx queue %u cannot register memory (CQ).",
1189 dev->data->port_id, txq_data->idx);
1192 /* Allocate doorbell record for completion queue. */
1193 txq_obj->cq_dbrec_offset = mlx5_get_dbr(priv->sh->ctx,
1195 &txq_obj->cq_dbrec_page);
1196 if (txq_obj->cq_dbrec_offset < 0) {
1198 DRV_LOG(ERR, "Failed to allocate CQ door-bell.");
1201 cq_attr.cqe_size = (sizeof(struct mlx5_cqe) == 128) ?
1202 MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B;
1203 cq_attr.uar_page_id = mlx5_os_get_devx_uar_page_id(priv->sh->tx_uar);
1204 cq_attr.eqn = priv->sh->eqn;
1205 cq_attr.q_umem_valid = 1;
1206 cq_attr.q_umem_offset = (uintptr_t)txq_obj->cq_buf % page_size;
1207 cq_attr.q_umem_id = mlx5_os_get_umem_id(txq_obj->cq_umem);
1208 cq_attr.db_umem_valid = 1;
1209 cq_attr.db_umem_offset = txq_obj->cq_dbrec_offset;
1210 cq_attr.db_umem_id = mlx5_os_get_umem_id(txq_obj->cq_dbrec_page->umem);
1211 cq_attr.log_cq_size = rte_log2_u32(cqe_n);
1212 cq_attr.log_page_size = rte_log2_u32(page_size);
1213 /* Create completion queue object with DevX. */
1214 txq_obj->cq_devx = mlx5_devx_cmd_create_cq(priv->sh->ctx, &cq_attr);
1215 if (!txq_obj->cq_devx) {
1217 DRV_LOG(ERR, "Port %u Tx queue %u CQ creation failure.",
1218 dev->data->port_id, idx);
1221 /* Initial fill CQ buffer with invalid CQE opcode. */
1222 cqe = (struct mlx5_cqe *)txq_obj->cq_buf;
1223 for (i = 0; i < cqe_n; i++) {
1224 cqe->op_own = (MLX5_CQE_INVALID << 4) | MLX5_CQE_OWNER_MASK;
1230 mlx5_txq_release_devx_cq_resources(txq_obj);
1236 * Create a SQ object and its resources using DevX.
1239 * Pointer to Ethernet device.
1241 * Queue index in DPDK Tx queue array.
1244 * Number of WQEs in SQ, 0 otherwise and rte_errno is set.
1247 mlx5_txq_create_devx_sq_resources(struct rte_eth_dev *dev, uint16_t idx)
1249 struct mlx5_priv *priv = dev->data->dev_private;
1250 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx];
1251 struct mlx5_txq_ctrl *txq_ctrl =
1252 container_of(txq_data, struct mlx5_txq_ctrl, txq);
1253 struct mlx5_txq_obj *txq_obj = txq_ctrl->obj;
1254 struct mlx5_devx_create_sq_attr sq_attr = { 0 };
1259 MLX5_ASSERT(txq_data);
1260 MLX5_ASSERT(txq_obj);
1261 page_size = rte_mem_page_size();
1262 if (page_size == (size_t)-1) {
1263 DRV_LOG(ERR, "Failed to get mem page size.");
1267 wqe_n = RTE_MIN(1UL << txq_data->elts_n,
1268 (uint32_t)priv->sh->device_attr.max_qp_wr);
1269 txq_obj->sq_buf = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO,
1270 wqe_n * sizeof(struct mlx5_wqe),
1271 page_size, priv->sh->numa_node);
1272 if (!txq_obj->sq_buf) {
1274 "Port %u Tx queue %u cannot allocate memory (SQ).",
1275 dev->data->port_id, txq_data->idx);
1279 /* Register allocated buffer in user space with DevX. */
1280 txq_obj->sq_umem = mlx5_glue->devx_umem_reg
1282 (void *)txq_obj->sq_buf,
1283 wqe_n * sizeof(struct mlx5_wqe),
1284 IBV_ACCESS_LOCAL_WRITE);
1285 if (!txq_obj->sq_umem) {
1288 "Port %u Tx queue %u cannot register memory (SQ).",
1289 dev->data->port_id, txq_data->idx);
1292 /* Allocate doorbell record for send queue. */
1293 txq_obj->sq_dbrec_offset = mlx5_get_dbr(priv->sh->ctx,
1295 &txq_obj->sq_dbrec_page);
1296 if (txq_obj->sq_dbrec_offset < 0) {
1298 DRV_LOG(ERR, "Failed to allocate SQ door-bell.");
1301 sq_attr.tis_lst_sz = 1;
1302 sq_attr.tis_num = priv->sh->tis->id;
1303 sq_attr.state = MLX5_SQC_STATE_RST;
1304 sq_attr.cqn = txq_obj->cq_devx->id;
1305 sq_attr.flush_in_error_en = 1;
1306 sq_attr.allow_multi_pkt_send_wqe = !!priv->config.mps;
1307 sq_attr.allow_swp = !!priv->config.swp;
1308 sq_attr.min_wqe_inline_mode = priv->config.hca_attr.vport_inline_mode;
1309 sq_attr.wq_attr.uar_page =
1310 mlx5_os_get_devx_uar_page_id(priv->sh->tx_uar);
1311 sq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC;
1312 sq_attr.wq_attr.pd = priv->sh->pdn;
1313 sq_attr.wq_attr.log_wq_stride = rte_log2_u32(MLX5_WQE_SIZE);
1314 sq_attr.wq_attr.log_wq_sz = log2above(wqe_n);
1315 sq_attr.wq_attr.dbr_umem_valid = 1;
1316 sq_attr.wq_attr.dbr_addr = txq_obj->sq_dbrec_offset;
1317 sq_attr.wq_attr.dbr_umem_id =
1318 mlx5_os_get_umem_id(txq_obj->sq_dbrec_page->umem);
1319 sq_attr.wq_attr.wq_umem_valid = 1;
1320 sq_attr.wq_attr.wq_umem_id = mlx5_os_get_umem_id(txq_obj->sq_umem);
1321 sq_attr.wq_attr.wq_umem_offset = (uintptr_t)txq_obj->sq_buf % page_size;
1322 /* Create Send Queue object with DevX. */
1323 txq_obj->sq_devx = mlx5_devx_cmd_create_sq(priv->sh->ctx, &sq_attr);
1324 if (!txq_obj->sq_devx) {
1326 DRV_LOG(ERR, "Port %u Tx queue %u SQ creation failure.",
1327 dev->data->port_id, idx);
1333 mlx5_txq_release_devx_sq_resources(txq_obj);
1340 * Create the Tx queue DevX object.
1343 * Pointer to Ethernet device.
1345 * Queue index in DPDK Tx queue array.
1348 * 0 on success, a negative errno value otherwise and rte_errno is set.
1351 mlx5_txq_devx_obj_new(struct rte_eth_dev *dev, uint16_t idx)
1353 struct mlx5_priv *priv = dev->data->dev_private;
1354 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx];
1355 struct mlx5_txq_ctrl *txq_ctrl =
1356 container_of(txq_data, struct mlx5_txq_ctrl, txq);
1358 if (txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN)
1359 return mlx5_txq_obj_hairpin_new(dev, idx);
1360 #ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET
1361 DRV_LOG(ERR, "Port %u Tx queue %u cannot create with DevX, no UAR.",
1362 dev->data->port_id, idx);
1366 struct mlx5_dev_ctx_shared *sh = priv->sh;
1367 struct mlx5_txq_obj *txq_obj = txq_ctrl->obj;
1373 MLX5_ASSERT(txq_data);
1374 MLX5_ASSERT(txq_obj);
1375 txq_obj->txq_ctrl = txq_ctrl;
1377 cqe_n = mlx5_txq_create_devx_cq_resources(dev, idx);
1382 txq_data->cqe_n = log2above(cqe_n);
1383 txq_data->cqe_s = 1 << txq_data->cqe_n;
1384 txq_data->cqe_m = txq_data->cqe_s - 1;
1385 txq_data->cqes = (volatile struct mlx5_cqe *)txq_obj->cq_buf;
1386 txq_data->cq_ci = 0;
1387 txq_data->cq_pi = 0;
1388 txq_data->cq_db = (volatile uint32_t *)(txq_obj->cq_dbrec_page->dbrs +
1389 txq_obj->cq_dbrec_offset);
1390 *txq_data->cq_db = 0;
1391 /* Create Send Queue object with DevX. */
1392 wqe_n = mlx5_txq_create_devx_sq_resources(dev, idx);
1397 /* Create the Work Queue. */
1398 txq_data->wqe_n = log2above(wqe_n);
1399 txq_data->wqe_s = 1 << txq_data->wqe_n;
1400 txq_data->wqe_m = txq_data->wqe_s - 1;
1401 txq_data->wqes = (struct mlx5_wqe *)txq_obj->sq_buf;
1402 txq_data->wqes_end = txq_data->wqes + txq_data->wqe_s;
1403 txq_data->wqe_ci = 0;
1404 txq_data->wqe_pi = 0;
1405 txq_data->wqe_comp = 0;
1406 txq_data->wqe_thres = txq_data->wqe_s / MLX5_TX_COMP_THRESH_INLINE_DIV;
1407 txq_data->qp_db = (volatile uint32_t *)
1408 (txq_obj->sq_dbrec_page->dbrs +
1409 txq_obj->sq_dbrec_offset +
1410 MLX5_SND_DBR * sizeof(uint32_t));
1411 *txq_data->qp_db = 0;
1412 txq_data->qp_num_8s = txq_obj->sq_devx->id << 8;
1413 /* Change Send Queue state to Ready-to-Send. */
1414 ret = mlx5_devx_modify_sq(txq_obj, MLX5_TXQ_MOD_RST2RDY, 0);
1418 "Port %u Tx queue %u SQ state to SQC_STATE_RDY failed.",
1419 dev->data->port_id, idx);
1422 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1424 * If using DevX need to query and store TIS transport domain value.
1425 * This is done once per port.
1426 * Will use this value on Rx, when creating matching TIR.
1429 priv->sh->tdn = priv->sh->td->id;
1431 MLX5_ASSERT(sh->tx_uar);
1432 reg_addr = mlx5_os_get_devx_uar_reg_addr(sh->tx_uar);
1433 MLX5_ASSERT(reg_addr);
1434 txq_ctrl->bf_reg = reg_addr;
1435 txq_ctrl->uar_mmap_offset =
1436 mlx5_os_get_devx_uar_mmap_offset(sh->tx_uar);
1437 txq_uar_init(txq_ctrl);
1438 dev->data->tx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STARTED;
1441 ret = rte_errno; /* Save rte_errno before cleanup. */
1442 mlx5_txq_release_devx_resources(txq_obj);
1443 rte_errno = ret; /* Restore rte_errno. */
1449 * Release an Tx DevX queue object.
1452 * DevX Tx queue object.
1455 mlx5_txq_devx_obj_release(struct mlx5_txq_obj *txq_obj)
1457 MLX5_ASSERT(txq_obj);
1458 if (txq_obj->txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) {
1460 claim_zero(mlx5_devx_cmd_destroy(txq_obj->tis));
1461 #ifdef HAVE_MLX5DV_DEVX_UAR_OFFSET
1463 mlx5_txq_release_devx_resources(txq_obj);
1468 struct mlx5_obj_ops devx_obj_ops = {
1469 .rxq_obj_modify_vlan_strip = mlx5_rxq_obj_modify_rq_vlan_strip,
1470 .rxq_obj_new = mlx5_rxq_devx_obj_new,
1471 .rxq_event_get = mlx5_rx_devx_get_event,
1472 .rxq_obj_modify = mlx5_devx_modify_rq,
1473 .rxq_obj_release = mlx5_rxq_devx_obj_release,
1474 .ind_table_new = mlx5_devx_ind_table_new,
1475 .ind_table_destroy = mlx5_devx_ind_table_destroy,
1476 .hrxq_new = mlx5_devx_hrxq_new,
1477 .hrxq_destroy = mlx5_devx_tir_destroy,
1478 .hrxq_modify = mlx5_devx_hrxq_modify,
1479 .drop_action_create = mlx5_devx_drop_action_create,
1480 .drop_action_destroy = mlx5_devx_drop_action_destroy,
1481 .txq_obj_new = mlx5_txq_devx_obj_new,
1482 .txq_obj_modify = mlx5_devx_modify_sq,
1483 .txq_obj_release = mlx5_txq_devx_obj_release,