1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2020 Mellanox Technologies, Ltd
11 #include <rte_malloc.h>
12 #include <rte_common.h>
13 #include <rte_eal_paging.h>
15 #include <mlx5_glue.h>
16 #include <mlx5_devx_cmds.h>
17 #include <mlx5_malloc.h>
20 #include "mlx5_common_os.h"
21 #include "mlx5_rxtx.h"
22 #include "mlx5_utils.h"
23 #include "mlx5_devx.h"
26 * Modify RQ vlan stripping offload
31 * @return 0 on success, non-0 otherwise
34 mlx5_rxq_obj_modify_rq_vlan_strip(struct mlx5_rxq_obj *rxq_obj, int on)
36 struct mlx5_devx_modify_rq_attr rq_attr;
38 memset(&rq_attr, 0, sizeof(rq_attr));
39 rq_attr.rq_state = MLX5_RQC_STATE_RDY;
40 rq_attr.state = MLX5_RQC_STATE_RDY;
41 rq_attr.vsd = (on ? 0 : 1);
42 rq_attr.modify_bitmask = MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD;
43 return mlx5_devx_cmd_modify_rq(rxq_obj->rq, &rq_attr);
47 * Release the resources allocated for an RQ DevX object.
50 * DevX Rx queue object.
53 rxq_release_devx_rq_resources(struct mlx5_rxq_ctrl *rxq_ctrl)
55 if (rxq_ctrl->rxq.wqes) {
56 mlx5_free((void *)(uintptr_t)rxq_ctrl->rxq.wqes);
57 rxq_ctrl->rxq.wqes = NULL;
59 if (rxq_ctrl->wq_umem) {
60 mlx5_glue->devx_umem_dereg(rxq_ctrl->wq_umem);
61 rxq_ctrl->wq_umem = NULL;
66 * Release the resources allocated for the Rx CQ DevX object.
69 * DevX Rx queue object.
72 rxq_release_devx_cq_resources(struct mlx5_rxq_ctrl *rxq_ctrl)
74 if (rxq_ctrl->rxq.cqes) {
75 rte_free((void *)(uintptr_t)rxq_ctrl->rxq.cqes);
76 rxq_ctrl->rxq.cqes = NULL;
78 if (rxq_ctrl->cq_umem) {
79 mlx5_glue->devx_umem_dereg(rxq_ctrl->cq_umem);
80 rxq_ctrl->cq_umem = NULL;
85 * Release an Rx hairpin related resources.
88 * Hairpin Rx queue object.
91 mlx5_rxq_obj_hairpin_release(struct mlx5_rxq_obj *rxq_obj)
93 struct mlx5_devx_modify_rq_attr rq_attr = { 0 };
96 rq_attr.state = MLX5_RQC_STATE_RST;
97 rq_attr.rq_state = MLX5_RQC_STATE_RDY;
98 mlx5_devx_cmd_modify_rq(rxq_obj->rq, &rq_attr);
99 claim_zero(mlx5_devx_cmd_destroy(rxq_obj->rq));
103 * Release an Rx DevX queue object.
106 * DevX Rx queue object.
109 mlx5_rxq_devx_obj_release(struct mlx5_rxq_obj *rxq_obj)
111 struct mlx5_priv *priv = rxq_obj->rxq_ctrl->priv;
113 MLX5_ASSERT(rxq_obj);
114 MLX5_ASSERT(rxq_obj->rq);
115 if (rxq_obj->type == MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN) {
116 mlx5_rxq_obj_hairpin_release(rxq_obj);
118 MLX5_ASSERT(rxq_obj->devx_cq);
119 claim_zero(mlx5_devx_cmd_destroy(rxq_obj->rq));
120 claim_zero(mlx5_devx_cmd_destroy(rxq_obj->devx_cq));
121 claim_zero(mlx5_release_dbr(&priv->dbrpgs,
122 rxq_obj->rxq_ctrl->rq_dbr_umem_id,
123 rxq_obj->rxq_ctrl->rq_dbr_offset));
124 claim_zero(mlx5_release_dbr(&priv->dbrpgs,
125 rxq_obj->rxq_ctrl->cq_dbr_umem_id,
126 rxq_obj->rxq_ctrl->cq_dbr_offset));
127 if (rxq_obj->devx_channel)
128 mlx5_glue->devx_destroy_event_channel
129 (rxq_obj->devx_channel);
130 rxq_release_devx_rq_resources(rxq_obj->rxq_ctrl);
131 rxq_release_devx_cq_resources(rxq_obj->rxq_ctrl);
136 * Get event for an Rx DevX queue object.
139 * DevX Rx queue object.
142 * 0 on success, a negative errno value otherwise and rte_errno is set.
145 mlx5_rx_devx_get_event(struct mlx5_rxq_obj *rxq_obj)
147 #ifdef HAVE_IBV_DEVX_EVENT
149 struct mlx5dv_devx_async_event_hdr event_resp;
150 uint8_t buf[sizeof(struct mlx5dv_devx_async_event_hdr) + 128];
152 int ret = mlx5_glue->devx_get_event(rxq_obj->devx_channel,
160 if (out.event_resp.cookie != (uint64_t)(uintptr_t)rxq_obj->devx_cq) {
169 #endif /* HAVE_IBV_DEVX_EVENT */
173 * Fill common fields of create RQ attributes structure.
176 * Pointer to Rx queue data.
178 * CQ number to use with this RQ.
180 * RQ attributes structure to fill..
183 mlx5_devx_create_rq_attr_fill(struct mlx5_rxq_data *rxq_data, uint32_t cqn,
184 struct mlx5_devx_create_rq_attr *rq_attr)
186 rq_attr->state = MLX5_RQC_STATE_RST;
187 rq_attr->vsd = (rxq_data->vlan_strip) ? 0 : 1;
189 rq_attr->scatter_fcs = (rxq_data->crc_present) ? 1 : 0;
193 * Fill common fields of DevX WQ attributes structure.
196 * Pointer to device private data.
198 * Pointer to Rx queue control structure.
200 * WQ attributes structure to fill..
203 mlx5_devx_wq_attr_fill(struct mlx5_priv *priv, struct mlx5_rxq_ctrl *rxq_ctrl,
204 struct mlx5_devx_wq_attr *wq_attr)
206 wq_attr->end_padding_mode = priv->config.cqe_pad ?
207 MLX5_WQ_END_PAD_MODE_ALIGN :
208 MLX5_WQ_END_PAD_MODE_NONE;
209 wq_attr->pd = priv->sh->pdn;
210 wq_attr->dbr_addr = rxq_ctrl->rq_dbr_offset;
211 wq_attr->dbr_umem_id = rxq_ctrl->rq_dbr_umem_id;
212 wq_attr->dbr_umem_valid = 1;
213 wq_attr->wq_umem_id = mlx5_os_get_umem_id(rxq_ctrl->wq_umem);
214 wq_attr->wq_umem_valid = 1;
218 * Create a RQ object using DevX.
221 * Pointer to Ethernet device.
223 * Queue index in DPDK Rx queue array.
225 * CQ number to use with this RQ.
228 * The DevX object initialized, NULL otherwise and rte_errno is set.
230 static struct mlx5_devx_obj *
231 mlx5_devx_rq_new(struct rte_eth_dev *dev, uint16_t idx, uint32_t cqn)
233 struct mlx5_priv *priv = dev->data->dev_private;
234 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
235 struct mlx5_rxq_ctrl *rxq_ctrl =
236 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
237 struct mlx5_devx_create_rq_attr rq_attr = { 0 };
238 uint32_t wqe_n = 1 << (rxq_data->elts_n - rxq_data->sges_n);
239 uint32_t wq_size = 0;
240 uint32_t wqe_size = 0;
241 uint32_t log_wqe_size = 0;
243 struct mlx5_devx_obj *rq;
245 /* Fill RQ attributes. */
246 rq_attr.mem_rq_type = MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE;
247 rq_attr.flush_in_error_en = 1;
248 mlx5_devx_create_rq_attr_fill(rxq_data, cqn, &rq_attr);
249 /* Fill WQ attributes for this RQ. */
250 if (mlx5_rxq_mprq_enabled(rxq_data)) {
251 rq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ;
253 * Number of strides in each WQE:
254 * 512*2^single_wqe_log_num_of_strides.
256 rq_attr.wq_attr.single_wqe_log_num_of_strides =
257 rxq_data->strd_num_n -
258 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
259 /* Stride size = (2^single_stride_log_num_of_bytes)*64B. */
260 rq_attr.wq_attr.single_stride_log_num_of_bytes =
261 rxq_data->strd_sz_n -
262 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
263 wqe_size = sizeof(struct mlx5_wqe_mprq);
265 rq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC;
266 wqe_size = sizeof(struct mlx5_wqe_data_seg);
268 log_wqe_size = log2above(wqe_size) + rxq_data->sges_n;
269 rq_attr.wq_attr.log_wq_stride = log_wqe_size;
270 rq_attr.wq_attr.log_wq_sz = rxq_data->elts_n - rxq_data->sges_n;
271 /* Calculate and allocate WQ memory space. */
272 wqe_size = 1 << log_wqe_size; /* round up power of two.*/
273 wq_size = wqe_n * wqe_size;
274 size_t alignment = MLX5_WQE_BUF_ALIGNMENT;
275 if (alignment == (size_t)-1) {
276 DRV_LOG(ERR, "Failed to get mem page size");
280 buf = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, wq_size,
281 alignment, rxq_ctrl->socket);
284 rxq_data->wqes = buf;
285 rxq_ctrl->wq_umem = mlx5_glue->devx_umem_reg(priv->sh->ctx,
287 if (!rxq_ctrl->wq_umem) {
291 mlx5_devx_wq_attr_fill(priv, rxq_ctrl, &rq_attr.wq_attr);
292 rq = mlx5_devx_cmd_create_rq(priv->sh->ctx, &rq_attr, rxq_ctrl->socket);
294 rxq_release_devx_rq_resources(rxq_ctrl);
299 * Create a DevX CQ object for an Rx queue.
302 * Pointer to Ethernet device.
304 * Number of CQEs in CQ.
306 * Queue index in DPDK Rx queue array.
308 * Pointer to Rx queue object data.
311 * The DevX object initialized, NULL otherwise and rte_errno is set.
313 static struct mlx5_devx_obj *
314 mlx5_devx_cq_new(struct rte_eth_dev *dev, unsigned int cqe_n, uint16_t idx,
315 struct mlx5_rxq_obj *rxq_obj)
317 struct mlx5_devx_obj *cq_obj = 0;
318 struct mlx5_devx_cq_attr cq_attr = { 0 };
319 struct mlx5_priv *priv = dev->data->dev_private;
320 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
321 struct mlx5_rxq_ctrl *rxq_ctrl =
322 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
323 size_t page_size = rte_mem_page_size();
324 uint32_t lcore = (uint32_t)rte_lcore_to_cpu_id(-1);
327 uint16_t event_nums[1] = {0};
332 if (page_size == (size_t)-1) {
333 DRV_LOG(ERR, "Failed to get page_size.");
336 if (priv->config.cqe_comp && !rxq_data->hw_timestamp &&
338 cq_attr.cqe_comp_en = MLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE;
339 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
340 cq_attr.mini_cqe_res_format =
341 mlx5_rxq_mprq_enabled(rxq_data) ?
342 MLX5DV_CQE_RES_FORMAT_CSUM_STRIDX :
343 MLX5DV_CQE_RES_FORMAT_HASH;
345 cq_attr.mini_cqe_res_format = MLX5DV_CQE_RES_FORMAT_HASH;
348 * For vectorized Rx, it must not be doubled in order to
349 * make cq_ci and rq_ci aligned.
351 if (mlx5_rxq_check_vec_support(rxq_data) < 0)
353 } else if (priv->config.cqe_comp && rxq_data->hw_timestamp) {
355 "Port %u Rx CQE compression is disabled for HW"
358 } else if (priv->config.cqe_comp && rxq_data->lro) {
360 "Port %u Rx CQE compression is disabled for LRO.",
363 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
364 if (priv->config.cqe_pad)
365 cq_attr.cqe_size = MLX5DV_CQ_INIT_ATTR_FLAGS_CQE_PAD;
367 log_cqe_n = log2above(cqe_n);
368 cq_size = sizeof(struct mlx5_cqe) * (1 << log_cqe_n);
369 /* Query the EQN for this core. */
370 if (mlx5_glue->devx_query_eqn(priv->sh->ctx, lcore, &eqn)) {
371 DRV_LOG(ERR, "Failed to query EQN for CQ.");
375 buf = rte_calloc_socket(__func__, 1, cq_size, page_size,
378 DRV_LOG(ERR, "Failed to allocate memory for CQ.");
381 rxq_data->cqes = (volatile struct mlx5_cqe (*)[])(uintptr_t)buf;
382 rxq_ctrl->cq_umem = mlx5_glue->devx_umem_reg(priv->sh->ctx, buf,
384 IBV_ACCESS_LOCAL_WRITE);
385 if (!rxq_ctrl->cq_umem) {
386 DRV_LOG(ERR, "Failed to register umem for CQ.");
389 cq_attr.uar_page_id =
390 mlx5_os_get_devx_uar_page_id(priv->sh->devx_rx_uar);
391 cq_attr.q_umem_id = mlx5_os_get_umem_id(rxq_ctrl->cq_umem);
392 cq_attr.q_umem_valid = 1;
393 cq_attr.log_cq_size = log_cqe_n;
394 cq_attr.log_page_size = rte_log2_u32(page_size);
395 cq_attr.db_umem_offset = rxq_ctrl->cq_dbr_offset;
396 cq_attr.db_umem_id = rxq_ctrl->cq_dbr_umem_id;
397 cq_attr.db_umem_valid = 1;
398 cq_obj = mlx5_devx_cmd_create_cq(priv->sh->ctx, &cq_attr);
401 rxq_data->cqe_n = log_cqe_n;
402 rxq_data->cqn = cq_obj->id;
403 if (rxq_obj->devx_channel) {
404 ret = mlx5_glue->devx_subscribe_devx_event
405 (rxq_obj->devx_channel,
409 (uint64_t)(uintptr_t)cq_obj);
411 DRV_LOG(ERR, "Fail to subscribe CQ to event channel.");
416 /* Initialise CQ to 1's to mark HW ownership for all CQEs. */
417 memset((void *)(uintptr_t)rxq_data->cqes, 0xFF, cq_size);
421 mlx5_devx_cmd_destroy(cq_obj);
422 rxq_release_devx_cq_resources(rxq_ctrl);
427 * Create the Rx hairpin queue object.
430 * Pointer to Ethernet device.
432 * Queue index in DPDK Rx queue array.
435 * 0 on success, a negative errno value otherwise and rte_errno is set.
438 mlx5_rxq_obj_hairpin_new(struct rte_eth_dev *dev, uint16_t idx)
440 struct mlx5_priv *priv = dev->data->dev_private;
441 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
442 struct mlx5_rxq_ctrl *rxq_ctrl =
443 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
444 struct mlx5_devx_create_rq_attr attr = { 0 };
445 struct mlx5_rxq_obj *tmpl = rxq_ctrl->obj;
446 uint32_t max_wq_data;
448 MLX5_ASSERT(rxq_data);
450 tmpl->type = MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN;
451 tmpl->rxq_ctrl = rxq_ctrl;
453 max_wq_data = priv->config.hca_attr.log_max_hairpin_wq_data_sz;
454 /* Jumbo frames > 9KB should be supported, and more packets. */
455 if (priv->config.log_hp_size != (uint32_t)MLX5_ARG_UNSET) {
456 if (priv->config.log_hp_size > max_wq_data) {
457 DRV_LOG(ERR, "Total data size %u power of 2 is "
458 "too large for hairpin.",
459 priv->config.log_hp_size);
463 attr.wq_attr.log_hairpin_data_sz = priv->config.log_hp_size;
465 attr.wq_attr.log_hairpin_data_sz =
466 (max_wq_data < MLX5_HAIRPIN_JUMBO_LOG_SIZE) ?
467 max_wq_data : MLX5_HAIRPIN_JUMBO_LOG_SIZE;
469 /* Set the packets number to the maximum value for performance. */
470 attr.wq_attr.log_hairpin_num_packets =
471 attr.wq_attr.log_hairpin_data_sz -
472 MLX5_HAIRPIN_QUEUE_STRIDE;
473 tmpl->rq = mlx5_devx_cmd_create_rq(priv->sh->ctx, &attr,
477 "Port %u Rx hairpin queue %u can't create rq object.",
478 dev->data->port_id, idx);
482 dev->data->rx_queue_state[idx] = RTE_ETH_QUEUE_STATE_HAIRPIN;
487 * Create the Rx queue DevX object.
490 * Pointer to Ethernet device.
492 * Queue index in DPDK Rx queue array.
495 * 0 on success, a negative errno value otherwise and rte_errno is set.
498 mlx5_rxq_devx_obj_new(struct rte_eth_dev *dev, uint16_t idx)
500 struct mlx5_priv *priv = dev->data->dev_private;
501 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
502 struct mlx5_rxq_ctrl *rxq_ctrl =
503 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
505 unsigned int wqe_n = 1 << rxq_data->elts_n;
506 struct mlx5_rxq_obj *tmpl = rxq_ctrl->obj;
507 struct mlx5_devx_modify_rq_attr rq_attr = { 0 };
508 struct mlx5_devx_dbr_page *cq_dbr_page = NULL;
509 struct mlx5_devx_dbr_page *rq_dbr_page = NULL;
513 MLX5_ASSERT(rxq_data);
515 if (rxq_ctrl->type == MLX5_RXQ_TYPE_HAIRPIN)
516 return mlx5_rxq_obj_hairpin_new(dev, idx);
517 tmpl->type = MLX5_RXQ_OBJ_TYPE_DEVX_RQ;
518 tmpl->rxq_ctrl = rxq_ctrl;
521 MLX5DV_DEVX_CREATE_EVENT_CHANNEL_FLAGS_OMIT_EV_DATA;
523 tmpl->devx_channel = mlx5_glue->devx_create_event_channel
526 if (!tmpl->devx_channel) {
528 DRV_LOG(ERR, "Failed to create event channel %d.",
532 tmpl->fd = mlx5_os_get_devx_channel_fd(tmpl->devx_channel);
534 if (mlx5_rxq_mprq_enabled(rxq_data))
535 cqe_n = wqe_n * (1 << rxq_data->strd_num_n) - 1;
538 /* Allocate CQ door-bell. */
539 dbr_offset = mlx5_get_dbr(priv->sh->ctx, &priv->dbrpgs, &cq_dbr_page);
540 if (dbr_offset < 0) {
541 DRV_LOG(ERR, "Failed to allocate CQ door-bell.");
544 rxq_ctrl->cq_dbr_offset = dbr_offset;
545 rxq_ctrl->cq_dbr_umem_id = mlx5_os_get_umem_id(cq_dbr_page->umem);
546 rxq_data->cq_db = (uint32_t *)((uintptr_t)cq_dbr_page->dbrs +
547 (uintptr_t)rxq_ctrl->cq_dbr_offset);
549 mlx5_os_get_devx_uar_base_addr(priv->sh->devx_rx_uar);
550 /* Create CQ using DevX API. */
551 tmpl->devx_cq = mlx5_devx_cq_new(dev, cqe_n, idx, tmpl);
552 if (!tmpl->devx_cq) {
553 DRV_LOG(ERR, "Failed to create CQ.");
556 /* Allocate RQ door-bell. */
557 dbr_offset = mlx5_get_dbr(priv->sh->ctx, &priv->dbrpgs, &rq_dbr_page);
558 if (dbr_offset < 0) {
559 DRV_LOG(ERR, "Failed to allocate RQ door-bell.");
562 rxq_ctrl->rq_dbr_offset = dbr_offset;
563 rxq_ctrl->rq_dbr_umem_id = mlx5_os_get_umem_id(rq_dbr_page->umem);
564 rxq_data->rq_db = (uint32_t *)((uintptr_t)rq_dbr_page->dbrs +
565 (uintptr_t)rxq_ctrl->rq_dbr_offset);
566 /* Create RQ using DevX API. */
567 tmpl->rq = mlx5_devx_rq_new(dev, idx, tmpl->devx_cq->id);
569 DRV_LOG(ERR, "Port %u Rx queue %u RQ creation failure.",
570 dev->data->port_id, idx);
574 /* Change queue state to ready. */
575 rq_attr.rq_state = MLX5_RQC_STATE_RST;
576 rq_attr.state = MLX5_RQC_STATE_RDY;
577 ret = mlx5_devx_cmd_modify_rq(tmpl->rq, &rq_attr);
580 rxq_data->cq_arm_sn = 0;
581 mlx5_rxq_initialize(rxq_data);
583 dev->data->rx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STARTED;
584 rxq_ctrl->wqn = tmpl->rq->id;
587 ret = rte_errno; /* Save rte_errno before cleanup. */
589 claim_zero(mlx5_devx_cmd_destroy(tmpl->rq));
591 claim_zero(mlx5_devx_cmd_destroy(tmpl->devx_cq));
592 if (tmpl->devx_channel)
593 mlx5_glue->devx_destroy_event_channel(tmpl->devx_channel);
595 claim_zero(mlx5_release_dbr(&priv->dbrpgs,
596 rxq_ctrl->rq_dbr_umem_id,
597 rxq_ctrl->rq_dbr_offset));
599 claim_zero(mlx5_release_dbr(&priv->dbrpgs,
600 rxq_ctrl->cq_dbr_umem_id,
601 rxq_ctrl->cq_dbr_offset));
602 rxq_release_devx_rq_resources(rxq_ctrl);
603 rxq_release_devx_cq_resources(rxq_ctrl);
604 rte_errno = ret; /* Restore rte_errno. */
608 struct mlx5_obj_ops devx_obj_ops = {
609 .rxq_obj_modify_vlan_strip = mlx5_rxq_obj_modify_rq_vlan_strip,
610 .rxq_obj_new = mlx5_rxq_devx_obj_new,
611 .rxq_event_get = mlx5_rx_devx_get_event,
612 .rxq_obj_release = mlx5_rxq_devx_obj_release,