1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2020 Mellanox Technologies, Ltd
10 #include <sys/queue.h>
12 #include <rte_malloc.h>
13 #include <rte_common.h>
14 #include <rte_eal_paging.h>
16 #include <mlx5_glue.h>
17 #include <mlx5_devx_cmds.h>
18 #include <mlx5_common_devx.h>
19 #include <mlx5_malloc.h>
22 #include "mlx5_common_os.h"
25 #include "mlx5_utils.h"
26 #include "mlx5_devx.h"
27 #include "mlx5_flow.h"
28 #include "mlx5_flow_os.h"
31 * Modify RQ vlan stripping offload
37 * 0 on success, non-0 otherwise
40 mlx5_rxq_obj_modify_rq_vlan_strip(struct mlx5_rxq_obj *rxq_obj, int on)
42 struct mlx5_devx_modify_rq_attr rq_attr;
44 memset(&rq_attr, 0, sizeof(rq_attr));
45 rq_attr.rq_state = MLX5_RQC_STATE_RDY;
46 rq_attr.state = MLX5_RQC_STATE_RDY;
47 rq_attr.vsd = (on ? 0 : 1);
48 rq_attr.modify_bitmask = MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD;
49 return mlx5_devx_cmd_modify_rq(rxq_obj->rq_obj.rq, &rq_attr);
53 * Modify RQ using DevX API.
56 * DevX Rx queue object.
58 * Type of change queue state.
61 * 0 on success, a negative errno value otherwise and rte_errno is set.
64 mlx5_devx_modify_rq(struct mlx5_rxq_obj *rxq_obj, uint8_t type)
66 struct mlx5_devx_modify_rq_attr rq_attr;
68 memset(&rq_attr, 0, sizeof(rq_attr));
70 case MLX5_RXQ_MOD_ERR2RST:
71 rq_attr.rq_state = MLX5_RQC_STATE_ERR;
72 rq_attr.state = MLX5_RQC_STATE_RST;
74 case MLX5_RXQ_MOD_RST2RDY:
75 rq_attr.rq_state = MLX5_RQC_STATE_RST;
76 rq_attr.state = MLX5_RQC_STATE_RDY;
78 case MLX5_RXQ_MOD_RDY2ERR:
79 rq_attr.rq_state = MLX5_RQC_STATE_RDY;
80 rq_attr.state = MLX5_RQC_STATE_ERR;
82 case MLX5_RXQ_MOD_RDY2RST:
83 rq_attr.rq_state = MLX5_RQC_STATE_RDY;
84 rq_attr.state = MLX5_RQC_STATE_RST;
89 return mlx5_devx_cmd_modify_rq(rxq_obj->rq_obj.rq, &rq_attr);
93 * Modify SQ using DevX API.
96 * DevX Tx queue object.
98 * Type of change queue state.
103 * 0 on success, a negative errno value otherwise and rte_errno is set.
106 mlx5_txq_devx_modify(struct mlx5_txq_obj *obj, enum mlx5_txq_modify_type type,
109 struct mlx5_devx_modify_sq_attr msq_attr = { 0 };
112 if (type != MLX5_TXQ_MOD_RST2RDY) {
113 /* Change queue state to reset. */
114 if (type == MLX5_TXQ_MOD_ERR2RDY)
115 msq_attr.sq_state = MLX5_SQC_STATE_ERR;
117 msq_attr.sq_state = MLX5_SQC_STATE_RDY;
118 msq_attr.state = MLX5_SQC_STATE_RST;
119 ret = mlx5_devx_cmd_modify_sq(obj->sq_obj.sq, &msq_attr);
121 DRV_LOG(ERR, "Cannot change the Tx SQ state to RESET"
122 " %s", strerror(errno));
127 if (type != MLX5_TXQ_MOD_RDY2RST) {
128 /* Change queue state to ready. */
129 msq_attr.sq_state = MLX5_SQC_STATE_RST;
130 msq_attr.state = MLX5_SQC_STATE_RDY;
131 ret = mlx5_devx_cmd_modify_sq(obj->sq_obj.sq, &msq_attr);
133 DRV_LOG(ERR, "Cannot change the Tx SQ state to READY"
134 " %s", strerror(errno));
140 * The dev_port variable is relevant only in Verbs API, and there is a
141 * pointer that points to this function and a parallel function in verbs
142 * intermittently, so they should have the same parameters.
149 * Destroy the Rx queue DevX object.
152 * Rxq object to destroy.
155 mlx5_rxq_release_devx_resources(struct mlx5_rxq_obj *rxq_obj)
157 mlx5_devx_rq_destroy(&rxq_obj->rq_obj);
158 memset(&rxq_obj->rq_obj, 0, sizeof(rxq_obj->rq_obj));
159 mlx5_devx_cq_destroy(&rxq_obj->cq_obj);
160 memset(&rxq_obj->cq_obj, 0, sizeof(rxq_obj->cq_obj));
164 * Release an Rx DevX queue object.
167 * DevX Rx queue object.
170 mlx5_rxq_devx_obj_release(struct mlx5_rxq_obj *rxq_obj)
172 MLX5_ASSERT(rxq_obj);
173 if (rxq_obj->rxq_ctrl->type == MLX5_RXQ_TYPE_HAIRPIN) {
174 MLX5_ASSERT(rxq_obj->rq);
175 mlx5_devx_modify_rq(rxq_obj, MLX5_RXQ_MOD_RDY2RST);
176 claim_zero(mlx5_devx_cmd_destroy(rxq_obj->rq));
178 MLX5_ASSERT(rxq_obj->cq_obj.cq);
179 MLX5_ASSERT(rxq_obj->rq_obj.rq);
180 mlx5_rxq_release_devx_resources(rxq_obj);
181 if (rxq_obj->devx_channel)
182 mlx5_os_devx_destroy_event_channel
183 (rxq_obj->devx_channel);
188 * Get event for an Rx DevX queue object.
191 * DevX Rx queue object.
194 * 0 on success, a negative errno value otherwise and rte_errno is set.
197 mlx5_rx_devx_get_event(struct mlx5_rxq_obj *rxq_obj)
199 #ifdef HAVE_IBV_DEVX_EVENT
201 struct mlx5dv_devx_async_event_hdr event_resp;
202 uint8_t buf[sizeof(struct mlx5dv_devx_async_event_hdr) + 128];
204 int ret = mlx5_glue->devx_get_event(rxq_obj->devx_channel,
212 if (out.event_resp.cookie != (uint64_t)(uintptr_t)rxq_obj->cq_obj.cq) {
221 #endif /* HAVE_IBV_DEVX_EVENT */
225 * Create a RQ object using DevX.
228 * Pointer to Ethernet device.
230 * Queue index in DPDK Rx queue array.
233 * 0 on success, a negative errno value otherwise and rte_errno is set.
236 mlx5_rxq_create_devx_rq_resources(struct rte_eth_dev *dev, uint16_t idx)
238 struct mlx5_priv *priv = dev->data->dev_private;
239 struct mlx5_common_device *cdev = priv->sh->cdev;
240 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
241 struct mlx5_rxq_ctrl *rxq_ctrl =
242 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
243 struct mlx5_devx_create_rq_attr rq_attr = { 0 };
244 uint16_t log_desc_n = rxq_data->elts_n - rxq_data->sges_n;
245 uint32_t wqe_size, log_wqe_size;
247 /* Fill RQ attributes. */
248 rq_attr.mem_rq_type = MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE;
249 rq_attr.flush_in_error_en = 1;
250 rq_attr.vsd = (rxq_data->vlan_strip) ? 0 : 1;
251 rq_attr.cqn = rxq_ctrl->obj->cq_obj.cq->id;
252 rq_attr.scatter_fcs = (rxq_data->crc_present) ? 1 : 0;
254 mlx5_ts_format_conv(cdev->config.hca_attr.rq_ts_format);
255 /* Fill WQ attributes for this RQ. */
256 if (mlx5_rxq_mprq_enabled(rxq_data)) {
257 rq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ;
259 * Number of strides in each WQE:
260 * 512*2^single_wqe_log_num_of_strides.
262 rq_attr.wq_attr.single_wqe_log_num_of_strides =
263 rxq_data->strd_num_n -
264 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
265 /* Stride size = (2^single_stride_log_num_of_bytes)*64B. */
266 rq_attr.wq_attr.single_stride_log_num_of_bytes =
267 rxq_data->strd_sz_n -
268 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
269 wqe_size = sizeof(struct mlx5_wqe_mprq);
271 rq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC;
272 wqe_size = sizeof(struct mlx5_wqe_data_seg);
274 log_wqe_size = log2above(wqe_size) + rxq_data->sges_n;
275 wqe_size = 1 << log_wqe_size; /* round up power of two.*/
276 rq_attr.wq_attr.log_wq_stride = log_wqe_size;
277 rq_attr.wq_attr.log_wq_sz = log_desc_n;
278 rq_attr.wq_attr.end_padding_mode = priv->config.hw_padding ?
279 MLX5_WQ_END_PAD_MODE_ALIGN :
280 MLX5_WQ_END_PAD_MODE_NONE;
281 rq_attr.wq_attr.pd = cdev->pdn;
282 rq_attr.counter_set_id = priv->counter_set_id;
283 /* Create RQ using DevX API. */
284 return mlx5_devx_rq_create(cdev->ctx, &rxq_ctrl->obj->rq_obj, wqe_size,
285 log_desc_n, &rq_attr, rxq_ctrl->socket);
289 * Create a DevX CQ object for an Rx queue.
292 * Pointer to Ethernet device.
294 * Queue index in DPDK Rx queue array.
297 * 0 on success, a negative errno value otherwise and rte_errno is set.
300 mlx5_rxq_create_devx_cq_resources(struct rte_eth_dev *dev, uint16_t idx)
302 struct mlx5_devx_cq *cq_obj = 0;
303 struct mlx5_devx_cq_attr cq_attr = { 0 };
304 struct mlx5_priv *priv = dev->data->dev_private;
305 struct mlx5_dev_ctx_shared *sh = priv->sh;
306 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
307 struct mlx5_rxq_ctrl *rxq_ctrl =
308 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
309 unsigned int cqe_n = mlx5_rxq_cqe_num(rxq_data);
311 uint16_t event_nums[1] = { 0 };
314 if (priv->config.cqe_comp && !rxq_data->hw_timestamp &&
316 cq_attr.cqe_comp_en = 1u;
317 rxq_data->mcqe_format = priv->config.cqe_comp_fmt;
318 rxq_data->byte_mask = UINT32_MAX;
319 switch (priv->config.cqe_comp_fmt) {
320 case MLX5_CQE_RESP_FORMAT_HASH:
322 case MLX5_CQE_RESP_FORMAT_CSUM:
324 * Select CSUM miniCQE format only for non-vectorized
325 * MPRQ Rx burst, use HASH miniCQE format for others.
327 if (mlx5_rxq_check_vec_support(rxq_data) < 0 &&
328 mlx5_rxq_mprq_enabled(rxq_data))
329 cq_attr.mini_cqe_res_format =
330 MLX5_CQE_RESP_FORMAT_CSUM_STRIDX;
332 cq_attr.mini_cqe_res_format =
333 MLX5_CQE_RESP_FORMAT_HASH;
334 rxq_data->mcqe_format = cq_attr.mini_cqe_res_format;
336 case MLX5_CQE_RESP_FORMAT_FTAG_STRIDX:
337 rxq_data->byte_mask = MLX5_LEN_WITH_MARK_MASK;
339 case MLX5_CQE_RESP_FORMAT_CSUM_STRIDX:
340 cq_attr.mini_cqe_res_format = priv->config.cqe_comp_fmt;
342 case MLX5_CQE_RESP_FORMAT_L34H_STRIDX:
343 cq_attr.mini_cqe_res_format = 0;
344 cq_attr.mini_cqe_res_format_ext = 1;
348 "Port %u Rx CQE compression is enabled, format %d.",
349 dev->data->port_id, priv->config.cqe_comp_fmt);
351 * For vectorized Rx, it must not be doubled in order to
352 * make cq_ci and rq_ci aligned.
354 if (mlx5_rxq_check_vec_support(rxq_data) < 0)
356 } else if (priv->config.cqe_comp && rxq_data->hw_timestamp) {
358 "Port %u Rx CQE compression is disabled for HW"
361 } else if (priv->config.cqe_comp && rxq_data->lro) {
363 "Port %u Rx CQE compression is disabled for LRO.",
366 cq_attr.uar_page_id = mlx5_os_get_devx_uar_page_id(sh->devx_rx_uar);
367 log_cqe_n = log2above(cqe_n);
368 /* Create CQ using DevX API. */
369 ret = mlx5_devx_cq_create(sh->cdev->ctx, &rxq_ctrl->obj->cq_obj,
370 log_cqe_n, &cq_attr, sh->numa_node);
373 cq_obj = &rxq_ctrl->obj->cq_obj;
374 rxq_data->cqes = (volatile struct mlx5_cqe (*)[])
375 (uintptr_t)cq_obj->cqes;
376 rxq_data->cq_db = cq_obj->db_rec;
377 rxq_data->cq_uar = mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar);
378 rxq_data->cqe_n = log_cqe_n;
379 rxq_data->cqn = cq_obj->cq->id;
380 if (rxq_ctrl->obj->devx_channel) {
381 ret = mlx5_os_devx_subscribe_devx_event
382 (rxq_ctrl->obj->devx_channel,
386 (uint64_t)(uintptr_t)cq_obj->cq);
388 DRV_LOG(ERR, "Fail to subscribe CQ to event channel.");
390 mlx5_devx_cq_destroy(cq_obj);
391 memset(cq_obj, 0, sizeof(*cq_obj));
400 * Create the Rx hairpin queue object.
403 * Pointer to Ethernet device.
405 * Queue index in DPDK Rx queue array.
408 * 0 on success, a negative errno value otherwise and rte_errno is set.
411 mlx5_rxq_obj_hairpin_new(struct rte_eth_dev *dev, uint16_t idx)
413 struct mlx5_priv *priv = dev->data->dev_private;
414 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
415 struct mlx5_rxq_ctrl *rxq_ctrl =
416 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
417 struct mlx5_devx_create_rq_attr attr = { 0 };
418 struct mlx5_rxq_obj *tmpl = rxq_ctrl->obj;
419 uint32_t max_wq_data;
421 MLX5_ASSERT(rxq_data);
423 tmpl->rxq_ctrl = rxq_ctrl;
425 max_wq_data = priv->config.hca_attr.log_max_hairpin_wq_data_sz;
426 /* Jumbo frames > 9KB should be supported, and more packets. */
427 if (priv->config.log_hp_size != (uint32_t)MLX5_ARG_UNSET) {
428 if (priv->config.log_hp_size > max_wq_data) {
429 DRV_LOG(ERR, "Total data size %u power of 2 is "
430 "too large for hairpin.",
431 priv->config.log_hp_size);
435 attr.wq_attr.log_hairpin_data_sz = priv->config.log_hp_size;
437 attr.wq_attr.log_hairpin_data_sz =
438 (max_wq_data < MLX5_HAIRPIN_JUMBO_LOG_SIZE) ?
439 max_wq_data : MLX5_HAIRPIN_JUMBO_LOG_SIZE;
441 /* Set the packets number to the maximum value for performance. */
442 attr.wq_attr.log_hairpin_num_packets =
443 attr.wq_attr.log_hairpin_data_sz -
444 MLX5_HAIRPIN_QUEUE_STRIDE;
445 attr.counter_set_id = priv->counter_set_id;
446 tmpl->rq = mlx5_devx_cmd_create_rq(priv->sh->cdev->ctx, &attr,
450 "Port %u Rx hairpin queue %u can't create rq object.",
451 dev->data->port_id, idx);
455 dev->data->rx_queue_state[idx] = RTE_ETH_QUEUE_STATE_HAIRPIN;
460 * Create the Rx queue DevX object.
463 * Pointer to Ethernet device.
465 * Queue index in DPDK Rx queue array.
468 * 0 on success, a negative errno value otherwise and rte_errno is set.
471 mlx5_rxq_devx_obj_new(struct rte_eth_dev *dev, uint16_t idx)
473 struct mlx5_priv *priv = dev->data->dev_private;
474 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
475 struct mlx5_rxq_ctrl *rxq_ctrl =
476 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
477 struct mlx5_rxq_obj *tmpl = rxq_ctrl->obj;
480 MLX5_ASSERT(rxq_data);
482 if (rxq_ctrl->type == MLX5_RXQ_TYPE_HAIRPIN)
483 return mlx5_rxq_obj_hairpin_new(dev, idx);
484 tmpl->rxq_ctrl = rxq_ctrl;
487 MLX5DV_DEVX_CREATE_EVENT_CHANNEL_FLAGS_OMIT_EV_DATA;
489 tmpl->devx_channel = mlx5_os_devx_create_event_channel
490 (priv->sh->cdev->ctx,
492 if (!tmpl->devx_channel) {
494 DRV_LOG(ERR, "Failed to create event channel %d.",
498 tmpl->fd = mlx5_os_get_devx_channel_fd(tmpl->devx_channel);
500 /* Create CQ using DevX API. */
501 ret = mlx5_rxq_create_devx_cq_resources(dev, idx);
503 DRV_LOG(ERR, "Failed to create CQ.");
506 /* Create RQ using DevX API. */
507 ret = mlx5_rxq_create_devx_rq_resources(dev, idx);
509 DRV_LOG(ERR, "Port %u Rx queue %u RQ creation failure.",
510 dev->data->port_id, idx);
514 /* Change queue state to ready. */
515 ret = mlx5_devx_modify_rq(tmpl, MLX5_RXQ_MOD_RST2RDY);
518 rxq_data->wqes = (void *)(uintptr_t)tmpl->rq_obj.umem_buf;
519 rxq_data->rq_db = (uint32_t *)(uintptr_t)tmpl->rq_obj.db_rec;
520 rxq_data->cq_arm_sn = 0;
522 mlx5_rxq_initialize(rxq_data);
523 dev->data->rx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STARTED;
524 rxq_ctrl->wqn = tmpl->rq_obj.rq->id;
527 ret = rte_errno; /* Save rte_errno before cleanup. */
528 mlx5_rxq_devx_obj_release(tmpl);
529 rte_errno = ret; /* Restore rte_errno. */
534 * Prepare RQT attribute structure for DevX RQT API.
537 * Pointer to Ethernet device.
539 * Log of number of queues in the array.
541 * DevX indirection table object.
544 * The RQT attr object initialized, NULL otherwise and rte_errno is set.
546 static struct mlx5_devx_rqt_attr *
547 mlx5_devx_ind_table_create_rqt_attr(struct rte_eth_dev *dev,
548 const unsigned int log_n,
549 const uint16_t *queues,
550 const uint32_t queues_n)
552 struct mlx5_priv *priv = dev->data->dev_private;
553 struct mlx5_devx_rqt_attr *rqt_attr = NULL;
554 const unsigned int rqt_n = 1 << log_n;
557 rqt_attr = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt_attr) +
558 rqt_n * sizeof(uint32_t), 0, SOCKET_ID_ANY);
560 DRV_LOG(ERR, "Port %u cannot allocate RQT resources.",
565 rqt_attr->rqt_max_size = priv->config.ind_table_max_size;
566 rqt_attr->rqt_actual_size = rqt_n;
567 for (i = 0; i != queues_n; ++i) {
568 struct mlx5_rxq_data *rxq = (*priv->rxqs)[queues[i]];
569 struct mlx5_rxq_ctrl *rxq_ctrl =
570 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
572 rqt_attr->rq_list[i] = rxq_ctrl->obj->rq_obj.rq->id;
575 for (j = 0; i != rqt_n; ++j, ++i)
576 rqt_attr->rq_list[i] = rqt_attr->rq_list[j];
581 * Create RQT using DevX API as a filed of indirection table.
584 * Pointer to Ethernet device.
586 * Log of number of queues in the array.
588 * DevX indirection table object.
591 * 0 on success, a negative errno value otherwise and rte_errno is set.
594 mlx5_devx_ind_table_new(struct rte_eth_dev *dev, const unsigned int log_n,
595 struct mlx5_ind_table_obj *ind_tbl)
597 struct mlx5_priv *priv = dev->data->dev_private;
598 struct mlx5_devx_rqt_attr *rqt_attr = NULL;
600 MLX5_ASSERT(ind_tbl);
601 rqt_attr = mlx5_devx_ind_table_create_rqt_attr(dev, log_n,
606 ind_tbl->rqt = mlx5_devx_cmd_create_rqt(priv->sh->cdev->ctx, rqt_attr);
609 DRV_LOG(ERR, "Port %u cannot create DevX RQT.",
618 * Modify RQT using DevX API as a filed of indirection table.
621 * Pointer to Ethernet device.
623 * Log of number of queues in the array.
625 * DevX indirection table object.
628 * 0 on success, a negative errno value otherwise and rte_errno is set.
631 mlx5_devx_ind_table_modify(struct rte_eth_dev *dev, const unsigned int log_n,
632 const uint16_t *queues, const uint32_t queues_n,
633 struct mlx5_ind_table_obj *ind_tbl)
636 struct mlx5_devx_rqt_attr *rqt_attr = NULL;
638 MLX5_ASSERT(ind_tbl);
639 rqt_attr = mlx5_devx_ind_table_create_rqt_attr(dev, log_n,
644 ret = mlx5_devx_cmd_modify_rqt(ind_tbl->rqt, rqt_attr);
647 DRV_LOG(ERR, "Port %u cannot modify DevX RQT.",
653 * Destroy the DevX RQT object.
656 * Indirection table to release.
659 mlx5_devx_ind_table_destroy(struct mlx5_ind_table_obj *ind_tbl)
661 claim_zero(mlx5_devx_cmd_destroy(ind_tbl->rqt));
665 * Set TIR attribute struct with relevant input values.
668 * Pointer to Ethernet device.
670 * RSS key for the Rx hash queue.
671 * @param[in] hash_fields
672 * Verbs protocol hash field to make the RSS on.
674 * Indirection table for TIR.
677 * @param[out] tir_attr
678 * Parameters structure for TIR creation/modification.
681 * The Verbs/DevX object initialised index, 0 otherwise and rte_errno is set.
684 mlx5_devx_tir_attr_set(struct rte_eth_dev *dev, const uint8_t *rss_key,
685 uint64_t hash_fields,
686 const struct mlx5_ind_table_obj *ind_tbl,
687 int tunnel, struct mlx5_devx_tir_attr *tir_attr)
689 struct mlx5_priv *priv = dev->data->dev_private;
690 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[ind_tbl->queues[0]];
691 struct mlx5_rxq_ctrl *rxq_ctrl =
692 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
693 enum mlx5_rxq_type rxq_obj_type = rxq_ctrl->type;
697 /* Enable TIR LRO only if all the queues were configured for. */
698 for (i = 0; i < ind_tbl->queues_n; ++i) {
699 if (!(*priv->rxqs)[ind_tbl->queues[i]]->lro) {
704 memset(tir_attr, 0, sizeof(*tir_attr));
705 tir_attr->disp_type = MLX5_TIRC_DISP_TYPE_INDIRECT;
706 tir_attr->rx_hash_fn = MLX5_RX_HASH_FN_TOEPLITZ;
707 tir_attr->tunneled_offload_en = !!tunnel;
708 /* If needed, translate hash_fields bitmap to PRM format. */
710 struct mlx5_rx_hash_field_select *rx_hash_field_select =
711 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
712 hash_fields & IBV_RX_HASH_INNER ?
713 &tir_attr->rx_hash_field_selector_inner :
715 &tir_attr->rx_hash_field_selector_outer;
716 /* 1 bit: 0: IPv4, 1: IPv6. */
717 rx_hash_field_select->l3_prot_type =
718 !!(hash_fields & MLX5_IPV6_IBV_RX_HASH);
719 /* 1 bit: 0: TCP, 1: UDP. */
720 rx_hash_field_select->l4_prot_type =
721 !!(hash_fields & MLX5_UDP_IBV_RX_HASH);
722 /* Bitmask which sets which fields to use in RX Hash. */
723 rx_hash_field_select->selected_fields =
724 ((!!(hash_fields & MLX5_L3_SRC_IBV_RX_HASH)) <<
725 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP) |
726 (!!(hash_fields & MLX5_L3_DST_IBV_RX_HASH)) <<
727 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP |
728 (!!(hash_fields & MLX5_L4_SRC_IBV_RX_HASH)) <<
729 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT |
730 (!!(hash_fields & MLX5_L4_DST_IBV_RX_HASH)) <<
731 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT;
733 if (rxq_obj_type == MLX5_RXQ_TYPE_HAIRPIN)
734 tir_attr->transport_domain = priv->sh->td->id;
736 tir_attr->transport_domain = priv->sh->tdn;
737 memcpy(tir_attr->rx_hash_toeplitz_key, rss_key, MLX5_RSS_HASH_KEY_LEN);
738 tir_attr->indirect_table = ind_tbl->rqt->id;
739 if (dev->data->dev_conf.lpbk_mode)
740 tir_attr->self_lb_block =
741 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
743 tir_attr->lro_timeout_period_usecs = priv->config.lro.timeout;
744 tir_attr->lro_max_msg_sz = priv->max_lro_msg_size;
745 tir_attr->lro_enable_mask =
746 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
747 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO;
752 * Create an Rx Hash queue.
755 * Pointer to Ethernet device.
757 * Pointer to Rx Hash queue.
762 * 0 on success, a negative errno value otherwise and rte_errno is set.
765 mlx5_devx_hrxq_new(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq,
766 int tunnel __rte_unused)
768 struct mlx5_priv *priv = dev->data->dev_private;
769 struct mlx5_devx_tir_attr tir_attr = {0};
772 mlx5_devx_tir_attr_set(dev, hrxq->rss_key, hrxq->hash_fields,
773 hrxq->ind_table, tunnel, &tir_attr);
774 hrxq->tir = mlx5_devx_cmd_create_tir(priv->sh->cdev->ctx, &tir_attr);
776 DRV_LOG(ERR, "Port %u cannot create DevX TIR.",
781 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
782 if (mlx5_flow_os_create_flow_action_dest_devx_tir(hrxq->tir,
790 err = rte_errno; /* Save rte_errno before cleanup. */
792 claim_zero(mlx5_devx_cmd_destroy(hrxq->tir));
793 rte_errno = err; /* Restore rte_errno. */
798 * Destroy a DevX TIR object.
801 * Hash Rx queue to release its tir.
804 mlx5_devx_tir_destroy(struct mlx5_hrxq *hrxq)
806 claim_zero(mlx5_devx_cmd_destroy(hrxq->tir));
810 * Modify an Rx Hash queue configuration.
813 * Pointer to Ethernet device.
815 * Hash Rx queue to modify.
817 * RSS key for the Rx hash queue.
819 * Verbs protocol hash field to make the RSS on.
821 * Indirection table for TIR.
824 * 0 on success, a negative errno value otherwise and rte_errno is set.
827 mlx5_devx_hrxq_modify(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq,
828 const uint8_t *rss_key,
829 uint64_t hash_fields,
830 const struct mlx5_ind_table_obj *ind_tbl)
832 struct mlx5_devx_modify_tir_attr modify_tir = {0};
835 * untested for modification fields:
836 * - rx_hash_symmetric not set in hrxq_new(),
837 * - rx_hash_fn set hard-coded in hrxq_new(),
838 * - lro_xxx not set after rxq setup
840 if (ind_tbl != hrxq->ind_table)
841 modify_tir.modify_bitmask |=
842 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE;
843 if (hash_fields != hrxq->hash_fields ||
844 memcmp(hrxq->rss_key, rss_key, MLX5_RSS_HASH_KEY_LEN))
845 modify_tir.modify_bitmask |=
846 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH;
847 mlx5_devx_tir_attr_set(dev, rss_key, hash_fields, ind_tbl,
848 0, /* N/A - tunnel modification unsupported */
850 modify_tir.tirn = hrxq->tir->id;
851 if (mlx5_devx_cmd_modify_tir(hrxq->tir, &modify_tir)) {
852 DRV_LOG(ERR, "port %u cannot modify DevX TIR",
861 * Create a DevX drop action for Rx Hash queue.
864 * Pointer to Ethernet device.
867 * 0 on success, a negative errno value otherwise and rte_errno is set.
870 mlx5_devx_drop_action_create(struct rte_eth_dev *dev)
873 DRV_LOG(ERR, "DevX drop action is not supported yet.");
879 * Release a drop hash Rx queue.
882 * Pointer to Ethernet device.
885 mlx5_devx_drop_action_destroy(struct rte_eth_dev *dev)
888 DRV_LOG(ERR, "DevX drop action is not supported yet.");
893 * Select TXQ TIS number.
896 * Pointer to Ethernet device.
898 * Queue index in DPDK Tx queue array.
901 * > 0 on success, a negative errno value otherwise.
904 mlx5_get_txq_tis_num(struct rte_eth_dev *dev, uint16_t queue_idx)
906 struct mlx5_priv *priv = dev->data->dev_private;
909 if (priv->sh->bond.n_port && priv->sh->lag.affinity_mode ==
911 tis_idx = (priv->lag_affinity_idx + queue_idx) %
912 priv->sh->bond.n_port;
913 DRV_LOG(INFO, "port %d txq %d gets affinity %d and maps to PF %d.",
914 dev->data->port_id, queue_idx, tis_idx + 1,
915 priv->sh->lag.tx_remap_affinity[tis_idx]);
919 MLX5_ASSERT(priv->sh->tis[tis_idx]);
920 return priv->sh->tis[tis_idx]->id;
924 * Create the Tx hairpin queue object.
927 * Pointer to Ethernet device.
929 * Queue index in DPDK Tx queue array.
932 * 0 on success, a negative errno value otherwise and rte_errno is set.
935 mlx5_txq_obj_hairpin_new(struct rte_eth_dev *dev, uint16_t idx)
937 struct mlx5_priv *priv = dev->data->dev_private;
938 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx];
939 struct mlx5_txq_ctrl *txq_ctrl =
940 container_of(txq_data, struct mlx5_txq_ctrl, txq);
941 struct mlx5_devx_create_sq_attr attr = { 0 };
942 struct mlx5_txq_obj *tmpl = txq_ctrl->obj;
943 uint32_t max_wq_data;
945 MLX5_ASSERT(txq_data);
947 tmpl->txq_ctrl = txq_ctrl;
950 max_wq_data = priv->config.hca_attr.log_max_hairpin_wq_data_sz;
951 /* Jumbo frames > 9KB should be supported, and more packets. */
952 if (priv->config.log_hp_size != (uint32_t)MLX5_ARG_UNSET) {
953 if (priv->config.log_hp_size > max_wq_data) {
954 DRV_LOG(ERR, "Total data size %u power of 2 is "
955 "too large for hairpin.",
956 priv->config.log_hp_size);
960 attr.wq_attr.log_hairpin_data_sz = priv->config.log_hp_size;
962 attr.wq_attr.log_hairpin_data_sz =
963 (max_wq_data < MLX5_HAIRPIN_JUMBO_LOG_SIZE) ?
964 max_wq_data : MLX5_HAIRPIN_JUMBO_LOG_SIZE;
966 /* Set the packets number to the maximum value for performance. */
967 attr.wq_attr.log_hairpin_num_packets =
968 attr.wq_attr.log_hairpin_data_sz -
969 MLX5_HAIRPIN_QUEUE_STRIDE;
971 attr.tis_num = mlx5_get_txq_tis_num(dev, idx);
972 tmpl->sq = mlx5_devx_cmd_create_sq(priv->sh->cdev->ctx, &attr);
975 "Port %u tx hairpin queue %u can't create SQ object.",
976 dev->data->port_id, idx);
983 #if defined(HAVE_MLX5DV_DEVX_UAR_OFFSET) || !defined(HAVE_INFINIBAND_VERBS_H)
985 * Destroy the Tx queue DevX object.
988 * Txq object to destroy.
991 mlx5_txq_release_devx_resources(struct mlx5_txq_obj *txq_obj)
993 mlx5_devx_sq_destroy(&txq_obj->sq_obj);
994 memset(&txq_obj->sq_obj, 0, sizeof(txq_obj->sq_obj));
995 mlx5_devx_cq_destroy(&txq_obj->cq_obj);
996 memset(&txq_obj->cq_obj, 0, sizeof(txq_obj->cq_obj));
1000 * Create a SQ object and its resources using DevX.
1003 * Pointer to Ethernet device.
1005 * Queue index in DPDK Tx queue array.
1006 * @param[in] log_desc_n
1007 * Log of number of descriptors in queue.
1010 * 0 on success, a negative errno value otherwise and rte_errno is set.
1013 mlx5_txq_create_devx_sq_resources(struct rte_eth_dev *dev, uint16_t idx,
1014 uint16_t log_desc_n)
1016 struct mlx5_priv *priv = dev->data->dev_private;
1017 struct mlx5_common_device *cdev = priv->sh->cdev;
1018 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx];
1019 struct mlx5_txq_ctrl *txq_ctrl =
1020 container_of(txq_data, struct mlx5_txq_ctrl, txq);
1021 struct mlx5_txq_obj *txq_obj = txq_ctrl->obj;
1022 struct mlx5_devx_create_sq_attr sq_attr = {
1023 .flush_in_error_en = 1,
1024 .allow_multi_pkt_send_wqe = !!priv->config.mps,
1025 .min_wqe_inline_mode = priv->config.hca_attr.vport_inline_mode,
1026 .allow_swp = !!priv->config.swp,
1027 .cqn = txq_obj->cq_obj.cq->id,
1029 .wq_attr = (struct mlx5_devx_wq_attr){
1032 mlx5_os_get_devx_uar_page_id(priv->sh->tx_uar),
1035 mlx5_ts_format_conv(cdev->config.hca_attr.sq_ts_format),
1036 .tis_num = mlx5_get_txq_tis_num(dev, idx),
1039 /* Create Send Queue object with DevX. */
1040 return mlx5_devx_sq_create(cdev->ctx, &txq_obj->sq_obj,
1041 log_desc_n, &sq_attr, priv->sh->numa_node);
1046 * Create the Tx queue DevX object.
1049 * Pointer to Ethernet device.
1051 * Queue index in DPDK Tx queue array.
1054 * 0 on success, a negative errno value otherwise and rte_errno is set.
1057 mlx5_txq_devx_obj_new(struct rte_eth_dev *dev, uint16_t idx)
1059 struct mlx5_priv *priv = dev->data->dev_private;
1060 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx];
1061 struct mlx5_txq_ctrl *txq_ctrl =
1062 container_of(txq_data, struct mlx5_txq_ctrl, txq);
1064 if (txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN)
1065 return mlx5_txq_obj_hairpin_new(dev, idx);
1066 #if !defined(HAVE_MLX5DV_DEVX_UAR_OFFSET) && defined(HAVE_INFINIBAND_VERBS_H)
1067 DRV_LOG(ERR, "Port %u Tx queue %u cannot create with DevX, no UAR.",
1068 dev->data->port_id, idx);
1072 struct mlx5_dev_ctx_shared *sh = priv->sh;
1073 struct mlx5_txq_obj *txq_obj = txq_ctrl->obj;
1074 struct mlx5_devx_cq_attr cq_attr = {
1075 .uar_page_id = mlx5_os_get_devx_uar_page_id(sh->tx_uar),
1078 uint32_t cqe_n, log_desc_n;
1079 uint32_t wqe_n, wqe_size;
1082 MLX5_ASSERT(txq_data);
1083 MLX5_ASSERT(txq_obj);
1084 txq_obj->txq_ctrl = txq_ctrl;
1086 cqe_n = (1UL << txq_data->elts_n) / MLX5_TX_COMP_THRESH +
1087 1 + MLX5_TX_COMP_THRESH_INLINE_DIV;
1088 log_desc_n = log2above(cqe_n);
1089 cqe_n = 1UL << log_desc_n;
1090 if (cqe_n > UINT16_MAX) {
1091 DRV_LOG(ERR, "Port %u Tx queue %u requests to many CQEs %u.",
1092 dev->data->port_id, txq_data->idx, cqe_n);
1096 /* Create completion queue object with DevX. */
1097 ret = mlx5_devx_cq_create(sh->cdev->ctx, &txq_obj->cq_obj, log_desc_n,
1098 &cq_attr, priv->sh->numa_node);
1100 DRV_LOG(ERR, "Port %u Tx queue %u CQ creation failure.",
1101 dev->data->port_id, idx);
1104 txq_data->cqe_n = log_desc_n;
1105 txq_data->cqe_s = cqe_n;
1106 txq_data->cqe_m = txq_data->cqe_s - 1;
1107 txq_data->cqes = txq_obj->cq_obj.cqes;
1108 txq_data->cq_ci = 0;
1109 txq_data->cq_pi = 0;
1110 txq_data->cq_db = txq_obj->cq_obj.db_rec;
1111 *txq_data->cq_db = 0;
1113 * Adjust the amount of WQEs depending on inline settings.
1114 * The number of descriptors should be enough to handle
1115 * the specified number of packets. If queue is being created
1116 * with Verbs the rdma-core does queue size adjustment
1117 * internally in the mlx5_calc_sq_size(), we do the same
1118 * for the queue being created with DevX at this point.
1120 wqe_size = txq_data->tso_en ?
1121 RTE_ALIGN(txq_ctrl->max_tso_header, MLX5_WSEG_SIZE) : 0;
1122 wqe_size += sizeof(struct mlx5_wqe_cseg) +
1123 sizeof(struct mlx5_wqe_eseg) +
1124 sizeof(struct mlx5_wqe_dseg);
1125 if (txq_data->inlen_send)
1126 wqe_size = RTE_MAX(wqe_size, sizeof(struct mlx5_wqe_cseg) +
1127 sizeof(struct mlx5_wqe_eseg) +
1128 RTE_ALIGN(txq_data->inlen_send +
1131 wqe_size = RTE_ALIGN(wqe_size, MLX5_WQE_SIZE) / MLX5_WQE_SIZE;
1132 /* Create Send Queue object with DevX. */
1133 wqe_n = RTE_MIN((1UL << txq_data->elts_n) * wqe_size,
1134 (uint32_t)priv->sh->device_attr.max_qp_wr);
1135 log_desc_n = log2above(wqe_n);
1136 ret = mlx5_txq_create_devx_sq_resources(dev, idx, log_desc_n);
1138 DRV_LOG(ERR, "Port %u Tx queue %u SQ creation failure.",
1139 dev->data->port_id, idx);
1143 /* Create the Work Queue. */
1144 txq_data->wqe_n = log_desc_n;
1145 txq_data->wqe_s = 1 << txq_data->wqe_n;
1146 txq_data->wqe_m = txq_data->wqe_s - 1;
1147 txq_data->wqes = (struct mlx5_wqe *)(uintptr_t)txq_obj->sq_obj.wqes;
1148 txq_data->wqes_end = txq_data->wqes + txq_data->wqe_s;
1149 txq_data->wqe_ci = 0;
1150 txq_data->wqe_pi = 0;
1151 txq_data->wqe_comp = 0;
1152 txq_data->wqe_thres = txq_data->wqe_s / MLX5_TX_COMP_THRESH_INLINE_DIV;
1153 txq_data->qp_db = &txq_obj->sq_obj.db_rec[MLX5_SND_DBR];
1154 *txq_data->qp_db = 0;
1155 txq_data->qp_num_8s = txq_obj->sq_obj.sq->id << 8;
1156 /* Change Send Queue state to Ready-to-Send. */
1157 ret = mlx5_txq_devx_modify(txq_obj, MLX5_TXQ_MOD_RST2RDY, 0);
1161 "Port %u Tx queue %u SQ state to SQC_STATE_RDY failed.",
1162 dev->data->port_id, idx);
1165 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1167 * If using DevX need to query and store TIS transport domain value.
1168 * This is done once per port.
1169 * Will use this value on Rx, when creating matching TIR.
1172 priv->sh->tdn = priv->sh->td->id;
1174 MLX5_ASSERT(sh->tx_uar);
1175 reg_addr = mlx5_os_get_devx_uar_reg_addr(sh->tx_uar);
1176 MLX5_ASSERT(reg_addr);
1177 txq_ctrl->bf_reg = reg_addr;
1178 txq_ctrl->uar_mmap_offset =
1179 mlx5_os_get_devx_uar_mmap_offset(sh->tx_uar);
1180 txq_uar_init(txq_ctrl);
1181 dev->data->tx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STARTED;
1184 ret = rte_errno; /* Save rte_errno before cleanup. */
1185 mlx5_txq_release_devx_resources(txq_obj);
1186 rte_errno = ret; /* Restore rte_errno. */
1192 * Release an Tx DevX queue object.
1195 * DevX Tx queue object.
1198 mlx5_txq_devx_obj_release(struct mlx5_txq_obj *txq_obj)
1200 MLX5_ASSERT(txq_obj);
1201 if (txq_obj->txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) {
1203 claim_zero(mlx5_devx_cmd_destroy(txq_obj->tis));
1204 #if defined(HAVE_MLX5DV_DEVX_UAR_OFFSET) || !defined(HAVE_INFINIBAND_VERBS_H)
1206 mlx5_txq_release_devx_resources(txq_obj);
1211 struct mlx5_obj_ops devx_obj_ops = {
1212 .rxq_obj_modify_vlan_strip = mlx5_rxq_obj_modify_rq_vlan_strip,
1213 .rxq_obj_new = mlx5_rxq_devx_obj_new,
1214 .rxq_event_get = mlx5_rx_devx_get_event,
1215 .rxq_obj_modify = mlx5_devx_modify_rq,
1216 .rxq_obj_release = mlx5_rxq_devx_obj_release,
1217 .ind_table_new = mlx5_devx_ind_table_new,
1218 .ind_table_modify = mlx5_devx_ind_table_modify,
1219 .ind_table_destroy = mlx5_devx_ind_table_destroy,
1220 .hrxq_new = mlx5_devx_hrxq_new,
1221 .hrxq_destroy = mlx5_devx_tir_destroy,
1222 .hrxq_modify = mlx5_devx_hrxq_modify,
1223 .drop_action_create = mlx5_devx_drop_action_create,
1224 .drop_action_destroy = mlx5_devx_drop_action_destroy,
1225 .txq_obj_new = mlx5_txq_devx_obj_new,
1226 .txq_obj_modify = mlx5_txq_devx_modify,
1227 .txq_obj_release = mlx5_txq_devx_obj_release,
1228 .lb_dummy_queue_create = NULL,
1229 .lb_dummy_queue_release = NULL,