1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2020 Mellanox Technologies, Ltd
10 #include <sys/queue.h>
12 #include <rte_malloc.h>
13 #include <rte_common.h>
14 #include <rte_eal_paging.h>
16 #include <mlx5_glue.h>
17 #include <mlx5_devx_cmds.h>
18 #include <mlx5_common_devx.h>
19 #include <mlx5_malloc.h>
22 #include "mlx5_common_os.h"
23 #include "mlx5_rxtx.h"
24 #include "mlx5_utils.h"
25 #include "mlx5_devx.h"
26 #include "mlx5_flow.h"
27 #include "mlx5_flow_os.h"
30 * Modify RQ vlan stripping offload
36 * 0 on success, non-0 otherwise
39 mlx5_rxq_obj_modify_rq_vlan_strip(struct mlx5_rxq_obj *rxq_obj, int on)
41 struct mlx5_devx_modify_rq_attr rq_attr;
43 memset(&rq_attr, 0, sizeof(rq_attr));
44 rq_attr.rq_state = MLX5_RQC_STATE_RDY;
45 rq_attr.state = MLX5_RQC_STATE_RDY;
46 rq_attr.vsd = (on ? 0 : 1);
47 rq_attr.modify_bitmask = MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD;
48 return mlx5_devx_cmd_modify_rq(rxq_obj->rq, &rq_attr);
52 * Modify RQ using DevX API.
55 * DevX Rx queue object.
57 * Type of change queue state.
60 * 0 on success, a negative errno value otherwise and rte_errno is set.
63 mlx5_devx_modify_rq(struct mlx5_rxq_obj *rxq_obj, uint8_t type)
65 struct mlx5_devx_modify_rq_attr rq_attr;
67 memset(&rq_attr, 0, sizeof(rq_attr));
69 case MLX5_RXQ_MOD_ERR2RST:
70 rq_attr.rq_state = MLX5_RQC_STATE_ERR;
71 rq_attr.state = MLX5_RQC_STATE_RST;
73 case MLX5_RXQ_MOD_RST2RDY:
74 rq_attr.rq_state = MLX5_RQC_STATE_RST;
75 rq_attr.state = MLX5_RQC_STATE_RDY;
77 case MLX5_RXQ_MOD_RDY2ERR:
78 rq_attr.rq_state = MLX5_RQC_STATE_RDY;
79 rq_attr.state = MLX5_RQC_STATE_ERR;
81 case MLX5_RXQ_MOD_RDY2RST:
82 rq_attr.rq_state = MLX5_RQC_STATE_RDY;
83 rq_attr.state = MLX5_RQC_STATE_RST;
88 return mlx5_devx_cmd_modify_rq(rxq_obj->rq, &rq_attr);
92 * Modify SQ using DevX API.
95 * DevX Tx queue object.
97 * Type of change queue state.
102 * 0 on success, a negative errno value otherwise and rte_errno is set.
105 mlx5_devx_modify_sq(struct mlx5_txq_obj *obj, enum mlx5_txq_modify_type type,
108 struct mlx5_devx_modify_sq_attr msq_attr = { 0 };
111 if (type != MLX5_TXQ_MOD_RST2RDY) {
112 /* Change queue state to reset. */
113 if (type == MLX5_TXQ_MOD_ERR2RDY)
114 msq_attr.sq_state = MLX5_SQC_STATE_ERR;
116 msq_attr.sq_state = MLX5_SQC_STATE_RDY;
117 msq_attr.state = MLX5_SQC_STATE_RST;
118 ret = mlx5_devx_cmd_modify_sq(obj->sq_devx, &msq_attr);
120 DRV_LOG(ERR, "Cannot change the Tx SQ state to RESET"
121 " %s", strerror(errno));
126 if (type != MLX5_TXQ_MOD_RDY2RST) {
127 /* Change queue state to ready. */
128 msq_attr.sq_state = MLX5_SQC_STATE_RST;
129 msq_attr.state = MLX5_SQC_STATE_RDY;
130 ret = mlx5_devx_cmd_modify_sq(obj->sq_devx, &msq_attr);
132 DRV_LOG(ERR, "Cannot change the Tx SQ state to READY"
133 " %s", strerror(errno));
139 * The dev_port variable is relevant only in Verbs API, and there is a
140 * pointer that points to this function and a parallel function in verbs
141 * intermittently, so they should have the same parameters.
148 * Release the resources allocated for an RQ DevX object.
151 * DevX Rx queue object.
154 mlx5_rxq_release_devx_rq_resources(struct mlx5_rxq_ctrl *rxq_ctrl)
156 struct mlx5_devx_dbr_page *dbr_page = rxq_ctrl->rq_dbrec_page;
158 if (rxq_ctrl->wq_umem) {
159 mlx5_os_umem_dereg(rxq_ctrl->wq_umem);
160 rxq_ctrl->wq_umem = NULL;
162 if (rxq_ctrl->rxq.wqes) {
163 mlx5_free((void *)(uintptr_t)rxq_ctrl->rxq.wqes);
164 rxq_ctrl->rxq.wqes = NULL;
167 claim_zero(mlx5_release_dbr(&rxq_ctrl->priv->dbrpgs,
168 mlx5_os_get_umem_id(dbr_page->umem),
169 rxq_ctrl->rq_dbr_offset));
170 rxq_ctrl->rq_dbrec_page = NULL;
175 * Destroy the Rx queue DevX object.
178 * Rxq object to destroy.
181 mlx5_rxq_release_devx_resources(struct mlx5_rxq_ctrl *rxq_ctrl)
183 mlx5_rxq_release_devx_rq_resources(rxq_ctrl);
184 mlx5_devx_cq_destroy(&rxq_ctrl->obj->cq_obj);
185 memset(&rxq_ctrl->obj->cq_obj, 0, sizeof(rxq_ctrl->obj->cq_obj));
189 * Release an Rx DevX queue object.
192 * DevX Rx queue object.
195 mlx5_rxq_devx_obj_release(struct mlx5_rxq_obj *rxq_obj)
197 MLX5_ASSERT(rxq_obj);
198 MLX5_ASSERT(rxq_obj->rq);
199 if (rxq_obj->rxq_ctrl->type == MLX5_RXQ_TYPE_HAIRPIN) {
200 mlx5_devx_modify_rq(rxq_obj, MLX5_RXQ_MOD_RDY2RST);
201 claim_zero(mlx5_devx_cmd_destroy(rxq_obj->rq));
203 MLX5_ASSERT(rxq_obj->cq_obj);
204 claim_zero(mlx5_devx_cmd_destroy(rxq_obj->rq));
205 if (rxq_obj->devx_channel)
206 mlx5_os_devx_destroy_event_channel
207 (rxq_obj->devx_channel);
208 mlx5_rxq_release_devx_resources(rxq_obj->rxq_ctrl);
213 * Get event for an Rx DevX queue object.
216 * DevX Rx queue object.
219 * 0 on success, a negative errno value otherwise and rte_errno is set.
222 mlx5_rx_devx_get_event(struct mlx5_rxq_obj *rxq_obj)
224 #ifdef HAVE_IBV_DEVX_EVENT
226 struct mlx5dv_devx_async_event_hdr event_resp;
227 uint8_t buf[sizeof(struct mlx5dv_devx_async_event_hdr) + 128];
229 int ret = mlx5_glue->devx_get_event(rxq_obj->devx_channel,
237 if (out.event_resp.cookie != (uint64_t)(uintptr_t)rxq_obj->cq_obj.cq) {
246 #endif /* HAVE_IBV_DEVX_EVENT */
250 * Fill common fields of create RQ attributes structure.
253 * Pointer to Rx queue data.
255 * CQ number to use with this RQ.
257 * RQ attributes structure to fill..
260 mlx5_devx_create_rq_attr_fill(struct mlx5_rxq_data *rxq_data, uint32_t cqn,
261 struct mlx5_devx_create_rq_attr *rq_attr)
263 rq_attr->state = MLX5_RQC_STATE_RST;
264 rq_attr->vsd = (rxq_data->vlan_strip) ? 0 : 1;
266 rq_attr->scatter_fcs = (rxq_data->crc_present) ? 1 : 0;
270 * Fill common fields of DevX WQ attributes structure.
273 * Pointer to device private data.
275 * Pointer to Rx queue control structure.
277 * WQ attributes structure to fill..
280 mlx5_devx_wq_attr_fill(struct mlx5_priv *priv, struct mlx5_rxq_ctrl *rxq_ctrl,
281 struct mlx5_devx_wq_attr *wq_attr)
283 wq_attr->end_padding_mode = priv->config.hw_padding ?
284 MLX5_WQ_END_PAD_MODE_ALIGN :
285 MLX5_WQ_END_PAD_MODE_NONE;
286 wq_attr->pd = priv->sh->pdn;
287 wq_attr->dbr_addr = rxq_ctrl->rq_dbr_offset;
288 wq_attr->dbr_umem_id =
289 mlx5_os_get_umem_id(rxq_ctrl->rq_dbrec_page->umem);
290 wq_attr->dbr_umem_valid = 1;
291 wq_attr->wq_umem_id = mlx5_os_get_umem_id(rxq_ctrl->wq_umem);
292 wq_attr->wq_umem_valid = 1;
296 * Create a RQ object using DevX.
299 * Pointer to Ethernet device.
301 * Queue index in DPDK Rx queue array.
304 * The DevX RQ object initialized, NULL otherwise and rte_errno is set.
306 static struct mlx5_devx_obj *
307 mlx5_rxq_create_devx_rq_resources(struct rte_eth_dev *dev, uint16_t idx)
309 struct mlx5_priv *priv = dev->data->dev_private;
310 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
311 struct mlx5_rxq_ctrl *rxq_ctrl =
312 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
313 struct mlx5_devx_create_rq_attr rq_attr = { 0 };
314 uint32_t wqe_n = 1 << (rxq_data->elts_n - rxq_data->sges_n);
315 uint32_t cqn = rxq_ctrl->obj->cq_obj.cq->id;
316 struct mlx5_devx_dbr_page *dbr_page;
318 uint32_t wq_size = 0;
319 uint32_t wqe_size = 0;
320 uint32_t log_wqe_size = 0;
322 struct mlx5_devx_obj *rq;
324 /* Fill RQ attributes. */
325 rq_attr.mem_rq_type = MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE;
326 rq_attr.flush_in_error_en = 1;
327 mlx5_devx_create_rq_attr_fill(rxq_data, cqn, &rq_attr);
328 /* Fill WQ attributes for this RQ. */
329 if (mlx5_rxq_mprq_enabled(rxq_data)) {
330 rq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ;
332 * Number of strides in each WQE:
333 * 512*2^single_wqe_log_num_of_strides.
335 rq_attr.wq_attr.single_wqe_log_num_of_strides =
336 rxq_data->strd_num_n -
337 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
338 /* Stride size = (2^single_stride_log_num_of_bytes)*64B. */
339 rq_attr.wq_attr.single_stride_log_num_of_bytes =
340 rxq_data->strd_sz_n -
341 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
342 wqe_size = sizeof(struct mlx5_wqe_mprq);
344 rq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC;
345 wqe_size = sizeof(struct mlx5_wqe_data_seg);
347 log_wqe_size = log2above(wqe_size) + rxq_data->sges_n;
348 rq_attr.wq_attr.log_wq_stride = log_wqe_size;
349 rq_attr.wq_attr.log_wq_sz = rxq_data->elts_n - rxq_data->sges_n;
350 /* Calculate and allocate WQ memory space. */
351 wqe_size = 1 << log_wqe_size; /* round up power of two.*/
352 wq_size = wqe_n * wqe_size;
353 size_t alignment = MLX5_WQE_BUF_ALIGNMENT;
354 if (alignment == (size_t)-1) {
355 DRV_LOG(ERR, "Failed to get mem page size");
359 buf = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, wq_size,
360 alignment, rxq_ctrl->socket);
363 rxq_data->wqes = buf;
364 rxq_ctrl->wq_umem = mlx5_os_umem_reg(priv->sh->ctx,
366 if (!rxq_ctrl->wq_umem)
368 /* Allocate RQ door-bell. */
369 dbr_offset = mlx5_get_dbr(priv->sh->ctx, &priv->dbrpgs, &dbr_page);
370 if (dbr_offset < 0) {
371 DRV_LOG(ERR, "Failed to allocate RQ door-bell.");
374 rxq_ctrl->rq_dbr_offset = dbr_offset;
375 rxq_ctrl->rq_dbrec_page = dbr_page;
376 rxq_data->rq_db = (uint32_t *)((uintptr_t)dbr_page->dbrs +
377 (uintptr_t)rxq_ctrl->rq_dbr_offset);
378 /* Create RQ using DevX API. */
379 mlx5_devx_wq_attr_fill(priv, rxq_ctrl, &rq_attr.wq_attr);
380 rq = mlx5_devx_cmd_create_rq(priv->sh->ctx, &rq_attr, rxq_ctrl->socket);
385 mlx5_rxq_release_devx_rq_resources(rxq_ctrl);
390 * Create a DevX CQ object for an Rx queue.
393 * Pointer to Ethernet device.
395 * Queue index in DPDK Rx queue array.
398 * 0 on success, a negative errno value otherwise and rte_errno is set.
401 mlx5_rxq_create_devx_cq_resources(struct rte_eth_dev *dev, uint16_t idx)
403 struct mlx5_devx_cq *cq_obj = 0;
404 struct mlx5_devx_cq_attr cq_attr = { 0 };
405 struct mlx5_priv *priv = dev->data->dev_private;
406 struct mlx5_dev_ctx_shared *sh = priv->sh;
407 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
408 struct mlx5_rxq_ctrl *rxq_ctrl =
409 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
410 unsigned int cqe_n = mlx5_rxq_cqe_num(rxq_data);
412 uint16_t event_nums[1] = { 0 };
415 if (priv->config.cqe_comp && !rxq_data->hw_timestamp &&
417 cq_attr.cqe_comp_en = 1u;
418 rxq_data->mcqe_format = priv->config.cqe_comp_fmt;
419 rxq_data->byte_mask = UINT32_MAX;
420 switch (priv->config.cqe_comp_fmt) {
421 case MLX5_CQE_RESP_FORMAT_HASH:
423 case MLX5_CQE_RESP_FORMAT_CSUM:
425 * Select CSUM miniCQE format only for non-vectorized
426 * MPRQ Rx burst, use HASH miniCQE format for others.
428 if (mlx5_rxq_check_vec_support(rxq_data) < 0 &&
429 mlx5_rxq_mprq_enabled(rxq_data))
430 cq_attr.mini_cqe_res_format =
431 MLX5_CQE_RESP_FORMAT_CSUM_STRIDX;
433 cq_attr.mini_cqe_res_format =
434 MLX5_CQE_RESP_FORMAT_HASH;
435 rxq_data->mcqe_format = cq_attr.mini_cqe_res_format;
437 case MLX5_CQE_RESP_FORMAT_FTAG_STRIDX:
438 rxq_data->byte_mask = MLX5_LEN_WITH_MARK_MASK;
440 case MLX5_CQE_RESP_FORMAT_CSUM_STRIDX:
441 cq_attr.mini_cqe_res_format = priv->config.cqe_comp_fmt;
443 case MLX5_CQE_RESP_FORMAT_L34H_STRIDX:
444 cq_attr.mini_cqe_res_format = 0;
445 cq_attr.mini_cqe_res_format_ext = 1;
449 "Port %u Rx CQE compression is enabled, format %d.",
450 dev->data->port_id, priv->config.cqe_comp_fmt);
452 * For vectorized Rx, it must not be doubled in order to
453 * make cq_ci and rq_ci aligned.
455 if (mlx5_rxq_check_vec_support(rxq_data) < 0)
457 } else if (priv->config.cqe_comp && rxq_data->hw_timestamp) {
459 "Port %u Rx CQE compression is disabled for HW"
462 } else if (priv->config.cqe_comp && rxq_data->lro) {
464 "Port %u Rx CQE compression is disabled for LRO.",
467 cq_attr.uar_page_id = mlx5_os_get_devx_uar_page_id(sh->devx_rx_uar);
468 log_cqe_n = log2above(cqe_n);
469 /* Create CQ using DevX API. */
470 ret = mlx5_devx_cq_create(sh->ctx, &rxq_ctrl->obj->cq_obj, log_cqe_n,
471 &cq_attr, sh->numa_node);
474 cq_obj = &rxq_ctrl->obj->cq_obj;
475 rxq_data->cqes = (volatile struct mlx5_cqe (*)[])
476 (uintptr_t)cq_obj->cqes;
477 rxq_data->cq_db = cq_obj->db_rec;
478 rxq_data->cq_uar = mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar);
479 rxq_data->cqe_n = log_cqe_n;
480 rxq_data->cqn = cq_obj->cq->id;
481 if (rxq_ctrl->obj->devx_channel) {
482 ret = mlx5_os_devx_subscribe_devx_event
483 (rxq_ctrl->obj->devx_channel,
487 (uint64_t)(uintptr_t)cq_obj->cq);
489 DRV_LOG(ERR, "Fail to subscribe CQ to event channel.");
491 mlx5_devx_cq_destroy(cq_obj);
492 memset(cq_obj, 0, sizeof(*cq_obj));
501 * Create the Rx hairpin queue object.
504 * Pointer to Ethernet device.
506 * Queue index in DPDK Rx queue array.
509 * 0 on success, a negative errno value otherwise and rte_errno is set.
512 mlx5_rxq_obj_hairpin_new(struct rte_eth_dev *dev, uint16_t idx)
514 struct mlx5_priv *priv = dev->data->dev_private;
515 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
516 struct mlx5_rxq_ctrl *rxq_ctrl =
517 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
518 struct mlx5_devx_create_rq_attr attr = { 0 };
519 struct mlx5_rxq_obj *tmpl = rxq_ctrl->obj;
520 uint32_t max_wq_data;
522 MLX5_ASSERT(rxq_data);
524 tmpl->rxq_ctrl = rxq_ctrl;
526 max_wq_data = priv->config.hca_attr.log_max_hairpin_wq_data_sz;
527 /* Jumbo frames > 9KB should be supported, and more packets. */
528 if (priv->config.log_hp_size != (uint32_t)MLX5_ARG_UNSET) {
529 if (priv->config.log_hp_size > max_wq_data) {
530 DRV_LOG(ERR, "Total data size %u power of 2 is "
531 "too large for hairpin.",
532 priv->config.log_hp_size);
536 attr.wq_attr.log_hairpin_data_sz = priv->config.log_hp_size;
538 attr.wq_attr.log_hairpin_data_sz =
539 (max_wq_data < MLX5_HAIRPIN_JUMBO_LOG_SIZE) ?
540 max_wq_data : MLX5_HAIRPIN_JUMBO_LOG_SIZE;
542 /* Set the packets number to the maximum value for performance. */
543 attr.wq_attr.log_hairpin_num_packets =
544 attr.wq_attr.log_hairpin_data_sz -
545 MLX5_HAIRPIN_QUEUE_STRIDE;
546 tmpl->rq = mlx5_devx_cmd_create_rq(priv->sh->ctx, &attr,
550 "Port %u Rx hairpin queue %u can't create rq object.",
551 dev->data->port_id, idx);
555 dev->data->rx_queue_state[idx] = RTE_ETH_QUEUE_STATE_HAIRPIN;
560 * Create the Rx queue DevX object.
563 * Pointer to Ethernet device.
565 * Queue index in DPDK Rx queue array.
568 * 0 on success, a negative errno value otherwise and rte_errno is set.
571 mlx5_rxq_devx_obj_new(struct rte_eth_dev *dev, uint16_t idx)
573 struct mlx5_priv *priv = dev->data->dev_private;
574 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
575 struct mlx5_rxq_ctrl *rxq_ctrl =
576 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
577 struct mlx5_rxq_obj *tmpl = rxq_ctrl->obj;
580 MLX5_ASSERT(rxq_data);
582 if (rxq_ctrl->type == MLX5_RXQ_TYPE_HAIRPIN)
583 return mlx5_rxq_obj_hairpin_new(dev, idx);
584 tmpl->rxq_ctrl = rxq_ctrl;
587 MLX5DV_DEVX_CREATE_EVENT_CHANNEL_FLAGS_OMIT_EV_DATA;
589 tmpl->devx_channel = mlx5_os_devx_create_event_channel
592 if (!tmpl->devx_channel) {
594 DRV_LOG(ERR, "Failed to create event channel %d.",
598 tmpl->fd = mlx5_os_get_devx_channel_fd(tmpl->devx_channel);
600 /* Create CQ using DevX API. */
601 ret = mlx5_rxq_create_devx_cq_resources(dev, idx);
603 DRV_LOG(ERR, "Failed to create CQ.");
606 /* Create RQ using DevX API. */
607 tmpl->rq = mlx5_rxq_create_devx_rq_resources(dev, idx);
609 DRV_LOG(ERR, "Port %u Rx queue %u RQ creation failure.",
610 dev->data->port_id, idx);
614 /* Change queue state to ready. */
615 ret = mlx5_devx_modify_rq(tmpl, MLX5_RXQ_MOD_RST2RDY);
618 rxq_data->cq_arm_sn = 0;
619 mlx5_rxq_initialize(rxq_data);
621 dev->data->rx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STARTED;
622 rxq_ctrl->wqn = tmpl->rq->id;
625 ret = rte_errno; /* Save rte_errno before cleanup. */
627 claim_zero(mlx5_devx_cmd_destroy(tmpl->rq));
628 if (tmpl->devx_channel)
629 mlx5_os_devx_destroy_event_channel(tmpl->devx_channel);
630 mlx5_rxq_release_devx_resources(rxq_ctrl);
631 rte_errno = ret; /* Restore rte_errno. */
636 * Prepare RQT attribute structure for DevX RQT API.
639 * Pointer to Ethernet device.
641 * Log of number of queues in the array.
643 * DevX indirection table object.
646 * The RQT attr object initialized, NULL otherwise and rte_errno is set.
648 static struct mlx5_devx_rqt_attr *
649 mlx5_devx_ind_table_create_rqt_attr(struct rte_eth_dev *dev,
650 const unsigned int log_n,
651 const uint16_t *queues,
652 const uint32_t queues_n)
654 struct mlx5_priv *priv = dev->data->dev_private;
655 struct mlx5_devx_rqt_attr *rqt_attr = NULL;
656 const unsigned int rqt_n = 1 << log_n;
659 rqt_attr = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt_attr) +
660 rqt_n * sizeof(uint32_t), 0, SOCKET_ID_ANY);
662 DRV_LOG(ERR, "Port %u cannot allocate RQT resources.",
667 rqt_attr->rqt_max_size = priv->config.ind_table_max_size;
668 rqt_attr->rqt_actual_size = rqt_n;
669 for (i = 0; i != queues_n; ++i) {
670 struct mlx5_rxq_data *rxq = (*priv->rxqs)[queues[i]];
671 struct mlx5_rxq_ctrl *rxq_ctrl =
672 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
674 rqt_attr->rq_list[i] = rxq_ctrl->obj->rq->id;
677 for (j = 0; i != rqt_n; ++j, ++i)
678 rqt_attr->rq_list[i] = rqt_attr->rq_list[j];
683 * Create RQT using DevX API as a filed of indirection table.
686 * Pointer to Ethernet device.
688 * Log of number of queues in the array.
690 * DevX indirection table object.
693 * 0 on success, a negative errno value otherwise and rte_errno is set.
696 mlx5_devx_ind_table_new(struct rte_eth_dev *dev, const unsigned int log_n,
697 struct mlx5_ind_table_obj *ind_tbl)
699 struct mlx5_priv *priv = dev->data->dev_private;
700 struct mlx5_devx_rqt_attr *rqt_attr = NULL;
702 MLX5_ASSERT(ind_tbl);
703 rqt_attr = mlx5_devx_ind_table_create_rqt_attr(dev, log_n,
708 ind_tbl->rqt = mlx5_devx_cmd_create_rqt(priv->sh->ctx, rqt_attr);
711 DRV_LOG(ERR, "Port %u cannot create DevX RQT.",
720 * Modify RQT using DevX API as a filed of indirection table.
723 * Pointer to Ethernet device.
725 * Log of number of queues in the array.
727 * DevX indirection table object.
730 * 0 on success, a negative errno value otherwise and rte_errno is set.
733 mlx5_devx_ind_table_modify(struct rte_eth_dev *dev, const unsigned int log_n,
734 const uint16_t *queues, const uint32_t queues_n,
735 struct mlx5_ind_table_obj *ind_tbl)
738 struct mlx5_devx_rqt_attr *rqt_attr = NULL;
740 MLX5_ASSERT(ind_tbl);
741 rqt_attr = mlx5_devx_ind_table_create_rqt_attr(dev, log_n,
746 ret = mlx5_devx_cmd_modify_rqt(ind_tbl->rqt, rqt_attr);
749 DRV_LOG(ERR, "Port %u cannot modify DevX RQT.",
755 * Destroy the DevX RQT object.
758 * Indirection table to release.
761 mlx5_devx_ind_table_destroy(struct mlx5_ind_table_obj *ind_tbl)
763 claim_zero(mlx5_devx_cmd_destroy(ind_tbl->rqt));
767 * Set TIR attribute struct with relevant input values.
770 * Pointer to Ethernet device.
772 * RSS key for the Rx hash queue.
773 * @param[in] hash_fields
774 * Verbs protocol hash field to make the RSS on.
776 * Indirection table for TIR.
779 * @param[out] tir_attr
780 * Parameters structure for TIR creation/modification.
783 * The Verbs/DevX object initialised index, 0 otherwise and rte_errno is set.
786 mlx5_devx_tir_attr_set(struct rte_eth_dev *dev, const uint8_t *rss_key,
787 uint64_t hash_fields,
788 const struct mlx5_ind_table_obj *ind_tbl,
789 int tunnel, struct mlx5_devx_tir_attr *tir_attr)
791 struct mlx5_priv *priv = dev->data->dev_private;
792 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[ind_tbl->queues[0]];
793 struct mlx5_rxq_ctrl *rxq_ctrl =
794 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
795 enum mlx5_rxq_type rxq_obj_type = rxq_ctrl->type;
799 /* Enable TIR LRO only if all the queues were configured for. */
800 for (i = 0; i < ind_tbl->queues_n; ++i) {
801 if (!(*priv->rxqs)[ind_tbl->queues[i]]->lro) {
806 memset(tir_attr, 0, sizeof(*tir_attr));
807 tir_attr->disp_type = MLX5_TIRC_DISP_TYPE_INDIRECT;
808 tir_attr->rx_hash_fn = MLX5_RX_HASH_FN_TOEPLITZ;
809 tir_attr->tunneled_offload_en = !!tunnel;
810 /* If needed, translate hash_fields bitmap to PRM format. */
812 struct mlx5_rx_hash_field_select *rx_hash_field_select =
813 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
814 hash_fields & IBV_RX_HASH_INNER ?
815 &tir_attr->rx_hash_field_selector_inner :
817 &tir_attr->rx_hash_field_selector_outer;
818 /* 1 bit: 0: IPv4, 1: IPv6. */
819 rx_hash_field_select->l3_prot_type =
820 !!(hash_fields & MLX5_IPV6_IBV_RX_HASH);
821 /* 1 bit: 0: TCP, 1: UDP. */
822 rx_hash_field_select->l4_prot_type =
823 !!(hash_fields & MLX5_UDP_IBV_RX_HASH);
824 /* Bitmask which sets which fields to use in RX Hash. */
825 rx_hash_field_select->selected_fields =
826 ((!!(hash_fields & MLX5_L3_SRC_IBV_RX_HASH)) <<
827 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP) |
828 (!!(hash_fields & MLX5_L3_DST_IBV_RX_HASH)) <<
829 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP |
830 (!!(hash_fields & MLX5_L4_SRC_IBV_RX_HASH)) <<
831 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT |
832 (!!(hash_fields & MLX5_L4_DST_IBV_RX_HASH)) <<
833 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT;
835 if (rxq_obj_type == MLX5_RXQ_TYPE_HAIRPIN)
836 tir_attr->transport_domain = priv->sh->td->id;
838 tir_attr->transport_domain = priv->sh->tdn;
839 memcpy(tir_attr->rx_hash_toeplitz_key, rss_key, MLX5_RSS_HASH_KEY_LEN);
840 tir_attr->indirect_table = ind_tbl->rqt->id;
841 if (dev->data->dev_conf.lpbk_mode)
842 tir_attr->self_lb_block =
843 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
845 tir_attr->lro_timeout_period_usecs = priv->config.lro.timeout;
846 tir_attr->lro_max_msg_sz = priv->max_lro_msg_size;
847 tir_attr->lro_enable_mask =
848 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
849 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO;
854 * Create an Rx Hash queue.
857 * Pointer to Ethernet device.
859 * Pointer to Rx Hash queue.
864 * 0 on success, a negative errno value otherwise and rte_errno is set.
867 mlx5_devx_hrxq_new(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq,
868 int tunnel __rte_unused)
870 struct mlx5_priv *priv = dev->data->dev_private;
871 struct mlx5_devx_tir_attr tir_attr = {0};
874 mlx5_devx_tir_attr_set(dev, hrxq->rss_key, hrxq->hash_fields,
875 hrxq->ind_table, tunnel, &tir_attr);
876 hrxq->tir = mlx5_devx_cmd_create_tir(priv->sh->ctx, &tir_attr);
878 DRV_LOG(ERR, "Port %u cannot create DevX TIR.",
883 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
884 if (mlx5_flow_os_create_flow_action_dest_devx_tir(hrxq->tir,
892 err = rte_errno; /* Save rte_errno before cleanup. */
894 claim_zero(mlx5_devx_cmd_destroy(hrxq->tir));
895 rte_errno = err; /* Restore rte_errno. */
900 * Destroy a DevX TIR object.
903 * Hash Rx queue to release its tir.
906 mlx5_devx_tir_destroy(struct mlx5_hrxq *hrxq)
908 claim_zero(mlx5_devx_cmd_destroy(hrxq->tir));
912 * Modify an Rx Hash queue configuration.
915 * Pointer to Ethernet device.
917 * Hash Rx queue to modify.
919 * RSS key for the Rx hash queue.
921 * Verbs protocol hash field to make the RSS on.
923 * Indirection table for TIR.
926 * 0 on success, a negative errno value otherwise and rte_errno is set.
929 mlx5_devx_hrxq_modify(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq,
930 const uint8_t *rss_key,
931 uint64_t hash_fields,
932 const struct mlx5_ind_table_obj *ind_tbl)
934 struct mlx5_devx_modify_tir_attr modify_tir = {0};
937 * untested for modification fields:
938 * - rx_hash_symmetric not set in hrxq_new(),
939 * - rx_hash_fn set hard-coded in hrxq_new(),
940 * - lro_xxx not set after rxq setup
942 if (ind_tbl != hrxq->ind_table)
943 modify_tir.modify_bitmask |=
944 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE;
945 if (hash_fields != hrxq->hash_fields ||
946 memcmp(hrxq->rss_key, rss_key, MLX5_RSS_HASH_KEY_LEN))
947 modify_tir.modify_bitmask |=
948 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH;
949 mlx5_devx_tir_attr_set(dev, rss_key, hash_fields, ind_tbl,
950 0, /* N/A - tunnel modification unsupported */
952 modify_tir.tirn = hrxq->tir->id;
953 if (mlx5_devx_cmd_modify_tir(hrxq->tir, &modify_tir)) {
954 DRV_LOG(ERR, "port %u cannot modify DevX TIR",
963 * Create a DevX drop action for Rx Hash queue.
966 * Pointer to Ethernet device.
969 * 0 on success, a negative errno value otherwise and rte_errno is set.
972 mlx5_devx_drop_action_create(struct rte_eth_dev *dev)
975 DRV_LOG(ERR, "DevX drop action is not supported yet.");
981 * Release a drop hash Rx queue.
984 * Pointer to Ethernet device.
987 mlx5_devx_drop_action_destroy(struct rte_eth_dev *dev)
990 DRV_LOG(ERR, "DevX drop action is not supported yet.");
995 * Create the Tx hairpin queue object.
998 * Pointer to Ethernet device.
1000 * Queue index in DPDK Tx queue array.
1003 * 0 on success, a negative errno value otherwise and rte_errno is set.
1006 mlx5_txq_obj_hairpin_new(struct rte_eth_dev *dev, uint16_t idx)
1008 struct mlx5_priv *priv = dev->data->dev_private;
1009 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx];
1010 struct mlx5_txq_ctrl *txq_ctrl =
1011 container_of(txq_data, struct mlx5_txq_ctrl, txq);
1012 struct mlx5_devx_create_sq_attr attr = { 0 };
1013 struct mlx5_txq_obj *tmpl = txq_ctrl->obj;
1014 uint32_t max_wq_data;
1016 MLX5_ASSERT(txq_data);
1018 tmpl->txq_ctrl = txq_ctrl;
1020 attr.tis_lst_sz = 1;
1021 max_wq_data = priv->config.hca_attr.log_max_hairpin_wq_data_sz;
1022 /* Jumbo frames > 9KB should be supported, and more packets. */
1023 if (priv->config.log_hp_size != (uint32_t)MLX5_ARG_UNSET) {
1024 if (priv->config.log_hp_size > max_wq_data) {
1025 DRV_LOG(ERR, "Total data size %u power of 2 is "
1026 "too large for hairpin.",
1027 priv->config.log_hp_size);
1031 attr.wq_attr.log_hairpin_data_sz = priv->config.log_hp_size;
1033 attr.wq_attr.log_hairpin_data_sz =
1034 (max_wq_data < MLX5_HAIRPIN_JUMBO_LOG_SIZE) ?
1035 max_wq_data : MLX5_HAIRPIN_JUMBO_LOG_SIZE;
1037 /* Set the packets number to the maximum value for performance. */
1038 attr.wq_attr.log_hairpin_num_packets =
1039 attr.wq_attr.log_hairpin_data_sz -
1040 MLX5_HAIRPIN_QUEUE_STRIDE;
1041 attr.tis_num = priv->sh->tis->id;
1042 tmpl->sq = mlx5_devx_cmd_create_sq(priv->sh->ctx, &attr);
1045 "Port %u tx hairpin queue %u can't create SQ object.",
1046 dev->data->port_id, idx);
1053 #if defined(HAVE_MLX5DV_DEVX_UAR_OFFSET) || !defined(HAVE_INFINIBAND_VERBS_H)
1055 * Release DevX SQ resources.
1058 * DevX Tx queue object.
1061 mlx5_txq_release_devx_sq_resources(struct mlx5_txq_obj *txq_obj)
1063 if (txq_obj->sq_devx) {
1064 claim_zero(mlx5_devx_cmd_destroy(txq_obj->sq_devx));
1065 txq_obj->sq_devx = NULL;
1067 if (txq_obj->sq_umem) {
1068 claim_zero(mlx5_os_umem_dereg(txq_obj->sq_umem));
1069 txq_obj->sq_umem = NULL;
1071 if (txq_obj->sq_buf) {
1072 mlx5_free(txq_obj->sq_buf);
1073 txq_obj->sq_buf = NULL;
1075 if (txq_obj->sq_dbrec_page) {
1076 claim_zero(mlx5_release_dbr(&txq_obj->txq_ctrl->priv->dbrpgs,
1078 (txq_obj->sq_dbrec_page->umem),
1079 txq_obj->sq_dbrec_offset));
1080 txq_obj->sq_dbrec_page = NULL;
1085 * Destroy the Tx queue DevX object.
1088 * Txq object to destroy.
1091 mlx5_txq_release_devx_resources(struct mlx5_txq_obj *txq_obj)
1093 mlx5_txq_release_devx_sq_resources(txq_obj);
1094 mlx5_devx_cq_destroy(&txq_obj->cq_obj);
1095 memset(&txq_obj->cq_obj, 0, sizeof(txq_obj->cq_obj));
1099 * Create a SQ object and its resources using DevX.
1102 * Pointer to Ethernet device.
1104 * Queue index in DPDK Tx queue array.
1107 * Number of WQEs in SQ, 0 otherwise and rte_errno is set.
1110 mlx5_txq_create_devx_sq_resources(struct rte_eth_dev *dev, uint16_t idx)
1112 struct mlx5_priv *priv = dev->data->dev_private;
1113 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx];
1114 struct mlx5_txq_ctrl *txq_ctrl =
1115 container_of(txq_data, struct mlx5_txq_ctrl, txq);
1116 struct mlx5_txq_obj *txq_obj = txq_ctrl->obj;
1117 struct mlx5_devx_create_sq_attr sq_attr = { 0 };
1122 MLX5_ASSERT(txq_data);
1123 MLX5_ASSERT(txq_obj);
1124 page_size = rte_mem_page_size();
1125 if (page_size == (size_t)-1) {
1126 DRV_LOG(ERR, "Failed to get mem page size.");
1130 wqe_n = RTE_MIN(1UL << txq_data->elts_n,
1131 (uint32_t)priv->sh->device_attr.max_qp_wr);
1132 txq_obj->sq_buf = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO,
1133 wqe_n * sizeof(struct mlx5_wqe),
1134 page_size, priv->sh->numa_node);
1135 if (!txq_obj->sq_buf) {
1137 "Port %u Tx queue %u cannot allocate memory (SQ).",
1138 dev->data->port_id, txq_data->idx);
1142 /* Register allocated buffer in user space with DevX. */
1143 txq_obj->sq_umem = mlx5_os_umem_reg
1145 (void *)txq_obj->sq_buf,
1146 wqe_n * sizeof(struct mlx5_wqe),
1147 IBV_ACCESS_LOCAL_WRITE);
1148 if (!txq_obj->sq_umem) {
1151 "Port %u Tx queue %u cannot register memory (SQ).",
1152 dev->data->port_id, txq_data->idx);
1155 /* Allocate doorbell record for send queue. */
1156 txq_obj->sq_dbrec_offset = mlx5_get_dbr(priv->sh->ctx,
1158 &txq_obj->sq_dbrec_page);
1159 if (txq_obj->sq_dbrec_offset < 0) {
1161 DRV_LOG(ERR, "Failed to allocate SQ door-bell.");
1164 sq_attr.tis_lst_sz = 1;
1165 sq_attr.tis_num = priv->sh->tis->id;
1166 sq_attr.state = MLX5_SQC_STATE_RST;
1167 sq_attr.cqn = txq_obj->cq_obj.cq->id;
1168 sq_attr.flush_in_error_en = 1;
1169 sq_attr.allow_multi_pkt_send_wqe = !!priv->config.mps;
1170 sq_attr.allow_swp = !!priv->config.swp;
1171 sq_attr.min_wqe_inline_mode = priv->config.hca_attr.vport_inline_mode;
1172 sq_attr.wq_attr.uar_page =
1173 mlx5_os_get_devx_uar_page_id(priv->sh->tx_uar);
1174 sq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC;
1175 sq_attr.wq_attr.pd = priv->sh->pdn;
1176 sq_attr.wq_attr.log_wq_stride = rte_log2_u32(MLX5_WQE_SIZE);
1177 sq_attr.wq_attr.log_wq_sz = log2above(wqe_n);
1178 sq_attr.wq_attr.dbr_umem_valid = 1;
1179 sq_attr.wq_attr.dbr_addr = txq_obj->sq_dbrec_offset;
1180 sq_attr.wq_attr.dbr_umem_id =
1181 mlx5_os_get_umem_id(txq_obj->sq_dbrec_page->umem);
1182 sq_attr.wq_attr.wq_umem_valid = 1;
1183 sq_attr.wq_attr.wq_umem_id = mlx5_os_get_umem_id(txq_obj->sq_umem);
1184 sq_attr.wq_attr.wq_umem_offset = (uintptr_t)txq_obj->sq_buf % page_size;
1185 /* Create Send Queue object with DevX. */
1186 txq_obj->sq_devx = mlx5_devx_cmd_create_sq(priv->sh->ctx, &sq_attr);
1187 if (!txq_obj->sq_devx) {
1189 DRV_LOG(ERR, "Port %u Tx queue %u SQ creation failure.",
1190 dev->data->port_id, idx);
1196 mlx5_txq_release_devx_sq_resources(txq_obj);
1203 * Create the Tx queue DevX object.
1206 * Pointer to Ethernet device.
1208 * Queue index in DPDK Tx queue array.
1211 * 0 on success, a negative errno value otherwise and rte_errno is set.
1214 mlx5_txq_devx_obj_new(struct rte_eth_dev *dev, uint16_t idx)
1216 struct mlx5_priv *priv = dev->data->dev_private;
1217 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx];
1218 struct mlx5_txq_ctrl *txq_ctrl =
1219 container_of(txq_data, struct mlx5_txq_ctrl, txq);
1221 if (txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN)
1222 return mlx5_txq_obj_hairpin_new(dev, idx);
1223 #if !defined(HAVE_MLX5DV_DEVX_UAR_OFFSET) && defined(HAVE_INFINIBAND_VERBS_H)
1224 DRV_LOG(ERR, "Port %u Tx queue %u cannot create with DevX, no UAR.",
1225 dev->data->port_id, idx);
1229 struct mlx5_dev_ctx_shared *sh = priv->sh;
1230 struct mlx5_txq_obj *txq_obj = txq_ctrl->obj;
1231 struct mlx5_devx_cq_attr cq_attr = {
1232 .uar_page_id = mlx5_os_get_devx_uar_page_id(sh->tx_uar),
1235 uint32_t cqe_n, log_desc_n;
1239 MLX5_ASSERT(txq_data);
1240 MLX5_ASSERT(txq_obj);
1241 txq_obj->txq_ctrl = txq_ctrl;
1243 cqe_n = (1UL << txq_data->elts_n) / MLX5_TX_COMP_THRESH +
1244 1 + MLX5_TX_COMP_THRESH_INLINE_DIV;
1245 log_desc_n = log2above(cqe_n);
1246 cqe_n = 1UL << log_desc_n;
1247 if (cqe_n > UINT16_MAX) {
1248 DRV_LOG(ERR, "Port %u Tx queue %u requests to many CQEs %u.",
1249 dev->data->port_id, txq_data->idx, cqe_n);
1253 /* Create completion queue object with DevX. */
1254 ret = mlx5_devx_cq_create(sh->ctx, &txq_obj->cq_obj, log_desc_n,
1255 &cq_attr, priv->sh->numa_node);
1257 DRV_LOG(ERR, "Port %u Tx queue %u CQ creation failure.",
1258 dev->data->port_id, idx);
1261 txq_data->cqe_n = log_desc_n;
1262 txq_data->cqe_s = cqe_n;
1263 txq_data->cqe_m = txq_data->cqe_s - 1;
1264 txq_data->cqes = txq_obj->cq_obj.cqes;
1265 txq_data->cq_ci = 0;
1266 txq_data->cq_pi = 0;
1267 txq_data->cq_db = txq_obj->cq_obj.db_rec;
1268 *txq_data->cq_db = 0;
1269 /* Create Send Queue object with DevX. */
1270 wqe_n = mlx5_txq_create_devx_sq_resources(dev, idx);
1275 /* Create the Work Queue. */
1276 txq_data->wqe_n = log2above(wqe_n);
1277 txq_data->wqe_s = 1 << txq_data->wqe_n;
1278 txq_data->wqe_m = txq_data->wqe_s - 1;
1279 txq_data->wqes = (struct mlx5_wqe *)txq_obj->sq_buf;
1280 txq_data->wqes_end = txq_data->wqes + txq_data->wqe_s;
1281 txq_data->wqe_ci = 0;
1282 txq_data->wqe_pi = 0;
1283 txq_data->wqe_comp = 0;
1284 txq_data->wqe_thres = txq_data->wqe_s / MLX5_TX_COMP_THRESH_INLINE_DIV;
1285 txq_data->qp_db = (volatile uint32_t *)
1286 (txq_obj->sq_dbrec_page->dbrs +
1287 txq_obj->sq_dbrec_offset +
1288 MLX5_SND_DBR * sizeof(uint32_t));
1289 *txq_data->qp_db = 0;
1290 txq_data->qp_num_8s = txq_obj->sq_devx->id << 8;
1291 /* Change Send Queue state to Ready-to-Send. */
1292 ret = mlx5_devx_modify_sq(txq_obj, MLX5_TXQ_MOD_RST2RDY, 0);
1296 "Port %u Tx queue %u SQ state to SQC_STATE_RDY failed.",
1297 dev->data->port_id, idx);
1300 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1302 * If using DevX need to query and store TIS transport domain value.
1303 * This is done once per port.
1304 * Will use this value on Rx, when creating matching TIR.
1307 priv->sh->tdn = priv->sh->td->id;
1309 MLX5_ASSERT(sh->tx_uar);
1310 reg_addr = mlx5_os_get_devx_uar_reg_addr(sh->tx_uar);
1311 MLX5_ASSERT(reg_addr);
1312 txq_ctrl->bf_reg = reg_addr;
1313 txq_ctrl->uar_mmap_offset =
1314 mlx5_os_get_devx_uar_mmap_offset(sh->tx_uar);
1315 txq_uar_init(txq_ctrl);
1316 dev->data->tx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STARTED;
1319 ret = rte_errno; /* Save rte_errno before cleanup. */
1320 mlx5_txq_release_devx_resources(txq_obj);
1321 rte_errno = ret; /* Restore rte_errno. */
1327 * Release an Tx DevX queue object.
1330 * DevX Tx queue object.
1333 mlx5_txq_devx_obj_release(struct mlx5_txq_obj *txq_obj)
1335 MLX5_ASSERT(txq_obj);
1336 if (txq_obj->txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) {
1338 claim_zero(mlx5_devx_cmd_destroy(txq_obj->tis));
1339 #if defined(HAVE_MLX5DV_DEVX_UAR_OFFSET) || !defined(HAVE_INFINIBAND_VERBS_H)
1341 mlx5_txq_release_devx_resources(txq_obj);
1346 struct mlx5_obj_ops devx_obj_ops = {
1347 .rxq_obj_modify_vlan_strip = mlx5_rxq_obj_modify_rq_vlan_strip,
1348 .rxq_obj_new = mlx5_rxq_devx_obj_new,
1349 .rxq_event_get = mlx5_rx_devx_get_event,
1350 .rxq_obj_modify = mlx5_devx_modify_rq,
1351 .rxq_obj_release = mlx5_rxq_devx_obj_release,
1352 .ind_table_new = mlx5_devx_ind_table_new,
1353 .ind_table_modify = mlx5_devx_ind_table_modify,
1354 .ind_table_destroy = mlx5_devx_ind_table_destroy,
1355 .hrxq_new = mlx5_devx_hrxq_new,
1356 .hrxq_destroy = mlx5_devx_tir_destroy,
1357 .hrxq_modify = mlx5_devx_hrxq_modify,
1358 .drop_action_create = mlx5_devx_drop_action_create,
1359 .drop_action_destroy = mlx5_devx_drop_action_destroy,
1360 .txq_obj_new = mlx5_txq_devx_obj_new,
1361 .txq_obj_modify = mlx5_devx_modify_sq,
1362 .txq_obj_release = mlx5_txq_devx_obj_release,