1 // SPDX-License-Identifier: BSD-3-Clause
2 /* Copyright 2018 Mellanox Technologies, Ltd */
4 #include <rte_flow_driver.h>
5 #include <rte_malloc.h>
13 * Allocate flow counters via devx interface.
16 * ibv contexts returned from mlx5dv_open_device.
18 * Pointer to counters properties structure to be filled by the routine.
20 * Bulk counter numbers in 128 counters units.
23 * Pointer to counter object on success, a negative value otherwise and
26 struct mlx5_devx_obj *
27 mlx5_devx_cmd_flow_counter_alloc(struct ibv_context *ctx, uint32_t bulk_n_128)
29 struct mlx5_devx_obj *dcs = rte_zmalloc("dcs", sizeof(*dcs), 0);
30 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0};
31 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0};
37 MLX5_SET(alloc_flow_counter_in, in, opcode,
38 MLX5_CMD_OP_ALLOC_FLOW_COUNTER);
39 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128);
40 dcs->obj = mlx5_glue->devx_obj_create(ctx, in,
41 sizeof(in), out, sizeof(out));
43 DRV_LOG(ERR, "Can't allocate counters - error %d", errno);
48 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id);
53 * Query flow counters values.
56 * devx object that was obtained from mlx5_devx_cmd_fc_alloc.
58 * Whether hardware should clear the counters after the query or not.
59 * @param[in] n_counters
60 * 0 in case of 1 counter to read, otherwise the counter number to read.
62 * The number of packets that matched the flow.
64 * The number of bytes that matched the flow.
66 * The mkey key for batch query.
68 * The address in the mkey range for batch query.
70 * The completion object for asynchronous batch query.
72 * The ID to be returned in the asynchronous batch query response.
75 * 0 on success, a negative value otherwise.
78 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
79 int clear, uint32_t n_counters,
80 uint64_t *pkts, uint64_t *bytes,
81 uint32_t mkey, void *addr,
82 struct mlx5dv_devx_cmd_comp *cmd_comp,
85 int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) +
86 MLX5_ST_SZ_BYTES(traffic_counter);
87 uint32_t out[out_len];
88 uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0};
92 MLX5_SET(query_flow_counter_in, in, opcode,
93 MLX5_CMD_OP_QUERY_FLOW_COUNTER);
94 MLX5_SET(query_flow_counter_in, in, op_mod, 0);
95 MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id);
96 MLX5_SET(query_flow_counter_in, in, clear, !!clear);
99 MLX5_SET(query_flow_counter_in, in, num_of_counters,
101 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1);
102 MLX5_SET(query_flow_counter_in, in, mkey, mkey);
103 MLX5_SET64(query_flow_counter_in, in, address,
104 (uint64_t)(uintptr_t)addr);
107 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out,
110 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in),
114 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc);
119 stats = MLX5_ADDR_OF(query_flow_counter_out,
120 out, flow_statistics);
121 *pkts = MLX5_GET64(traffic_counter, stats, packets);
122 *bytes = MLX5_GET64(traffic_counter, stats, octets);
131 * ibv contexts returned from mlx5dv_open_device.
133 * Attributes of the requested mkey.
136 * Pointer to Devx mkey on success, a negative value otherwise and rte_errno
139 struct mlx5_devx_obj *
140 mlx5_devx_cmd_mkey_create(struct ibv_context *ctx,
141 struct mlx5_devx_mkey_attr *attr)
143 uint32_t in[MLX5_ST_SZ_DW(create_mkey_in)] = {0};
144 uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0};
146 struct mlx5_devx_obj *mkey = rte_zmalloc("mkey", sizeof(*mkey), 0);
148 uint32_t translation_size;
154 pgsize = sysconf(_SC_PAGESIZE);
155 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16;
156 MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY);
157 MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
159 MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id);
160 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
161 MLX5_SET(mkc, mkc, lw, 0x1);
162 MLX5_SET(mkc, mkc, lr, 0x1);
163 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
164 MLX5_SET(mkc, mkc, qpn, 0xffffff);
165 MLX5_SET(mkc, mkc, pd, attr->pd);
166 MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF);
167 MLX5_SET(mkc, mkc, translations_octword_size, translation_size);
168 MLX5_SET64(mkc, mkc, start_addr, attr->addr);
169 MLX5_SET64(mkc, mkc, len, attr->size);
170 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize));
171 mkey->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
174 DRV_LOG(ERR, "Can't create mkey - error %d", errno);
179 mkey->id = MLX5_GET(create_mkey_out, out, mkey_index);
180 mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF);
185 * Get status of devx command response.
186 * Mainly used for asynchronous commands.
189 * The out response buffer.
192 * 0 on success, non-zero value otherwise.
195 mlx5_devx_get_out_command_status(void *out)
201 status = MLX5_GET(query_flow_counter_out, out, status);
203 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome);
205 DRV_LOG(ERR, "Bad devX status %x, syndrome = %x", status,
212 * Destroy any object allocated by a Devx API.
215 * Pointer to a general object.
218 * 0 on success, a negative value otherwise.
221 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj)
227 ret = mlx5_glue->devx_obj_destroy(obj->obj);
233 * Query NIC vport context.
234 * Fills minimal inline attribute.
237 * ibv contexts returned from mlx5dv_open_device.
241 * Attributes device values.
244 * 0 on success, a negative value otherwise.
247 mlx5_devx_cmd_query_nic_vport_context(struct ibv_context *ctx,
249 struct mlx5_hca_attr *attr)
251 uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0};
252 uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0};
254 int status, syndrome, rc;
256 /* Query NIC vport context to determine inline mode. */
257 MLX5_SET(query_nic_vport_context_in, in, opcode,
258 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT);
259 MLX5_SET(query_nic_vport_context_in, in, vport_number, vport);
261 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1);
262 rc = mlx5_glue->devx_general_cmd(ctx,
267 status = MLX5_GET(query_nic_vport_context_out, out, status);
268 syndrome = MLX5_GET(query_nic_vport_context_out, out, syndrome);
270 DRV_LOG(DEBUG, "Failed to query NIC vport context, "
271 "status %x, syndrome = %x",
275 vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out,
277 attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx,
278 min_wqe_inline_mode);
281 rc = (rc > 0) ? -rc : rc;
286 * Query HCA attributes.
287 * Using those attributes we can check on run time if the device
288 * is having the required capabilities.
291 * ibv contexts returned from mlx5dv_open_device.
293 * Attributes device values.
296 * 0 on success, a negative value otherwise.
299 mlx5_devx_cmd_query_hca_attr(struct ibv_context *ctx,
300 struct mlx5_hca_attr *attr)
302 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
303 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
305 int status, syndrome, rc;
307 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
308 MLX5_SET(query_hca_cap_in, in, op_mod,
309 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE |
310 MLX5_HCA_CAP_OPMOD_GET_CUR);
312 rc = mlx5_glue->devx_general_cmd(ctx,
313 in, sizeof(in), out, sizeof(out));
316 status = MLX5_GET(query_hca_cap_out, out, status);
317 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
319 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
320 "status %x, syndrome = %x",
324 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
325 attr->flow_counter_bulk_alloc_bitmap =
326 MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc);
327 attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr,
329 attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager);
330 attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin);
331 attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr,
332 log_max_hairpin_queues);
333 attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr,
334 log_max_hairpin_wq_data_sz);
335 attr->log_max_hairpin_num_packets = MLX5_GET
336 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz);
337 attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id);
338 attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr,
340 attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt);
341 attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr,
342 flex_parser_protocols);
343 if (!attr->eth_net_offloads)
346 /* Query HCA offloads for Ethernet protocol. */
347 memset(in, 0, sizeof(in));
348 memset(out, 0, sizeof(out));
349 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
350 MLX5_SET(query_hca_cap_in, in, op_mod,
351 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS |
352 MLX5_HCA_CAP_OPMOD_GET_CUR);
354 rc = mlx5_glue->devx_general_cmd(ctx,
358 attr->eth_net_offloads = 0;
361 status = MLX5_GET(query_hca_cap_out, out, status);
362 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
364 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
365 "status %x, syndrome = %x",
367 attr->eth_net_offloads = 0;
370 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
371 attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps,
372 hcattr, wqe_vlan_insert);
373 attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr,
375 attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps,
376 hcattr, tunnel_lro_gre);
377 attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps,
378 hcattr, tunnel_lro_vxlan);
379 attr->lro_max_msg_sz_mode = MLX5_GET
380 (per_protocol_networking_offload_caps,
381 hcattr, lro_max_msg_sz_mode);
382 for (int i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) {
383 attr->lro_timer_supported_periods[i] =
384 MLX5_GET(per_protocol_networking_offload_caps, hcattr,
385 lro_timer_supported_periods[i]);
387 attr->tunnel_stateless_geneve_rx =
388 MLX5_GET(per_protocol_networking_offload_caps,
389 hcattr, tunnel_stateless_geneve_rx);
390 attr->geneve_max_opt_len =
391 MLX5_GET(per_protocol_networking_offload_caps,
392 hcattr, max_geneve_opt_len);
393 attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps,
394 hcattr, wqe_inline_mode);
395 if (attr->wqe_inline_mode != MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
397 if (attr->eth_virt) {
398 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr);
406 rc = (rc > 0) ? -rc : rc;
411 * Query TIS transport domain from QP verbs object using DevX API.
414 * Pointer to verbs QP returned by ibv_create_qp .
416 * TIS number of TIS to query.
418 * Pointer to TIS transport domain variable, to be set by the routine.
421 * 0 on success, a negative value otherwise.
424 mlx5_devx_cmd_qp_query_tis_td(struct ibv_qp *qp, uint32_t tis_num,
427 uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0};
428 uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0};
432 MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS);
433 MLX5_SET(query_tis_in, in, tisn, tis_num);
434 rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out));
436 DRV_LOG(ERR, "Failed to query QP using DevX");
439 tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context);
440 *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain);
445 * Fill WQ data for DevX API command.
446 * Utility function for use when creating DevX objects containing a WQ.
449 * Pointer to WQ context to fill with data.
450 * @param [in] wq_attr
451 * Pointer to WQ attributes structure to fill in WQ context.
454 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr)
456 MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type);
457 MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature);
458 MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode);
459 MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave);
460 MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge);
461 MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size);
462 MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset);
463 MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm);
464 MLX5_SET(wq, wq_ctx, pd, wq_attr->pd);
465 MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page);
466 MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr);
467 MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter);
468 MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter);
469 MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride);
470 MLX5_SET(wq, wq_ctx, log_wq_pg_sz, wq_attr->log_wq_pg_sz);
471 MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz);
472 MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid);
473 MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid);
474 MLX5_SET(wq, wq_ctx, log_hairpin_num_packets,
475 wq_attr->log_hairpin_num_packets);
476 MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz);
477 MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides,
478 wq_attr->single_wqe_log_num_of_strides);
479 MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en);
480 MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes,
481 wq_attr->single_stride_log_num_of_bytes);
482 MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id);
483 MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id);
484 MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset);
488 * Create RQ using DevX API.
491 * ibv_context returned from mlx5dv_open_device.
492 * @param [in] rq_attr
493 * Pointer to create RQ attributes structure.
495 * CPU socket ID for allocations.
498 * The DevX object created, NULL otherwise and rte_errno is set.
500 struct mlx5_devx_obj *
501 mlx5_devx_cmd_create_rq(struct ibv_context *ctx,
502 struct mlx5_devx_create_rq_attr *rq_attr,
505 uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0};
506 uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0};
507 void *rq_ctx, *wq_ctx;
508 struct mlx5_devx_wq_attr *wq_attr;
509 struct mlx5_devx_obj *rq = NULL;
511 rq = rte_calloc_socket(__func__, 1, sizeof(*rq), 0, socket);
513 DRV_LOG(ERR, "Failed to allocate RQ data");
517 MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ);
518 rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx);
519 MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky);
520 MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en);
521 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
522 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
523 MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type);
524 MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
525 MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en);
526 MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin);
527 MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index);
528 MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn);
529 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
530 MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn);
531 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
532 wq_attr = &rq_attr->wq_attr;
533 devx_cmd_fill_wq_data(wq_ctx, wq_attr);
534 rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
537 DRV_LOG(ERR, "Failed to create RQ using DevX");
542 rq->id = MLX5_GET(create_rq_out, out, rqn);
547 * Modify RQ using DevX API.
550 * Pointer to RQ object structure.
551 * @param [in] rq_attr
552 * Pointer to modify RQ attributes structure.
555 * 0 on success, a negative errno value otherwise and rte_errno is set.
558 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
559 struct mlx5_devx_modify_rq_attr *rq_attr)
561 uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0};
562 uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0};
563 void *rq_ctx, *wq_ctx;
566 MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ);
567 MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state);
568 MLX5_SET(modify_rq_in, in, rqn, rq->id);
569 MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask);
570 rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
571 MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
572 if (rq_attr->modify_bitmask &
573 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS)
574 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
575 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD)
576 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
577 if (rq_attr->modify_bitmask &
578 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID)
579 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
580 MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq);
581 MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca);
582 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) {
583 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
584 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm);
586 ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in),
589 DRV_LOG(ERR, "Failed to modify RQ using DevX");
597 * Create TIR using DevX API.
600 * ibv_context returned from mlx5dv_open_device.
601 * @param [in] tir_attr
602 * Pointer to TIR attributes structure.
605 * The DevX object created, NULL otherwise and rte_errno is set.
607 struct mlx5_devx_obj *
608 mlx5_devx_cmd_create_tir(struct ibv_context *ctx,
609 struct mlx5_devx_tir_attr *tir_attr)
611 uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
612 uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0};
613 void *tir_ctx, *outer, *inner;
614 struct mlx5_devx_obj *tir = NULL;
617 tir = rte_calloc(__func__, 1, sizeof(*tir), 0);
619 DRV_LOG(ERR, "Failed to allocate TIR data");
623 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
624 tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx);
625 MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type);
626 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
627 tir_attr->lro_timeout_period_usecs);
628 MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask);
629 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz);
630 MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn);
631 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric);
632 MLX5_SET(tirc, tir_ctx, tunneled_offload_en,
633 tir_attr->tunneled_offload_en);
634 MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table);
635 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
636 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
637 MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain);
638 for (i = 0; i < 10; i++) {
639 MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i],
640 tir_attr->rx_hash_toeplitz_key[i]);
642 outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer);
643 MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
644 tir_attr->rx_hash_field_selector_outer.l3_prot_type);
645 MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
646 tir_attr->rx_hash_field_selector_outer.l4_prot_type);
647 MLX5_SET(rx_hash_field_select, outer, selected_fields,
648 tir_attr->rx_hash_field_selector_outer.selected_fields);
649 inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner);
650 MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
651 tir_attr->rx_hash_field_selector_inner.l3_prot_type);
652 MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
653 tir_attr->rx_hash_field_selector_inner.l4_prot_type);
654 MLX5_SET(rx_hash_field_select, inner, selected_fields,
655 tir_attr->rx_hash_field_selector_inner.selected_fields);
656 tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
659 DRV_LOG(ERR, "Failed to create TIR using DevX");
664 tir->id = MLX5_GET(create_tir_out, out, tirn);
669 * Create RQT using DevX API.
672 * ibv_context returned from mlx5dv_open_device.
673 * @param [in] rqt_attr
674 * Pointer to RQT attributes structure.
677 * The DevX object created, NULL otherwise and rte_errno is set.
679 struct mlx5_devx_obj *
680 mlx5_devx_cmd_create_rqt(struct ibv_context *ctx,
681 struct mlx5_devx_rqt_attr *rqt_attr)
684 uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) +
685 rqt_attr->rqt_actual_size * sizeof(uint32_t);
686 uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
688 struct mlx5_devx_obj *rqt = NULL;
691 in = rte_calloc(__func__, 1, inlen, 0);
693 DRV_LOG(ERR, "Failed to allocate RQT IN data");
697 rqt = rte_calloc(__func__, 1, sizeof(*rqt), 0);
699 DRV_LOG(ERR, "Failed to allocate RQT data");
704 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
705 rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
706 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size);
707 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
708 for (i = 0; i < rqt_attr->rqt_actual_size; i++)
709 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
710 rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out));
713 DRV_LOG(ERR, "Failed to create RQT using DevX");
718 rqt->id = MLX5_GET(create_rqt_out, out, rqtn);
723 * Create SQ using DevX API.
726 * ibv_context returned from mlx5dv_open_device.
727 * @param [in] sq_attr
728 * Pointer to SQ attributes structure.
730 * CPU socket ID for allocations.
733 * The DevX object created, NULL otherwise and rte_errno is set.
735 struct mlx5_devx_obj *
736 mlx5_devx_cmd_create_sq(struct ibv_context *ctx,
737 struct mlx5_devx_create_sq_attr *sq_attr)
739 uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0};
740 uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0};
743 struct mlx5_devx_wq_attr *wq_attr;
744 struct mlx5_devx_obj *sq = NULL;
746 sq = rte_calloc(__func__, 1, sizeof(*sq), 0);
748 DRV_LOG(ERR, "Failed to allocate SQ data");
752 MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ);
753 sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx);
754 MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky);
755 MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master);
756 MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre);
757 MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en);
758 MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe,
759 sq_attr->flush_in_error_en);
760 MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode,
761 sq_attr->min_wqe_inline_mode);
762 MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
763 MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr);
764 MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp);
765 MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin);
766 MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index);
767 MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn);
768 MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index,
769 sq_attr->packet_pacing_rate_limit_index);
770 MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz);
771 MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num);
772 wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq);
773 wq_attr = &sq_attr->wq_attr;
774 devx_cmd_fill_wq_data(wq_ctx, wq_attr);
775 sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
778 DRV_LOG(ERR, "Failed to create SQ using DevX");
783 sq->id = MLX5_GET(create_sq_out, out, sqn);
788 * Modify SQ using DevX API.
791 * Pointer to SQ object structure.
792 * @param [in] sq_attr
793 * Pointer to SQ attributes structure.
796 * 0 on success, a negative errno value otherwise and rte_errno is set.
799 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq,
800 struct mlx5_devx_modify_sq_attr *sq_attr)
802 uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0};
803 uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0};
807 MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ);
808 MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state);
809 MLX5_SET(modify_sq_in, in, sqn, sq->id);
810 sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx);
811 MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
812 MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq);
813 MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca);
814 ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in),
817 DRV_LOG(ERR, "Failed to modify SQ using DevX");
825 * Create TIS using DevX API.
828 * ibv_context returned from mlx5dv_open_device.
829 * @param [in] tis_attr
830 * Pointer to TIS attributes structure.
833 * The DevX object created, NULL otherwise and rte_errno is set.
835 struct mlx5_devx_obj *
836 mlx5_devx_cmd_create_tis(struct ibv_context *ctx,
837 struct mlx5_devx_tis_attr *tis_attr)
839 uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
840 uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0};
841 struct mlx5_devx_obj *tis = NULL;
844 tis = rte_calloc(__func__, 1, sizeof(*tis), 0);
846 DRV_LOG(ERR, "Failed to allocate TIS object");
850 MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS);
851 tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx);
852 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity,
853 tis_attr->strict_lag_tx_port_affinity);
854 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity,
855 tis_attr->strict_lag_tx_port_affinity);
856 MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio);
857 MLX5_SET(tisc, tis_ctx, transport_domain,
858 tis_attr->transport_domain);
859 tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
862 DRV_LOG(ERR, "Failed to create TIS using DevX");
867 tis->id = MLX5_GET(create_tis_out, out, tisn);
872 * Create transport domain using DevX API.
875 * ibv_context returned from mlx5dv_open_device.
878 * The DevX object created, NULL otherwise and rte_errno is set.
880 struct mlx5_devx_obj *
881 mlx5_devx_cmd_create_td(struct ibv_context *ctx)
883 uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0};
884 uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0};
885 struct mlx5_devx_obj *td = NULL;
887 td = rte_calloc(__func__, 1, sizeof(*td), 0);
889 DRV_LOG(ERR, "Failed to allocate TD object");
893 MLX5_SET(alloc_transport_domain_in, in, opcode,
894 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN);
895 td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
898 DRV_LOG(ERR, "Failed to create TIS using DevX");
903 td->id = MLX5_GET(alloc_transport_domain_out, out,