1 // SPDX-License-Identifier: BSD-3-Clause
2 /* Copyright 2018 Mellanox Technologies, Ltd */
4 #include <rte_flow_driver.h>
5 #include <rte_malloc.h>
13 * Allocate flow counters via devx interface.
16 * ibv contexts returned from mlx5dv_open_device.
18 * Pointer to counters properties structure to be filled by the routine.
20 * Bulk counter numbers in 128 counters units.
23 * Pointer to counter object on success, a negative value otherwise and
26 struct mlx5_devx_obj *
27 mlx5_devx_cmd_flow_counter_alloc(struct ibv_context *ctx, uint32_t bulk_n_128)
29 struct mlx5_devx_obj *dcs = rte_zmalloc("dcs", sizeof(*dcs), 0);
30 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0};
31 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0};
37 MLX5_SET(alloc_flow_counter_in, in, opcode,
38 MLX5_CMD_OP_ALLOC_FLOW_COUNTER);
39 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128);
40 dcs->obj = mlx5_glue->devx_obj_create(ctx, in,
41 sizeof(in), out, sizeof(out));
43 DRV_LOG(ERR, "Can't allocate counters - error %d", errno);
48 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id);
53 * Query flow counters values.
56 * devx object that was obtained from mlx5_devx_cmd_fc_alloc.
58 * Whether hardware should clear the counters after the query or not.
59 * @param[in] n_counters
60 * 0 in case of 1 counter to read, otherwise the counter number to read.
62 * The number of packets that matched the flow.
64 * The number of bytes that matched the flow.
66 * The mkey key for batch query.
68 * The address in the mkey range for batch query.
70 * The completion object for asynchronous batch query.
72 * The ID to be returned in the asynchronous batch query response.
75 * 0 on success, a negative value otherwise.
78 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
79 int clear, uint32_t n_counters,
80 uint64_t *pkts, uint64_t *bytes,
81 uint32_t mkey, void *addr,
82 struct mlx5dv_devx_cmd_comp *cmd_comp,
85 int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) +
86 MLX5_ST_SZ_BYTES(traffic_counter);
87 uint32_t out[out_len];
88 uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0};
92 MLX5_SET(query_flow_counter_in, in, opcode,
93 MLX5_CMD_OP_QUERY_FLOW_COUNTER);
94 MLX5_SET(query_flow_counter_in, in, op_mod, 0);
95 MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id);
96 MLX5_SET(query_flow_counter_in, in, clear, !!clear);
99 MLX5_SET(query_flow_counter_in, in, num_of_counters,
101 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1);
102 MLX5_SET(query_flow_counter_in, in, mkey, mkey);
103 MLX5_SET64(query_flow_counter_in, in, address,
104 (uint64_t)(uintptr_t)addr);
107 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out,
110 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in),
114 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc);
119 stats = MLX5_ADDR_OF(query_flow_counter_out,
120 out, flow_statistics);
121 *pkts = MLX5_GET64(traffic_counter, stats, packets);
122 *bytes = MLX5_GET64(traffic_counter, stats, octets);
131 * ibv contexts returned from mlx5dv_open_device.
133 * Attributes of the requested mkey.
136 * Pointer to Devx mkey on success, a negative value otherwise and rte_errno
139 struct mlx5_devx_obj *
140 mlx5_devx_cmd_mkey_create(struct ibv_context *ctx,
141 struct mlx5_devx_mkey_attr *attr)
143 uint32_t in[MLX5_ST_SZ_DW(create_mkey_in)] = {0};
144 uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0};
146 struct mlx5_devx_obj *mkey = rte_zmalloc("mkey", sizeof(*mkey), 0);
148 uint32_t translation_size;
154 pgsize = sysconf(_SC_PAGESIZE);
155 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16;
156 MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY);
157 MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
159 MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id);
160 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
161 MLX5_SET(mkc, mkc, lw, 0x1);
162 MLX5_SET(mkc, mkc, lr, 0x1);
163 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
164 MLX5_SET(mkc, mkc, qpn, 0xffffff);
165 MLX5_SET(mkc, mkc, pd, attr->pd);
166 MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF);
167 MLX5_SET(mkc, mkc, translations_octword_size, translation_size);
168 MLX5_SET64(mkc, mkc, start_addr, attr->addr);
169 MLX5_SET64(mkc, mkc, len, attr->size);
170 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize));
171 mkey->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
174 DRV_LOG(ERR, "Can't create mkey - error %d", errno);
179 mkey->id = MLX5_GET(create_mkey_out, out, mkey_index);
180 mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF);
185 * Get status of devx command response.
186 * Mainly used for asynchronous commands.
189 * The out response buffer.
192 * 0 on success, non-zero value otherwise.
195 mlx5_devx_get_out_command_status(void *out)
201 status = MLX5_GET(query_flow_counter_out, out, status);
203 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome);
205 DRV_LOG(ERR, "Bad devX status %x, syndrome = %x", status,
212 * Destroy any object allocated by a Devx API.
215 * Pointer to a general object.
218 * 0 on success, a negative value otherwise.
221 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj)
227 ret = mlx5_glue->devx_obj_destroy(obj->obj);
233 * Query NIC vport context.
234 * Fills minimal inline attribute.
237 * ibv contexts returned from mlx5dv_open_device.
241 * Attributes device values.
244 * 0 on success, a negative value otherwise.
247 mlx5_devx_cmd_query_nic_vport_context(struct ibv_context *ctx,
249 struct mlx5_hca_attr *attr)
251 uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0};
252 uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0};
254 int status, syndrome, rc;
256 /* Query NIC vport context to determine inline mode. */
257 MLX5_SET(query_nic_vport_context_in, in, opcode,
258 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT);
259 MLX5_SET(query_nic_vport_context_in, in, vport_number, vport);
261 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1);
262 rc = mlx5_glue->devx_general_cmd(ctx,
267 status = MLX5_GET(query_nic_vport_context_out, out, status);
268 syndrome = MLX5_GET(query_nic_vport_context_out, out, syndrome);
270 DRV_LOG(DEBUG, "Failed to query NIC vport context, "
271 "status %x, syndrome = %x",
275 vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out,
277 attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx,
278 min_wqe_inline_mode);
281 rc = (rc > 0) ? -rc : rc;
286 * Query HCA attributes.
287 * Using those attributes we can check on run time if the device
288 * is having the required capabilities.
291 * ibv contexts returned from mlx5dv_open_device.
293 * Attributes device values.
296 * 0 on success, a negative value otherwise.
299 mlx5_devx_cmd_query_hca_attr(struct ibv_context *ctx,
300 struct mlx5_hca_attr *attr)
302 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
303 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
305 int status, syndrome, rc;
307 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
308 MLX5_SET(query_hca_cap_in, in, op_mod,
309 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE |
310 MLX5_HCA_CAP_OPMOD_GET_CUR);
312 rc = mlx5_glue->devx_general_cmd(ctx,
313 in, sizeof(in), out, sizeof(out));
316 status = MLX5_GET(query_hca_cap_out, out, status);
317 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
319 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
320 "status %x, syndrome = %x",
324 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
325 attr->flow_counter_bulk_alloc_bitmap =
326 MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc);
327 attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr,
329 attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager);
330 attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin);
331 attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr,
332 log_max_hairpin_queues);
333 attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr,
334 log_max_hairpin_wq_data_sz);
335 attr->log_max_hairpin_num_packets = MLX5_GET
336 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz);
337 attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id);
338 attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos);
340 MLX5_SET(query_hca_cap_in, in, op_mod,
341 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |
342 MLX5_HCA_CAP_OPMOD_GET_CUR);
343 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in),
348 DRV_LOG(DEBUG, "Failed to query devx QOS capabilities,"
349 " status %x, syndrome = %x",
353 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
354 attr->qos.srtcm_sup =
355 MLX5_GET(qos_cap, hcattr, flow_meter_srtcm);
356 attr->qos.log_max_flow_meter =
357 MLX5_GET(qos_cap, hcattr, log_max_flow_meter);
358 attr->qos.flow_meter_reg_c_ids =
359 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id);
361 attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr,
363 attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt);
364 attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr,
365 flex_parser_protocols);
366 if (!attr->eth_net_offloads)
369 /* Query HCA offloads for Ethernet protocol. */
370 memset(in, 0, sizeof(in));
371 memset(out, 0, sizeof(out));
372 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
373 MLX5_SET(query_hca_cap_in, in, op_mod,
374 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS |
375 MLX5_HCA_CAP_OPMOD_GET_CUR);
377 rc = mlx5_glue->devx_general_cmd(ctx,
381 attr->eth_net_offloads = 0;
384 status = MLX5_GET(query_hca_cap_out, out, status);
385 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
387 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
388 "status %x, syndrome = %x",
390 attr->eth_net_offloads = 0;
393 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
394 attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps,
395 hcattr, wqe_vlan_insert);
396 attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr,
398 attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps,
399 hcattr, tunnel_lro_gre);
400 attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps,
401 hcattr, tunnel_lro_vxlan);
402 attr->lro_max_msg_sz_mode = MLX5_GET
403 (per_protocol_networking_offload_caps,
404 hcattr, lro_max_msg_sz_mode);
405 for (int i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) {
406 attr->lro_timer_supported_periods[i] =
407 MLX5_GET(per_protocol_networking_offload_caps, hcattr,
408 lro_timer_supported_periods[i]);
410 attr->tunnel_stateless_geneve_rx =
411 MLX5_GET(per_protocol_networking_offload_caps,
412 hcattr, tunnel_stateless_geneve_rx);
413 attr->geneve_max_opt_len =
414 MLX5_GET(per_protocol_networking_offload_caps,
415 hcattr, max_geneve_opt_len);
416 attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps,
417 hcattr, wqe_inline_mode);
418 if (attr->wqe_inline_mode != MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
420 if (attr->eth_virt) {
421 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr);
429 rc = (rc > 0) ? -rc : rc;
434 * Query TIS transport domain from QP verbs object using DevX API.
437 * Pointer to verbs QP returned by ibv_create_qp .
439 * TIS number of TIS to query.
441 * Pointer to TIS transport domain variable, to be set by the routine.
444 * 0 on success, a negative value otherwise.
447 mlx5_devx_cmd_qp_query_tis_td(struct ibv_qp *qp, uint32_t tis_num,
450 uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0};
451 uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0};
455 MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS);
456 MLX5_SET(query_tis_in, in, tisn, tis_num);
457 rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out));
459 DRV_LOG(ERR, "Failed to query QP using DevX");
462 tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context);
463 *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain);
468 * Fill WQ data for DevX API command.
469 * Utility function for use when creating DevX objects containing a WQ.
472 * Pointer to WQ context to fill with data.
473 * @param [in] wq_attr
474 * Pointer to WQ attributes structure to fill in WQ context.
477 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr)
479 MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type);
480 MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature);
481 MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode);
482 MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave);
483 MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge);
484 MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size);
485 MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset);
486 MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm);
487 MLX5_SET(wq, wq_ctx, pd, wq_attr->pd);
488 MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page);
489 MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr);
490 MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter);
491 MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter);
492 MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride);
493 MLX5_SET(wq, wq_ctx, log_wq_pg_sz, wq_attr->log_wq_pg_sz);
494 MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz);
495 MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid);
496 MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid);
497 MLX5_SET(wq, wq_ctx, log_hairpin_num_packets,
498 wq_attr->log_hairpin_num_packets);
499 MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz);
500 MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides,
501 wq_attr->single_wqe_log_num_of_strides);
502 MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en);
503 MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes,
504 wq_attr->single_stride_log_num_of_bytes);
505 MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id);
506 MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id);
507 MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset);
511 * Create RQ using DevX API.
514 * ibv_context returned from mlx5dv_open_device.
515 * @param [in] rq_attr
516 * Pointer to create RQ attributes structure.
518 * CPU socket ID for allocations.
521 * The DevX object created, NULL otherwise and rte_errno is set.
523 struct mlx5_devx_obj *
524 mlx5_devx_cmd_create_rq(struct ibv_context *ctx,
525 struct mlx5_devx_create_rq_attr *rq_attr,
528 uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0};
529 uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0};
530 void *rq_ctx, *wq_ctx;
531 struct mlx5_devx_wq_attr *wq_attr;
532 struct mlx5_devx_obj *rq = NULL;
534 rq = rte_calloc_socket(__func__, 1, sizeof(*rq), 0, socket);
536 DRV_LOG(ERR, "Failed to allocate RQ data");
540 MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ);
541 rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx);
542 MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky);
543 MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en);
544 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
545 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
546 MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type);
547 MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
548 MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en);
549 MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin);
550 MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index);
551 MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn);
552 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
553 MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn);
554 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
555 wq_attr = &rq_attr->wq_attr;
556 devx_cmd_fill_wq_data(wq_ctx, wq_attr);
557 rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
560 DRV_LOG(ERR, "Failed to create RQ using DevX");
565 rq->id = MLX5_GET(create_rq_out, out, rqn);
570 * Modify RQ using DevX API.
573 * Pointer to RQ object structure.
574 * @param [in] rq_attr
575 * Pointer to modify RQ attributes structure.
578 * 0 on success, a negative errno value otherwise and rte_errno is set.
581 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
582 struct mlx5_devx_modify_rq_attr *rq_attr)
584 uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0};
585 uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0};
586 void *rq_ctx, *wq_ctx;
589 MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ);
590 MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state);
591 MLX5_SET(modify_rq_in, in, rqn, rq->id);
592 MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask);
593 rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
594 MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
595 if (rq_attr->modify_bitmask &
596 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS)
597 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
598 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD)
599 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
600 if (rq_attr->modify_bitmask &
601 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID)
602 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
603 MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq);
604 MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca);
605 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) {
606 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
607 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm);
609 ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in),
612 DRV_LOG(ERR, "Failed to modify RQ using DevX");
620 * Create TIR using DevX API.
623 * ibv_context returned from mlx5dv_open_device.
624 * @param [in] tir_attr
625 * Pointer to TIR attributes structure.
628 * The DevX object created, NULL otherwise and rte_errno is set.
630 struct mlx5_devx_obj *
631 mlx5_devx_cmd_create_tir(struct ibv_context *ctx,
632 struct mlx5_devx_tir_attr *tir_attr)
634 uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
635 uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0};
636 void *tir_ctx, *outer, *inner;
637 struct mlx5_devx_obj *tir = NULL;
640 tir = rte_calloc(__func__, 1, sizeof(*tir), 0);
642 DRV_LOG(ERR, "Failed to allocate TIR data");
646 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
647 tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx);
648 MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type);
649 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
650 tir_attr->lro_timeout_period_usecs);
651 MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask);
652 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz);
653 MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn);
654 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric);
655 MLX5_SET(tirc, tir_ctx, tunneled_offload_en,
656 tir_attr->tunneled_offload_en);
657 MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table);
658 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
659 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
660 MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain);
661 for (i = 0; i < 10; i++) {
662 MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i],
663 tir_attr->rx_hash_toeplitz_key[i]);
665 outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer);
666 MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
667 tir_attr->rx_hash_field_selector_outer.l3_prot_type);
668 MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
669 tir_attr->rx_hash_field_selector_outer.l4_prot_type);
670 MLX5_SET(rx_hash_field_select, outer, selected_fields,
671 tir_attr->rx_hash_field_selector_outer.selected_fields);
672 inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner);
673 MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
674 tir_attr->rx_hash_field_selector_inner.l3_prot_type);
675 MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
676 tir_attr->rx_hash_field_selector_inner.l4_prot_type);
677 MLX5_SET(rx_hash_field_select, inner, selected_fields,
678 tir_attr->rx_hash_field_selector_inner.selected_fields);
679 tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
682 DRV_LOG(ERR, "Failed to create TIR using DevX");
687 tir->id = MLX5_GET(create_tir_out, out, tirn);
692 * Create RQT using DevX API.
695 * ibv_context returned from mlx5dv_open_device.
696 * @param [in] rqt_attr
697 * Pointer to RQT attributes structure.
700 * The DevX object created, NULL otherwise and rte_errno is set.
702 struct mlx5_devx_obj *
703 mlx5_devx_cmd_create_rqt(struct ibv_context *ctx,
704 struct mlx5_devx_rqt_attr *rqt_attr)
707 uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) +
708 rqt_attr->rqt_actual_size * sizeof(uint32_t);
709 uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
711 struct mlx5_devx_obj *rqt = NULL;
714 in = rte_calloc(__func__, 1, inlen, 0);
716 DRV_LOG(ERR, "Failed to allocate RQT IN data");
720 rqt = rte_calloc(__func__, 1, sizeof(*rqt), 0);
722 DRV_LOG(ERR, "Failed to allocate RQT data");
727 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
728 rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
729 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size);
730 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
731 for (i = 0; i < rqt_attr->rqt_actual_size; i++)
732 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
733 rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out));
736 DRV_LOG(ERR, "Failed to create RQT using DevX");
741 rqt->id = MLX5_GET(create_rqt_out, out, rqtn);
746 * Create SQ using DevX API.
749 * ibv_context returned from mlx5dv_open_device.
750 * @param [in] sq_attr
751 * Pointer to SQ attributes structure.
753 * CPU socket ID for allocations.
756 * The DevX object created, NULL otherwise and rte_errno is set.
758 struct mlx5_devx_obj *
759 mlx5_devx_cmd_create_sq(struct ibv_context *ctx,
760 struct mlx5_devx_create_sq_attr *sq_attr)
762 uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0};
763 uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0};
766 struct mlx5_devx_wq_attr *wq_attr;
767 struct mlx5_devx_obj *sq = NULL;
769 sq = rte_calloc(__func__, 1, sizeof(*sq), 0);
771 DRV_LOG(ERR, "Failed to allocate SQ data");
775 MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ);
776 sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx);
777 MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky);
778 MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master);
779 MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre);
780 MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en);
781 MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe,
782 sq_attr->flush_in_error_en);
783 MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode,
784 sq_attr->min_wqe_inline_mode);
785 MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
786 MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr);
787 MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp);
788 MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin);
789 MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index);
790 MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn);
791 MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index,
792 sq_attr->packet_pacing_rate_limit_index);
793 MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz);
794 MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num);
795 wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq);
796 wq_attr = &sq_attr->wq_attr;
797 devx_cmd_fill_wq_data(wq_ctx, wq_attr);
798 sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
801 DRV_LOG(ERR, "Failed to create SQ using DevX");
806 sq->id = MLX5_GET(create_sq_out, out, sqn);
811 * Modify SQ using DevX API.
814 * Pointer to SQ object structure.
815 * @param [in] sq_attr
816 * Pointer to SQ attributes structure.
819 * 0 on success, a negative errno value otherwise and rte_errno is set.
822 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq,
823 struct mlx5_devx_modify_sq_attr *sq_attr)
825 uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0};
826 uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0};
830 MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ);
831 MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state);
832 MLX5_SET(modify_sq_in, in, sqn, sq->id);
833 sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx);
834 MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
835 MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq);
836 MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca);
837 ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in),
840 DRV_LOG(ERR, "Failed to modify SQ using DevX");
848 * Create TIS using DevX API.
851 * ibv_context returned from mlx5dv_open_device.
852 * @param [in] tis_attr
853 * Pointer to TIS attributes structure.
856 * The DevX object created, NULL otherwise and rte_errno is set.
858 struct mlx5_devx_obj *
859 mlx5_devx_cmd_create_tis(struct ibv_context *ctx,
860 struct mlx5_devx_tis_attr *tis_attr)
862 uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
863 uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0};
864 struct mlx5_devx_obj *tis = NULL;
867 tis = rte_calloc(__func__, 1, sizeof(*tis), 0);
869 DRV_LOG(ERR, "Failed to allocate TIS object");
873 MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS);
874 tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx);
875 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity,
876 tis_attr->strict_lag_tx_port_affinity);
877 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity,
878 tis_attr->strict_lag_tx_port_affinity);
879 MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio);
880 MLX5_SET(tisc, tis_ctx, transport_domain,
881 tis_attr->transport_domain);
882 tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
885 DRV_LOG(ERR, "Failed to create TIS using DevX");
890 tis->id = MLX5_GET(create_tis_out, out, tisn);
895 * Create transport domain using DevX API.
898 * ibv_context returned from mlx5dv_open_device.
901 * The DevX object created, NULL otherwise and rte_errno is set.
903 struct mlx5_devx_obj *
904 mlx5_devx_cmd_create_td(struct ibv_context *ctx)
906 uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0};
907 uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0};
908 struct mlx5_devx_obj *td = NULL;
910 td = rte_calloc(__func__, 1, sizeof(*td), 0);
912 DRV_LOG(ERR, "Failed to allocate TD object");
916 MLX5_SET(alloc_transport_domain_in, in, opcode,
917 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN);
918 td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
921 DRV_LOG(ERR, "Failed to create TIS using DevX");
926 td->id = MLX5_GET(alloc_transport_domain_out, out,