1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
13 #include <ethdev_driver.h>
14 #include <rte_bus_pci.h>
16 #include <rte_common.h>
17 #include <rte_interrupts.h>
18 #include <rte_malloc.h>
19 #include <rte_string_fns.h>
20 #include <rte_rwlock.h>
21 #include <rte_cycles.h>
23 #include <mlx5_malloc.h>
25 #include "mlx5_rxtx.h"
28 #include "mlx5_autoconf.h"
29 #include "mlx5_devx.h"
32 * Get the interface index from device name.
35 * Pointer to Ethernet device.
38 * Nonzero interface index on success, zero otherwise and rte_errno is set.
41 mlx5_ifindex(const struct rte_eth_dev *dev)
43 struct mlx5_priv *priv = dev->data->dev_private;
47 MLX5_ASSERT(priv->if_index);
48 if (priv->master && priv->sh->bond.ifindex > 0)
49 ifindex = priv->sh->bond.ifindex;
51 ifindex = priv->if_index;
58 * DPDK callback for Ethernet device configuration.
61 * Pointer to Ethernet device structure.
64 * 0 on success, a negative errno value otherwise and rte_errno is set.
67 mlx5_dev_configure(struct rte_eth_dev *dev)
69 struct mlx5_priv *priv = dev->data->dev_private;
70 unsigned int rxqs_n = dev->data->nb_rx_queues;
71 unsigned int txqs_n = dev->data->nb_tx_queues;
72 const uint8_t use_app_rss_key =
73 !!dev->data->dev_conf.rx_adv_conf.rss_conf.rss_key;
76 if (use_app_rss_key &&
77 (dev->data->dev_conf.rx_adv_conf.rss_conf.rss_key_len !=
78 MLX5_RSS_HASH_KEY_LEN)) {
79 DRV_LOG(ERR, "port %u RSS key len must be %s Bytes long",
80 dev->data->port_id, RTE_STR(MLX5_RSS_HASH_KEY_LEN));
84 priv->rss_conf.rss_key =
85 mlx5_realloc(priv->rss_conf.rss_key, MLX5_MEM_RTE,
86 MLX5_RSS_HASH_KEY_LEN, 0, SOCKET_ID_ANY);
87 if (!priv->rss_conf.rss_key) {
88 DRV_LOG(ERR, "port %u cannot allocate RSS hash key memory (%u)",
89 dev->data->port_id, rxqs_n);
94 if ((dev->data->dev_conf.txmode.offloads &
95 RTE_ETH_TX_OFFLOAD_SEND_ON_TIMESTAMP) &&
96 rte_mbuf_dyn_tx_timestamp_register(NULL, NULL) != 0) {
97 DRV_LOG(ERR, "port %u cannot register Tx timestamp field/flag",
101 memcpy(priv->rss_conf.rss_key,
103 dev->data->dev_conf.rx_adv_conf.rss_conf.rss_key :
104 rss_hash_default_key,
105 MLX5_RSS_HASH_KEY_LEN);
106 priv->rss_conf.rss_key_len = MLX5_RSS_HASH_KEY_LEN;
107 priv->rss_conf.rss_hf = dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf;
108 priv->rxq_privs = mlx5_realloc(priv->rxq_privs,
109 MLX5_MEM_RTE | MLX5_MEM_ZERO,
110 sizeof(void *) * rxqs_n, 0,
112 if (priv->rxq_privs == NULL) {
113 DRV_LOG(ERR, "port %u cannot allocate rxq private data",
118 priv->txqs = (void *)dev->data->tx_queues;
119 if (txqs_n != priv->txqs_n) {
120 DRV_LOG(INFO, "port %u Tx queues number update: %u -> %u",
121 dev->data->port_id, priv->txqs_n, txqs_n);
122 priv->txqs_n = txqs_n;
124 if (rxqs_n > priv->sh->dev_cap.ind_table_max_size) {
125 DRV_LOG(ERR, "port %u cannot handle this many Rx queues (%u)",
126 dev->data->port_id, rxqs_n);
130 if (rxqs_n != priv->rxqs_n) {
131 DRV_LOG(INFO, "port %u Rx queues number update: %u -> %u",
132 dev->data->port_id, priv->rxqs_n, rxqs_n);
133 priv->rxqs_n = rxqs_n;
135 priv->skip_default_rss_reta = 0;
136 ret = mlx5_proc_priv_init(dev);
143 * Configure default RSS reta.
146 * Pointer to Ethernet device structure.
149 * 0 on success, a negative errno value otherwise and rte_errno is set.
152 mlx5_dev_configure_rss_reta(struct rte_eth_dev *dev)
154 struct mlx5_priv *priv = dev->data->dev_private;
155 unsigned int rxqs_n = dev->data->nb_rx_queues;
158 unsigned int reta_idx_n;
160 unsigned int *rss_queue_arr = NULL;
161 unsigned int rss_queue_n = 0;
163 if (priv->skip_default_rss_reta)
165 rss_queue_arr = mlx5_malloc(0, rxqs_n * sizeof(unsigned int), 0,
167 if (!rss_queue_arr) {
168 DRV_LOG(ERR, "port %u cannot allocate RSS queue list (%u)",
169 dev->data->port_id, rxqs_n);
173 for (i = 0, j = 0; i < rxqs_n; i++) {
174 struct mlx5_rxq_ctrl *rxq_ctrl = mlx5_rxq_ctrl_get(dev, i);
176 if (rxq_ctrl && rxq_ctrl->type == MLX5_RXQ_TYPE_STANDARD)
177 rss_queue_arr[j++] = i;
180 if (rss_queue_n > priv->sh->dev_cap.ind_table_max_size) {
181 DRV_LOG(ERR, "port %u cannot handle this many Rx queues (%u)",
182 dev->data->port_id, rss_queue_n);
184 mlx5_free(rss_queue_arr);
187 DRV_LOG(INFO, "port %u Rx queues number update: %u -> %u",
188 dev->data->port_id, priv->rxqs_n, rxqs_n);
189 priv->rxqs_n = rxqs_n;
191 * If the requested number of RX queues is not a power of two,
192 * use the maximum indirection table size for better balancing.
193 * The result is always rounded to the next power of two.
195 reta_idx_n = (1 << log2above((rss_queue_n & (rss_queue_n - 1)) ?
196 priv->sh->dev_cap.ind_table_max_size :
198 ret = mlx5_rss_reta_index_resize(dev, reta_idx_n);
200 mlx5_free(rss_queue_arr);
204 * When the number of RX queues is not a power of two,
205 * the remaining table entries are padded with reused WQs
206 * and hashes are not spread uniformly.
208 for (i = 0, j = 0; (i != reta_idx_n); ++i) {
209 (*priv->reta_idx)[i] = rss_queue_arr[j];
210 if (++j == rss_queue_n)
213 mlx5_free(rss_queue_arr);
218 * Sets default tuning parameters.
221 * Pointer to Ethernet device.
223 * Info structure output buffer.
226 mlx5_set_default_params(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)
228 struct mlx5_priv *priv = dev->data->dev_private;
230 /* Minimum CPU utilization. */
231 info->default_rxportconf.ring_size = 256;
232 info->default_txportconf.ring_size = 256;
233 info->default_rxportconf.burst_size = MLX5_RX_DEFAULT_BURST;
234 info->default_txportconf.burst_size = MLX5_TX_DEFAULT_BURST;
235 if ((priv->link_speed_capa & RTE_ETH_LINK_SPEED_200G) |
236 (priv->link_speed_capa & RTE_ETH_LINK_SPEED_100G)) {
237 info->default_rxportconf.nb_queues = 16;
238 info->default_txportconf.nb_queues = 16;
239 if (dev->data->nb_rx_queues > 2 ||
240 dev->data->nb_tx_queues > 2) {
241 /* Max Throughput. */
242 info->default_rxportconf.ring_size = 2048;
243 info->default_txportconf.ring_size = 2048;
246 info->default_rxportconf.nb_queues = 8;
247 info->default_txportconf.nb_queues = 8;
248 if (dev->data->nb_rx_queues > 2 ||
249 dev->data->nb_tx_queues > 2) {
250 /* Max Throughput. */
251 info->default_rxportconf.ring_size = 4096;
252 info->default_txportconf.ring_size = 4096;
258 * Sets tx mbuf limiting parameters.
261 * Pointer to Ethernet device.
263 * Info structure output buffer.
266 mlx5_set_txlimit_params(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)
268 struct mlx5_priv *priv = dev->data->dev_private;
269 struct mlx5_port_config *config = &priv->config;
273 inlen = (config->txq_inline_max == MLX5_ARG_UNSET) ?
274 MLX5_SEND_DEF_INLINE_LEN :
275 (unsigned int)config->txq_inline_max;
276 MLX5_ASSERT(config->txq_inline_min >= 0);
277 inlen = RTE_MAX(inlen, (unsigned int)config->txq_inline_min);
278 inlen = RTE_MIN(inlen, MLX5_WQE_SIZE_MAX +
279 MLX5_ESEG_MIN_INLINE_SIZE -
282 MLX5_WQE_DSEG_SIZE * 2);
283 nb_max = (MLX5_WQE_SIZE_MAX +
284 MLX5_ESEG_MIN_INLINE_SIZE -
288 inlen) / MLX5_WSEG_SIZE;
289 info->tx_desc_lim.nb_seg_max = nb_max;
290 info->tx_desc_lim.nb_mtu_seg_max = nb_max;
294 * DPDK callback to get information about the device.
297 * Pointer to Ethernet device structure.
299 * Info structure output buffer.
302 mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)
304 struct mlx5_priv *priv = dev->data->dev_private;
307 /* FIXME: we should ask the device for these values. */
308 info->min_rx_bufsize = 32;
309 info->max_rx_pktlen = 65536;
310 info->max_lro_pkt_size = MLX5_MAX_LRO_SIZE;
312 * Since we need one CQ per QP, the limit is the minimum number
313 * between the two values.
315 max = RTE_MIN(priv->sh->dev_cap.max_cq, priv->sh->dev_cap.max_qp);
316 /* max_rx_queues is uint16_t. */
317 max = RTE_MIN(max, (unsigned int)UINT16_MAX);
318 info->max_rx_queues = max;
319 info->max_tx_queues = max;
320 info->max_mac_addrs = MLX5_MAX_UC_MAC_ADDRESSES;
321 info->rx_queue_offload_capa = mlx5_get_rx_queue_offloads(dev);
322 info->rx_seg_capa.max_nseg = MLX5_MAX_RXQ_NSEG;
323 info->rx_seg_capa.multi_pools = !priv->config.mprq.enabled;
324 info->rx_seg_capa.offset_allowed = !priv->config.mprq.enabled;
325 info->rx_seg_capa.offset_align_log2 = 0;
326 info->rx_offload_capa = (mlx5_get_rx_port_offloads() |
327 info->rx_queue_offload_capa);
328 info->tx_offload_capa = mlx5_get_tx_port_offloads(dev);
329 info->dev_capa = RTE_ETH_DEV_CAPA_FLOW_SHARED_OBJECT_KEEP;
330 info->if_index = mlx5_ifindex(dev);
331 info->reta_size = priv->reta_idx_n ?
332 priv->reta_idx_n : priv->sh->dev_cap.ind_table_max_size;
333 info->hash_key_size = MLX5_RSS_HASH_KEY_LEN;
334 info->speed_capa = priv->link_speed_capa;
335 info->flow_type_rss_offloads = ~MLX5_RSS_HF_MASK;
336 mlx5_set_default_params(dev, info);
337 mlx5_set_txlimit_params(dev, info);
338 if (priv->sh->cdev->config.hca_attr.mem_rq_rmp &&
339 priv->obj_ops.rxq_obj_new == devx_obj_ops.rxq_obj_new)
340 info->dev_capa |= RTE_ETH_DEV_CAPA_RXQ_SHARE;
341 info->switch_info.name = dev->data->name;
342 info->switch_info.domain_id = priv->domain_id;
343 info->switch_info.port_id = priv->representor_id;
344 info->switch_info.rx_domain = 0; /* No sub Rx domains. */
345 if (priv->representor) {
348 MLX5_ETH_FOREACH_DEV(port_id, dev->device) {
349 struct mlx5_priv *opriv =
350 rte_eth_devices[port_id].data->dev_private;
353 opriv->representor ||
354 opriv->sh != priv->sh ||
355 opriv->domain_id != priv->domain_id)
358 * Override switch name with that of the master
361 info->switch_info.name = opriv->dev_data->name;
369 * Calculate representor ID from port switch info.
371 * Uint16 representor ID bits definition:
379 * Use this type if port is HPF.
382 * Encoded representor ID.
385 mlx5_representor_id_encode(const struct mlx5_switch_info *info,
386 enum rte_eth_representor_type hpf_type)
388 enum rte_eth_representor_type type = RTE_ETH_REPRESENTOR_VF;
389 uint16_t repr = info->port_name;
391 if (info->representor == 0)
393 if (info->name_type == MLX5_PHYS_PORT_NAME_TYPE_PFSF)
394 type = RTE_ETH_REPRESENTOR_SF;
395 if (info->name_type == MLX5_PHYS_PORT_NAME_TYPE_PFHPF) {
399 return MLX5_REPRESENTOR_ID(info->pf_num, type, repr);
403 * DPDK callback to get information about representor.
405 * Representor ID bits definition:
411 * Pointer to Ethernet device structure.
413 * Nullable info structure output buffer.
416 * negative on error, or the number of representor ranges.
419 mlx5_representor_info_get(struct rte_eth_dev *dev,
420 struct rte_eth_representor_info *info)
422 struct mlx5_priv *priv = dev->data->dev_private;
423 int n_type = 4; /* Representor types, VF, HPF@VF, SF and HPF@SF. */
424 int n_pf = 2; /* Number of PFs. */
431 n_entries = n_type * n_pf;
432 if ((uint32_t)n_entries > info->nb_ranges_alloc)
433 n_entries = info->nb_ranges_alloc;
435 info->controller = 0;
436 info->pf = priv->pf_bond >= 0 ? priv->pf_bond : 0;
437 for (pf = 0; pf < n_pf; ++pf) {
439 info->ranges[i].type = RTE_ETH_REPRESENTOR_VF;
440 info->ranges[i].controller = 0;
441 info->ranges[i].pf = pf;
442 info->ranges[i].vf = 0;
443 info->ranges[i].id_base =
444 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, 0);
445 info->ranges[i].id_end =
446 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1);
447 snprintf(info->ranges[i].name,
448 sizeof(info->ranges[i].name), "pf%dvf", pf);
452 /* HPF range of VF type. */
453 info->ranges[i].type = RTE_ETH_REPRESENTOR_VF;
454 info->ranges[i].controller = 0;
455 info->ranges[i].pf = pf;
456 info->ranges[i].vf = UINT16_MAX;
457 info->ranges[i].id_base =
458 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1);
459 info->ranges[i].id_end =
460 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1);
461 snprintf(info->ranges[i].name,
462 sizeof(info->ranges[i].name), "pf%dvf", pf);
467 info->ranges[i].type = RTE_ETH_REPRESENTOR_SF;
468 info->ranges[i].controller = 0;
469 info->ranges[i].pf = pf;
470 info->ranges[i].vf = 0;
471 info->ranges[i].id_base =
472 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, 0);
473 info->ranges[i].id_end =
474 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1);
475 snprintf(info->ranges[i].name,
476 sizeof(info->ranges[i].name), "pf%dsf", pf);
480 /* HPF range of SF type. */
481 info->ranges[i].type = RTE_ETH_REPRESENTOR_SF;
482 info->ranges[i].controller = 0;
483 info->ranges[i].pf = pf;
484 info->ranges[i].vf = UINT16_MAX;
485 info->ranges[i].id_base =
486 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1);
487 info->ranges[i].id_end =
488 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1);
489 snprintf(info->ranges[i].name,
490 sizeof(info->ranges[i].name), "pf%dsf", pf);
497 return n_type * n_pf;
501 * Get firmware version of a device.
504 * Ethernet device port.
506 * String output allocated by caller.
508 * Size of the output string, including terminating null byte.
511 * 0 on success, or the size of the non truncated string if too big.
514 mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size)
516 struct mlx5_priv *priv = dev->data->dev_private;
517 struct mlx5_dev_cap *attr = &priv->sh->dev_cap;
518 size_t size = strnlen(attr->fw_ver, sizeof(attr->fw_ver)) + 1;
523 strlcpy(fw_ver, attr->fw_ver, fw_size);
528 * Get supported packet types.
531 * Pointer to Ethernet device structure.
534 * A pointer to the supported Packet types array.
537 mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev)
539 static const uint32_t ptypes[] = {
540 /* refers to rxq_cq_to_pkt_type() */
542 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
543 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
544 RTE_PTYPE_L4_NONFRAG,
548 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
549 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
550 RTE_PTYPE_INNER_L4_NONFRAG,
551 RTE_PTYPE_INNER_L4_FRAG,
552 RTE_PTYPE_INNER_L4_TCP,
553 RTE_PTYPE_INNER_L4_UDP,
557 if (dev->rx_pkt_burst == mlx5_rx_burst ||
558 dev->rx_pkt_burst == mlx5_rx_burst_mprq ||
559 dev->rx_pkt_burst == mlx5_rx_burst_vec ||
560 dev->rx_pkt_burst == mlx5_rx_burst_mprq_vec)
566 * DPDK callback to change the MTU.
569 * Pointer to Ethernet device structure.
574 * 0 on success, a negative errno value otherwise and rte_errno is set.
577 mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
579 struct mlx5_priv *priv = dev->data->dev_private;
580 uint16_t kern_mtu = 0;
583 ret = mlx5_get_mtu(dev, &kern_mtu);
586 /* Set kernel interface MTU first. */
587 ret = mlx5_set_mtu(dev, mtu);
590 ret = mlx5_get_mtu(dev, &kern_mtu);
593 if (kern_mtu == mtu) {
595 DRV_LOG(DEBUG, "port %u adapter MTU set to %u",
596 dev->data->port_id, mtu);
604 * Configure the RX function to use.
607 * Pointer to private data structure.
610 * Pointer to selected Rx burst function.
613 mlx5_select_rx_function(struct rte_eth_dev *dev)
615 eth_rx_burst_t rx_pkt_burst = mlx5_rx_burst;
617 MLX5_ASSERT(dev != NULL);
618 if (mlx5_check_vec_rx_support(dev) > 0) {
619 if (mlx5_mprq_enabled(dev)) {
620 rx_pkt_burst = mlx5_rx_burst_mprq_vec;
621 DRV_LOG(DEBUG, "port %u selected vectorized"
622 " MPRQ Rx function", dev->data->port_id);
624 rx_pkt_burst = mlx5_rx_burst_vec;
625 DRV_LOG(DEBUG, "port %u selected vectorized"
626 " SPRQ Rx function", dev->data->port_id);
628 } else if (mlx5_mprq_enabled(dev)) {
629 rx_pkt_burst = mlx5_rx_burst_mprq;
630 DRV_LOG(DEBUG, "port %u selected MPRQ Rx function",
633 DRV_LOG(DEBUG, "port %u selected SPRQ Rx function",
640 * Get the E-Switch parameters by port id.
645 * Device port id is valid, skip check. This flag is useful
646 * when trials are performed from probing and device is not
647 * flagged as valid yet (in attaching process).
648 * @param[out] es_domain_id
649 * E-Switch domain id.
650 * @param[out] es_port_id
651 * The port id of the port in the E-Switch.
654 * pointer to device private data structure containing data needed
655 * on success, NULL otherwise and rte_errno is set.
658 mlx5_port_to_eswitch_info(uint16_t port, bool valid)
660 struct rte_eth_dev *dev;
661 struct mlx5_priv *priv;
663 if (port >= RTE_MAX_ETHPORTS) {
667 if (!valid && !rte_eth_dev_is_valid_port(port)) {
671 dev = &rte_eth_devices[port];
672 priv = dev->data->dev_private;
673 if (!priv->sh->esw_mode) {
681 * Get the E-Switch parameters by device instance.
685 * @param[out] es_domain_id
686 * E-Switch domain id.
687 * @param[out] es_port_id
688 * The port id of the port in the E-Switch.
691 * pointer to device private data structure containing data needed
692 * on success, NULL otherwise and rte_errno is set.
695 mlx5_dev_to_eswitch_info(struct rte_eth_dev *dev)
697 struct mlx5_priv *priv;
699 priv = dev->data->dev_private;
700 if (!priv->sh->esw_mode) {
708 * DPDK callback to retrieve hairpin capabilities.
711 * Pointer to Ethernet device structure.
713 * Storage for hairpin capability data.
716 * 0 on success, a negative errno value otherwise and rte_errno is set.
719 mlx5_hairpin_cap_get(struct rte_eth_dev *dev, struct rte_eth_hairpin_cap *cap)
721 struct mlx5_priv *priv = dev->data->dev_private;
723 if (!mlx5_devx_obj_ops_en(priv->sh)) {
727 cap->max_nb_queues = UINT16_MAX;
728 cap->max_rx_2_tx = 1;
729 cap->max_tx_2_rx = 1;
730 cap->max_nb_desc = 8192;