1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
13 #include <ethdev_driver.h>
14 #include <rte_bus_pci.h>
16 #include <rte_common.h>
17 #include <rte_interrupts.h>
18 #include <rte_malloc.h>
19 #include <rte_string_fns.h>
20 #include <rte_rwlock.h>
21 #include <rte_cycles.h>
23 #include <mlx5_malloc.h>
25 #include "mlx5_rxtx.h"
28 #include "mlx5_autoconf.h"
31 * Get the interface index from device name.
34 * Pointer to Ethernet device.
37 * Nonzero interface index on success, zero otherwise and rte_errno is set.
40 mlx5_ifindex(const struct rte_eth_dev *dev)
42 struct mlx5_priv *priv = dev->data->dev_private;
46 MLX5_ASSERT(priv->if_index);
47 if (priv->master && priv->sh->bond.ifindex > 0)
48 ifindex = priv->sh->bond.ifindex;
50 ifindex = priv->if_index;
57 * DPDK callback for Ethernet device configuration.
60 * Pointer to Ethernet device structure.
63 * 0 on success, a negative errno value otherwise and rte_errno is set.
66 mlx5_dev_configure(struct rte_eth_dev *dev)
68 struct mlx5_priv *priv = dev->data->dev_private;
69 unsigned int rxqs_n = dev->data->nb_rx_queues;
70 unsigned int txqs_n = dev->data->nb_tx_queues;
71 const uint8_t use_app_rss_key =
72 !!dev->data->dev_conf.rx_adv_conf.rss_conf.rss_key;
75 if (use_app_rss_key &&
76 (dev->data->dev_conf.rx_adv_conf.rss_conf.rss_key_len !=
77 MLX5_RSS_HASH_KEY_LEN)) {
78 DRV_LOG(ERR, "port %u RSS key len must be %s Bytes long",
79 dev->data->port_id, RTE_STR(MLX5_RSS_HASH_KEY_LEN));
83 priv->rss_conf.rss_key =
84 mlx5_realloc(priv->rss_conf.rss_key, MLX5_MEM_RTE,
85 MLX5_RSS_HASH_KEY_LEN, 0, SOCKET_ID_ANY);
86 if (!priv->rss_conf.rss_key) {
87 DRV_LOG(ERR, "port %u cannot allocate RSS hash key memory (%u)",
88 dev->data->port_id, rxqs_n);
93 if ((dev->data->dev_conf.txmode.offloads &
94 DEV_TX_OFFLOAD_SEND_ON_TIMESTAMP) &&
95 rte_mbuf_dyn_tx_timestamp_register(NULL, NULL) != 0) {
96 DRV_LOG(ERR, "port %u cannot register Tx timestamp field/flag",
100 memcpy(priv->rss_conf.rss_key,
102 dev->data->dev_conf.rx_adv_conf.rss_conf.rss_key :
103 rss_hash_default_key,
104 MLX5_RSS_HASH_KEY_LEN);
105 priv->rss_conf.rss_key_len = MLX5_RSS_HASH_KEY_LEN;
106 priv->rss_conf.rss_hf = dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf;
107 priv->rxqs = (void *)dev->data->rx_queues;
108 priv->txqs = (void *)dev->data->tx_queues;
109 if (txqs_n != priv->txqs_n) {
110 DRV_LOG(INFO, "port %u Tx queues number update: %u -> %u",
111 dev->data->port_id, priv->txqs_n, txqs_n);
112 priv->txqs_n = txqs_n;
114 if (rxqs_n > priv->config.ind_table_max_size) {
115 DRV_LOG(ERR, "port %u cannot handle this many Rx queues (%u)",
116 dev->data->port_id, rxqs_n);
120 if (rxqs_n != priv->rxqs_n) {
121 DRV_LOG(INFO, "port %u Rx queues number update: %u -> %u",
122 dev->data->port_id, priv->rxqs_n, rxqs_n);
123 priv->rxqs_n = rxqs_n;
125 priv->skip_default_rss_reta = 0;
126 ret = mlx5_proc_priv_init(dev);
133 * Configure default RSS reta.
136 * Pointer to Ethernet device structure.
139 * 0 on success, a negative errno value otherwise and rte_errno is set.
142 mlx5_dev_configure_rss_reta(struct rte_eth_dev *dev)
144 struct mlx5_priv *priv = dev->data->dev_private;
145 unsigned int rxqs_n = dev->data->nb_rx_queues;
148 unsigned int reta_idx_n;
150 unsigned int *rss_queue_arr = NULL;
151 unsigned int rss_queue_n = 0;
153 if (priv->skip_default_rss_reta)
155 rss_queue_arr = mlx5_malloc(0, rxqs_n * sizeof(unsigned int), 0,
157 if (!rss_queue_arr) {
158 DRV_LOG(ERR, "port %u cannot allocate RSS queue list (%u)",
159 dev->data->port_id, rxqs_n);
163 for (i = 0, j = 0; i < rxqs_n; i++) {
164 struct mlx5_rxq_data *rxq_data;
165 struct mlx5_rxq_ctrl *rxq_ctrl;
167 rxq_data = (*priv->rxqs)[i];
168 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
169 if (rxq_ctrl && rxq_ctrl->type == MLX5_RXQ_TYPE_STANDARD)
170 rss_queue_arr[j++] = i;
173 if (rss_queue_n > priv->config.ind_table_max_size) {
174 DRV_LOG(ERR, "port %u cannot handle this many Rx queues (%u)",
175 dev->data->port_id, rss_queue_n);
177 mlx5_free(rss_queue_arr);
180 DRV_LOG(INFO, "port %u Rx queues number update: %u -> %u",
181 dev->data->port_id, priv->rxqs_n, rxqs_n);
182 priv->rxqs_n = rxqs_n;
184 * If the requested number of RX queues is not a power of two,
185 * use the maximum indirection table size for better balancing.
186 * The result is always rounded to the next power of two.
188 reta_idx_n = (1 << log2above((rss_queue_n & (rss_queue_n - 1)) ?
189 priv->config.ind_table_max_size :
191 ret = mlx5_rss_reta_index_resize(dev, reta_idx_n);
193 mlx5_free(rss_queue_arr);
197 * When the number of RX queues is not a power of two,
198 * the remaining table entries are padded with reused WQs
199 * and hashes are not spread uniformly.
201 for (i = 0, j = 0; (i != reta_idx_n); ++i) {
202 (*priv->reta_idx)[i] = rss_queue_arr[j];
203 if (++j == rss_queue_n)
206 mlx5_free(rss_queue_arr);
211 * Sets default tuning parameters.
214 * Pointer to Ethernet device.
216 * Info structure output buffer.
219 mlx5_set_default_params(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)
221 struct mlx5_priv *priv = dev->data->dev_private;
223 /* Minimum CPU utilization. */
224 info->default_rxportconf.ring_size = 256;
225 info->default_txportconf.ring_size = 256;
226 info->default_rxportconf.burst_size = MLX5_RX_DEFAULT_BURST;
227 info->default_txportconf.burst_size = MLX5_TX_DEFAULT_BURST;
228 if ((priv->link_speed_capa & ETH_LINK_SPEED_200G) |
229 (priv->link_speed_capa & ETH_LINK_SPEED_100G)) {
230 info->default_rxportconf.nb_queues = 16;
231 info->default_txportconf.nb_queues = 16;
232 if (dev->data->nb_rx_queues > 2 ||
233 dev->data->nb_tx_queues > 2) {
234 /* Max Throughput. */
235 info->default_rxportconf.ring_size = 2048;
236 info->default_txportconf.ring_size = 2048;
239 info->default_rxportconf.nb_queues = 8;
240 info->default_txportconf.nb_queues = 8;
241 if (dev->data->nb_rx_queues > 2 ||
242 dev->data->nb_tx_queues > 2) {
243 /* Max Throughput. */
244 info->default_rxportconf.ring_size = 4096;
245 info->default_txportconf.ring_size = 4096;
251 * Sets tx mbuf limiting parameters.
254 * Pointer to Ethernet device.
256 * Info structure output buffer.
259 mlx5_set_txlimit_params(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)
261 struct mlx5_priv *priv = dev->data->dev_private;
262 struct mlx5_dev_config *config = &priv->config;
266 inlen = (config->txq_inline_max == MLX5_ARG_UNSET) ?
267 MLX5_SEND_DEF_INLINE_LEN :
268 (unsigned int)config->txq_inline_max;
269 MLX5_ASSERT(config->txq_inline_min >= 0);
270 inlen = RTE_MAX(inlen, (unsigned int)config->txq_inline_min);
271 inlen = RTE_MIN(inlen, MLX5_WQE_SIZE_MAX +
272 MLX5_ESEG_MIN_INLINE_SIZE -
275 MLX5_WQE_DSEG_SIZE * 2);
276 nb_max = (MLX5_WQE_SIZE_MAX +
277 MLX5_ESEG_MIN_INLINE_SIZE -
281 inlen) / MLX5_WSEG_SIZE;
282 info->tx_desc_lim.nb_seg_max = nb_max;
283 info->tx_desc_lim.nb_mtu_seg_max = nb_max;
287 * DPDK callback to get information about the device.
290 * Pointer to Ethernet device structure.
292 * Info structure output buffer.
295 mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)
297 struct mlx5_priv *priv = dev->data->dev_private;
298 struct mlx5_dev_config *config = &priv->config;
301 /* FIXME: we should ask the device for these values. */
302 info->min_rx_bufsize = 32;
303 info->max_rx_pktlen = 65536;
304 info->max_lro_pkt_size = MLX5_MAX_LRO_SIZE;
306 * Since we need one CQ per QP, the limit is the minimum number
307 * between the two values.
309 max = RTE_MIN(priv->sh->device_attr.max_cq,
310 priv->sh->device_attr.max_qp);
311 /* max_rx_queues is uint16_t. */
312 max = RTE_MIN(max, (unsigned int)UINT16_MAX);
313 info->max_rx_queues = max;
314 info->max_tx_queues = max;
315 info->max_mac_addrs = MLX5_MAX_UC_MAC_ADDRESSES;
316 info->rx_queue_offload_capa = mlx5_get_rx_queue_offloads(dev);
317 info->rx_seg_capa.max_nseg = MLX5_MAX_RXQ_NSEG;
318 info->rx_seg_capa.multi_pools = !config->mprq.enabled;
319 info->rx_seg_capa.offset_allowed = !config->mprq.enabled;
320 info->rx_seg_capa.offset_align_log2 = 0;
321 info->rx_offload_capa = (mlx5_get_rx_port_offloads() |
322 info->rx_queue_offload_capa);
323 info->tx_offload_capa = mlx5_get_tx_port_offloads(dev);
324 info->if_index = mlx5_ifindex(dev);
325 info->reta_size = priv->reta_idx_n ?
326 priv->reta_idx_n : config->ind_table_max_size;
327 info->hash_key_size = MLX5_RSS_HASH_KEY_LEN;
328 info->speed_capa = priv->link_speed_capa;
329 info->flow_type_rss_offloads = ~MLX5_RSS_HF_MASK;
330 mlx5_set_default_params(dev, info);
331 mlx5_set_txlimit_params(dev, info);
332 info->switch_info.name = dev->data->name;
333 info->switch_info.domain_id = priv->domain_id;
334 info->switch_info.port_id = priv->representor_id;
335 if (priv->representor) {
338 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
339 struct mlx5_priv *opriv =
340 rte_eth_devices[port_id].data->dev_private;
343 opriv->representor ||
344 opriv->sh != priv->sh ||
345 opriv->domain_id != priv->domain_id)
348 * Override switch name with that of the master
351 info->switch_info.name = opriv->dev_data->name;
359 * Calculate representor ID from port switch info.
361 * Uint16 representor ID bits definition:
369 * Use this type if port is HPF.
372 * Encoded representor ID.
375 mlx5_representor_id_encode(const struct mlx5_switch_info *info,
376 enum rte_eth_representor_type hpf_type)
378 enum rte_eth_representor_type type = RTE_ETH_REPRESENTOR_VF;
379 uint16_t repr = info->port_name;
381 if (info->representor == 0)
383 if (info->name_type == MLX5_PHYS_PORT_NAME_TYPE_PFSF)
384 type = RTE_ETH_REPRESENTOR_SF;
385 if (info->name_type == MLX5_PHYS_PORT_NAME_TYPE_PFHPF) {
389 return MLX5_REPRESENTOR_ID(info->pf_num, type, repr);
393 * DPDK callback to get information about representor.
395 * Representor ID bits definition:
401 * Pointer to Ethernet device structure.
403 * Nullable info structure output buffer.
406 * negative on error, or the number of representor ranges.
409 mlx5_representor_info_get(struct rte_eth_dev *dev,
410 struct rte_eth_representor_info *info)
412 struct mlx5_priv *priv = dev->data->dev_private;
413 int n_type = 4; /* Representor types, VF, HPF@VF, SF and HPF@SF. */
414 int n_pf = 2; /* Number of PFs. */
419 info->controller = 0;
420 info->pf = priv->pf_bond >= 0 ? priv->pf_bond : 0;
421 for (pf = 0; pf < n_pf; ++pf) {
423 info->ranges[i].type = RTE_ETH_REPRESENTOR_VF;
424 info->ranges[i].controller = 0;
425 info->ranges[i].pf = pf;
426 info->ranges[i].vf = 0;
427 info->ranges[i].id_base =
428 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, 0);
429 info->ranges[i].id_end =
430 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1);
431 snprintf(info->ranges[i].name,
432 sizeof(info->ranges[i].name), "pf%dvf", pf);
434 /* HPF range of VF type. */
435 info->ranges[i].type = RTE_ETH_REPRESENTOR_VF;
436 info->ranges[i].controller = 0;
437 info->ranges[i].pf = pf;
438 info->ranges[i].vf = UINT16_MAX;
439 info->ranges[i].id_base =
440 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1);
441 info->ranges[i].id_end =
442 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1);
443 snprintf(info->ranges[i].name,
444 sizeof(info->ranges[i].name), "pf%dvf", pf);
447 info->ranges[i].type = RTE_ETH_REPRESENTOR_SF;
448 info->ranges[i].controller = 0;
449 info->ranges[i].pf = pf;
450 info->ranges[i].vf = 0;
451 info->ranges[i].id_base =
452 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, 0);
453 info->ranges[i].id_end =
454 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1);
455 snprintf(info->ranges[i].name,
456 sizeof(info->ranges[i].name), "pf%dsf", pf);
458 /* HPF range of SF type. */
459 info->ranges[i].type = RTE_ETH_REPRESENTOR_SF;
460 info->ranges[i].controller = 0;
461 info->ranges[i].pf = pf;
462 info->ranges[i].vf = UINT16_MAX;
463 info->ranges[i].id_base =
464 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1);
465 info->ranges[i].id_end =
466 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1);
467 snprintf(info->ranges[i].name,
468 sizeof(info->ranges[i].name), "pf%dsf", pf);
472 return n_type * n_pf;
476 * Get firmware version of a device.
479 * Ethernet device port.
481 * String output allocated by caller.
483 * Size of the output string, including terminating null byte.
486 * 0 on success, or the size of the non truncated string if too big.
489 mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size)
491 struct mlx5_priv *priv = dev->data->dev_private;
492 struct mlx5_dev_attr *attr = &priv->sh->device_attr;
493 size_t size = strnlen(attr->fw_ver, sizeof(attr->fw_ver)) + 1;
498 strlcpy(fw_ver, attr->fw_ver, fw_size);
503 * Get supported packet types.
506 * Pointer to Ethernet device structure.
509 * A pointer to the supported Packet types array.
512 mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev)
514 static const uint32_t ptypes[] = {
515 /* refers to rxq_cq_to_pkt_type() */
517 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
518 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
519 RTE_PTYPE_L4_NONFRAG,
523 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
524 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
525 RTE_PTYPE_INNER_L4_NONFRAG,
526 RTE_PTYPE_INNER_L4_FRAG,
527 RTE_PTYPE_INNER_L4_TCP,
528 RTE_PTYPE_INNER_L4_UDP,
532 if (dev->rx_pkt_burst == mlx5_rx_burst ||
533 dev->rx_pkt_burst == mlx5_rx_burst_mprq ||
534 dev->rx_pkt_burst == mlx5_rx_burst_vec ||
535 dev->rx_pkt_burst == mlx5_rx_burst_mprq_vec)
541 * DPDK callback to change the MTU.
544 * Pointer to Ethernet device structure.
549 * 0 on success, a negative errno value otherwise and rte_errno is set.
552 mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
554 struct mlx5_priv *priv = dev->data->dev_private;
555 uint16_t kern_mtu = 0;
558 ret = mlx5_get_mtu(dev, &kern_mtu);
561 /* Set kernel interface MTU first. */
562 ret = mlx5_set_mtu(dev, mtu);
565 ret = mlx5_get_mtu(dev, &kern_mtu);
568 if (kern_mtu == mtu) {
570 DRV_LOG(DEBUG, "port %u adapter MTU set to %u",
571 dev->data->port_id, mtu);
579 * Configure the RX function to use.
582 * Pointer to private data structure.
585 * Pointer to selected Rx burst function.
588 mlx5_select_rx_function(struct rte_eth_dev *dev)
590 eth_rx_burst_t rx_pkt_burst = mlx5_rx_burst;
592 MLX5_ASSERT(dev != NULL);
593 if (mlx5_check_vec_rx_support(dev) > 0) {
594 if (mlx5_mprq_enabled(dev)) {
595 rx_pkt_burst = mlx5_rx_burst_mprq_vec;
596 DRV_LOG(DEBUG, "port %u selected vectorized"
597 " MPRQ Rx function", dev->data->port_id);
599 rx_pkt_burst = mlx5_rx_burst_vec;
600 DRV_LOG(DEBUG, "port %u selected vectorized"
601 " SPRQ Rx function", dev->data->port_id);
603 } else if (mlx5_mprq_enabled(dev)) {
604 rx_pkt_burst = mlx5_rx_burst_mprq;
605 DRV_LOG(DEBUG, "port %u selected MPRQ Rx function",
608 DRV_LOG(DEBUG, "port %u selected SPRQ Rx function",
615 * Get the E-Switch parameters by port id.
620 * Device port id is valid, skip check. This flag is useful
621 * when trials are performed from probing and device is not
622 * flagged as valid yet (in attaching process).
623 * @param[out] es_domain_id
624 * E-Switch domain id.
625 * @param[out] es_port_id
626 * The port id of the port in the E-Switch.
629 * pointer to device private data structure containing data needed
630 * on success, NULL otherwise and rte_errno is set.
633 mlx5_port_to_eswitch_info(uint16_t port, bool valid)
635 struct rte_eth_dev *dev;
636 struct mlx5_priv *priv;
638 if (port >= RTE_MAX_ETHPORTS) {
642 if (!valid && !rte_eth_dev_is_valid_port(port)) {
646 dev = &rte_eth_devices[port];
647 priv = dev->data->dev_private;
648 if (!(priv->representor || priv->master)) {
656 * Get the E-Switch parameters by device instance.
660 * @param[out] es_domain_id
661 * E-Switch domain id.
662 * @param[out] es_port_id
663 * The port id of the port in the E-Switch.
666 * pointer to device private data structure containing data needed
667 * on success, NULL otherwise and rte_errno is set.
670 mlx5_dev_to_eswitch_info(struct rte_eth_dev *dev)
672 struct mlx5_priv *priv;
674 priv = dev->data->dev_private;
675 if (!(priv->representor || priv->master)) {
683 * DPDK callback to retrieve hairpin capabilities.
686 * Pointer to Ethernet device structure.
688 * Storage for hairpin capability data.
691 * 0 on success, a negative errno value otherwise and rte_errno is set.
694 mlx5_hairpin_cap_get(struct rte_eth_dev *dev, struct rte_eth_hairpin_cap *cap)
696 struct mlx5_priv *priv = dev->data->dev_private;
697 struct mlx5_dev_config *config = &priv->config;
699 if (!priv->sh->devx || !config->dest_tir || !config->dv_flow_en) {
703 cap->max_nb_queues = UINT16_MAX;
704 cap->max_rx_2_tx = 1;
705 cap->max_tx_2_rx = 1;
706 cap->max_nb_desc = 8192;